]>
Commit | Line | Data |
---|---|---|
4b6da8e7 | 1 | /* Tuning model description for AArch64 architecture. |
a945c346 | 2 | Copyright (C) 2009-2024 Free Software Foundation, Inc. |
4b6da8e7 TC |
3 | |
4 | This file is part of GCC. | |
5 | ||
6 | GCC is free software; you can redistribute it and/or modify it | |
7 | under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GCC is distributed in the hope that it will be useful, but | |
12 | WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GCC; see the file COPYING3. If not see | |
18 | <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef GCC_AARCH64_H_A64FX | |
21 | #define GCC_AARCH64_H_A64FX | |
22 | ||
23 | #include "generic.h" | |
24 | ||
25 | static const struct cpu_addrcost_table a64fx_addrcost_table = | |
26 | { | |
27 | { | |
28 | 1, /* hi */ | |
29 | 1, /* si */ | |
30 | 1, /* di */ | |
31 | 2, /* ti */ | |
32 | }, | |
33 | 0, /* pre_modify */ | |
34 | 0, /* post_modify */ | |
35 | 0, /* post_modify_ld3_st3 */ | |
36 | 0, /* post_modify_ld4_st4 */ | |
37 | 2, /* register_offset */ | |
38 | 3, /* register_sextend */ | |
39 | 3, /* register_zextend */ | |
40 | 0, /* imm_offset */ | |
41 | }; | |
42 | ||
43 | static const struct cpu_regmove_cost a64fx_regmove_cost = | |
44 | { | |
45 | 1, /* GP2GP */ | |
46 | /* Avoid the use of slow int<->fp moves for spilling by setting | |
47 | their cost higher than memmov_cost. */ | |
48 | 5, /* GP2FP */ | |
49 | 7, /* FP2GP */ | |
50 | 2 /* FP2FP */ | |
51 | }; | |
52 | ||
53 | static const advsimd_vec_cost a64fx_advsimd_vector_cost = | |
54 | { | |
55 | 2, /* int_stmt_cost */ | |
56 | 5, /* fp_stmt_cost */ | |
57 | 0, /* ld2_st2_permute_cost */ | |
58 | 0, /* ld3_st3_permute_cost */ | |
59 | 0, /* ld4_st4_permute_cost */ | |
60 | 3, /* permute_cost */ | |
61 | 13, /* reduc_i8_cost */ | |
62 | 13, /* reduc_i16_cost */ | |
63 | 13, /* reduc_i32_cost */ | |
64 | 13, /* reduc_i64_cost */ | |
65 | 13, /* reduc_f16_cost */ | |
66 | 13, /* reduc_f32_cost */ | |
67 | 13, /* reduc_f64_cost */ | |
68 | 13, /* store_elt_extra_cost */ | |
69 | 13, /* vec_to_scalar_cost */ | |
70 | 4, /* scalar_to_vec_cost */ | |
71 | 6, /* align_load_cost */ | |
72 | 6, /* unalign_load_cost */ | |
73 | 1, /* unalign_store_cost */ | |
74 | 1 /* store_cost */ | |
75 | }; | |
76 | ||
77 | static const sve_vec_cost a64fx_sve_vector_cost = | |
78 | { | |
79 | { | |
80 | 2, /* int_stmt_cost */ | |
81 | 5, /* fp_stmt_cost */ | |
82 | 0, /* ld2_st2_permute_cost */ | |
83 | 0, /* ld3_st3_permute_cost */ | |
84 | 0, /* ld4_st4_permute_cost */ | |
85 | 3, /* permute_cost */ | |
86 | 13, /* reduc_i8_cost */ | |
87 | 13, /* reduc_i16_cost */ | |
88 | 13, /* reduc_i32_cost */ | |
89 | 13, /* reduc_i64_cost */ | |
90 | 13, /* reduc_f16_cost */ | |
91 | 13, /* reduc_f32_cost */ | |
92 | 13, /* reduc_f64_cost */ | |
93 | 13, /* store_elt_extra_cost */ | |
94 | 13, /* vec_to_scalar_cost */ | |
95 | 4, /* scalar_to_vec_cost */ | |
96 | 6, /* align_load_cost */ | |
97 | 6, /* unalign_load_cost */ | |
98 | 1, /* unalign_store_cost */ | |
99 | 1 /* store_cost */ | |
100 | }, | |
101 | 13, /* clast_cost */ | |
102 | 13, /* fadda_f16_cost */ | |
103 | 13, /* fadda_f32_cost */ | |
104 | 13, /* fadda_f64_cost */ | |
105 | 64, /* gather_load_x32_cost */ | |
106 | 32, /* gather_load_x64_cost */ | |
107 | 1 /* scatter_store_elt_cost */ | |
108 | }; | |
109 | ||
110 | static const struct cpu_vector_cost a64fx_vector_cost = | |
111 | { | |
112 | 1, /* scalar_int_stmt_cost */ | |
113 | 5, /* scalar_fp_stmt_cost */ | |
114 | 4, /* scalar_load_cost */ | |
115 | 1, /* scalar_store_cost */ | |
116 | 3, /* cond_taken_branch_cost */ | |
117 | 1, /* cond_not_taken_branch_cost */ | |
118 | &a64fx_advsimd_vector_cost, /* advsimd */ | |
119 | &a64fx_sve_vector_cost, /* sve */ | |
120 | nullptr /* issue_info */ | |
121 | }; | |
122 | ||
123 | static const cpu_prefetch_tune a64fx_prefetch_tune = | |
124 | { | |
125 | 8, /* num_slots */ | |
126 | 64, /* l1_cache_size */ | |
127 | 256, /* l1_cache_line_size */ | |
128 | 32768, /* l2_cache_size */ | |
129 | true, /* prefetch_dynamic_strides */ | |
130 | -1, /* minimum_stride */ | |
131 | -1 /* default_opt_level */ | |
132 | }; | |
133 | ||
134 | static const struct tune_params a64fx_tunings = | |
135 | { | |
136 | &a64fx_extra_costs, | |
137 | &a64fx_addrcost_table, | |
138 | &a64fx_regmove_cost, | |
139 | &a64fx_vector_cost, | |
140 | &generic_branch_cost, | |
141 | &generic_approx_modes, | |
142 | SVE_512, /* sve_width */ | |
143 | { 4, /* load_int. */ | |
144 | 4, /* store_int. */ | |
145 | 4, /* load_fp. */ | |
146 | 4, /* store_fp. */ | |
147 | 4, /* load_pred. */ | |
148 | 4 /* store_pred. */ | |
149 | }, /* memmov_cost. */ | |
150 | 7, /* issue_rate */ | |
151 | (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH), /* fusible_ops */ | |
152 | "32", /* function_align. */ | |
153 | "16", /* jump_align. */ | |
154 | "32", /* loop_align. */ | |
155 | 4, /* int_reassoc_width. */ | |
156 | 2, /* fp_reassoc_width. */ | |
157 | 1, /* fma_reassoc_width. */ | |
158 | 2, /* vec_reassoc_width. */ | |
159 | 2, /* min_div_recip_mul_sf. */ | |
160 | 2, /* min_div_recip_mul_df. */ | |
161 | 0, /* max_case_values. */ | |
162 | tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ | |
163 | (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ | |
164 | &a64fx_prefetch_tune, | |
165 | AARCH64_LDP_STP_POLICY_ALWAYS, /* ldp_policy_model. */ | |
166 | AARCH64_LDP_STP_POLICY_ALWAYS /* stp_policy_model. */ | |
167 | }; | |
168 | ||
169 | #endif /* GCC_AARCH64_H_A64FX. */ |