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5944e3a8 1;; Unspec defintions.
a945c346 2;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
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3;; Contributed by ARM Ltd.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
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21;; UNSPEC Usage:
22;; Note: sin and cos are no-longer used.
23;; Unspec enumerators for Neon are defined in neon.md.
24;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
25
26(define_c_enum "unspec" [
27 UNSPEC_PUSH_MULT ; `push multiple' operation:
28 ; operand 0 is the first register,
29 ; subsequent registers are in parallel (use ...)
30 ; expressions.
31 UNSPEC_PIC_SYM ; A symbol that has been treated properly for pic
32 ; usage, that is, we will add the pic_register
33 ; value to it before trying to dereference it.
34 UNSPEC_PIC_BASE ; Add PC and all but the last operand together,
35 ; The last operand is the number of a PIC_LABEL
36 ; that points at the containing instruction.
37 UNSPEC_PRLG_STK ; A special barrier that prevents frame accesses
38 ; being scheduled before the stack adjustment insn.
39 UNSPEC_REGISTER_USE ; As USE insns are not meaningful after reload,
40 ; this unspec is used to prevent the deletion of
41 ; instructions setting registers for EH handling
42 ; and stack frame generation. Operand 0 is the
43 ; register to "use".
44 UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode.
45 UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
46 UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction.
47 UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
48 UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction.
49 UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
50 UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction.
51 UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction.
52 UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
53 UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
54 UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
55 UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
56 UNSPEC_TLS ; A symbol that has been treated properly for TLS usage.
57 UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the
58 ; instruction stream.
59 UNSPEC_PIC_OFFSET ; A symbolic 12-bit OFFSET that has been treated
60 ; correctly for PIC usage.
61 UNSPEC_GOTSYM_OFF ; The offset of the start of the GOT from a
62 ; a given symbolic address.
63 UNSPEC_THUMB1_CASESI ; A Thumb1 compressed dispatch-table call.
64 UNSPEC_RBIT ; rbit operation.
65 UNSPEC_SYMBOL_OFFSET ; The offset of the start of the symbol from
66 ; another symbolic address.
67 UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
68 UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access
69 ; unaligned locations, on architectures which support
70 ; that.
71 UNSPEC_UNALIGNED_STORE ; Same for str/strh.
72 UNSPEC_PIC_UNIFIED ; Create a common pic addressing form.
cf16f980 73 UNSPEC_Q_SET ; Represent setting the Q bit.
16155ccf 74 UNSPEC_GE_SET ; Represent setting the GE bits.
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75 UNSPEC_APSR_READ ; Represent reading the APSR.
76
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77 UNSPEC_LL ; Represent an unpaired load-register-exclusive.
78 UNSPEC_VRINTZ ; Represent a float to integral float rounding
79 ; towards zero.
80 UNSPEC_VRINTP ; Represent a float to integral float rounding
81 ; towards +Inf.
82 UNSPEC_VRINTM ; Represent a float to integral float rounding
83 ; towards -Inf.
84 UNSPEC_VRINTR ; Represent a float to integral float rounding
85 ; FPSCR rounding mode.
86 UNSPEC_VRINTX ; Represent a float to integral float rounding
87 ; FPSCR rounding mode and signal inexactness.
88 UNSPEC_VRINTA ; Represent a float to integral float rounding
89 ; towards nearest, ties away from zero.
4fb94ef9 90 UNSPEC_PROBE_STACK ; Probe stack memory reference
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91 UNSPEC_NONSECURE_MEM ; Represent non-secure memory in ARMv8-M with
92 ; security extension
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93 UNSPEC_SP_SET ; Represent the setting of stack protector's canary
94 UNSPEC_SP_TEST ; Represent the testing of stack protector's canary
95 ; against the guard.
8b63716e 96 UNSPEC_PIC_RESTORE ; Use to restore fdpic register
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97
98 UNSPEC_SXTAB16 ; Represent the SXTAB16 operation.
99 UNSPEC_UXTAB16 ; Represent the UXTAB16 operation.
100 UNSPEC_SXTB16 ; Represent the SXTB16 operation.
101 UNSPEC_UXTB16 ; Represent the UXTB16 operation.
102 UNSPEC_QADD8 ; Represent the QADD8 operation.
103 UNSPEC_QSUB8 ; Represent the QSUB8 operation.
104 UNSPEC_SHADD8 ; Represent the SHADD8 operation.
105 UNSPEC_SHSUB8 ; Represent the SHSUB8 operation.
106 UNSPEC_UHADD8 ; Represent the UHADD8 operation.
107 UNSPEC_UHSUB8 ; Represent the UHSUB8 operation.
108 UNSPEC_UQADD8 ; Represent the UQADD8 operation.
109 UNSPEC_UQSUB8 ; Represent the UQSUB8 operation.
110 UNSPEC_QADD16 ; Represent the QADD16 operation.
111 UNSPEC_QASX ; Represent the QASX operation.
112 UNSPEC_QSAX ; Represent the QSAX operation.
113 UNSPEC_QSUB16 ; Represent the QSUB16 operation.
114 UNSPEC_SHADD16 ; Represent the SHADD16 operation.
115 UNSPEC_SHASX ; Represent the SHASX operation.
116 UNSPEC_SHSAX ; Represent the SSAX operation.
117 UNSPEC_SHSUB16 ; Represent the SHSUB16 operation.
118 UNSPEC_UHADD16 ; Represent the UHADD16 operation.
119 UNSPEC_UHASX ; Represent the UHASX operation.
120 UNSPEC_UHSAX ; Represent the USAX operation.
121 UNSPEC_UHSUB16 ; Represent the UHSUB16 operation.
122 UNSPEC_UQADD16 ; Represent the UQADD16 operation.
123 UNSPEC_UQASX ; Represent the UQASX operation.
124 UNSPEC_UQSAX ; Represent the UQSAX operation.
125 UNSPEC_UQSUB16 ; Represent the UQSUB16 operation.
126 UNSPEC_SMUSD ; Represent the SMUSD operation.
127 UNSPEC_SMUSDX ; Represent the SMUSDX operation.
128 UNSPEC_USAD8 ; Represent the USAD8 operation.
129 UNSPEC_USADA8 ; Represent the USADA8 operation.
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130 UNSPEC_SMLALD ; Represent the SMLALD operation.
131 UNSPEC_SMLALDX ; Represent the SMLALDX operation.
132 UNSPEC_SMLSLD ; Represent the SMLSLD operation.
133 UNSPEC_SMLSLDX ; Represent the SMLSLDX operation.
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134 UNSPEC_SMLAWB ; Represent the SMLAWB operation.
135 UNSPEC_SMLAWT ; Represent the SMLAWT operation.
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136 UNSPEC_SEL ; Represent the SEL operation.
137 UNSPEC_SADD8 ; Represent the SADD8 operation.
138 UNSPEC_SSUB8 ; Represent the SSUB8 operation.
139 UNSPEC_UADD8 ; Represent the UADD8 operation.
140 UNSPEC_USUB8 ; Represent the USUB8 operation.
141 UNSPEC_SADD16 ; Represent the SADD16 operation.
142 UNSPEC_SASX ; Represent the SASX operation.
143 UNSPEC_SSAX ; Represent the SSAX operation.
144 UNSPEC_SSUB16 ; Represent the SSUB16 operation.
145 UNSPEC_UADD16 ; Represent the UADD16 operation.
146 UNSPEC_UASX ; Represent the UASX operation.
147 UNSPEC_USAX ; Represent the USAX operation.
148 UNSPEC_USUB16 ; Represent the USUB16 operation.
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149 UNSPEC_SMLAD ; Represent the SMLAD operation.
150 UNSPEC_SMLADX ; Represent the SMLADX operation.
151 UNSPEC_SMLSD ; Represent the SMLSD operation.
152 UNSPEC_SMLSDX ; Represent the SMLSDX operation.
153 UNSPEC_SMUAD ; Represent the SMUAD operation.
154 UNSPEC_SMUADX ; Represent the SMUADX operation.
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155 UNSPEC_SSAT16 ; Represent the SSAT16 operation.
156 UNSPEC_USAT16 ; Represent the USAT16 operation.
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157 UNSPEC_CDE ; Custom Datapath Extension instruction.
158 UNSPEC_CDEA ; Custom Datapath Extension instruction.
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159 UNSPEC_VCDE ; Custom Datapath Extension instruction.
160 UNSPEC_VCDEA ; Custom Datapath Extension instruction.
d2ed233c 161 UNSPEC_DLS ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction
651460b4 162 UNSPEC_PAC_NOP ; Represents PAC signing LR
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163])
164
53cd0ac6 165
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166(define_c_enum "unspec" [
167 UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction.
168 UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction.
169 UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
170 UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
171 UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
172 UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
173 UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
174 UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
175 UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction.
176 UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction.
177 UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
178 UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
c3562f81 179 UNSPEC_GET_FPSCR_NZCVQC ; Represent fetch of FPSCR_nzcvqc content.
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180])
181
182
183;; UNSPEC_VOLATILE Usage:
184
185(define_c_enum "unspecv" [
186 VUNSPEC_BLOCKAGE ; `blockage' insn to prevent scheduling across an
187 ; insn in the code.
188 VUNSPEC_EPILOGUE ; `epilogue' insn, used to represent any part of the
189 ; instruction epilogue sequence that isn't expanded
190 ; into normal RTL. Used for both normal and sibcall
191 ; epilogues.
192 VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
193 ; modes from arm to thumb.
194 VUNSPEC_ALIGN ; `align' insn. Used at the head of a minipool table
195 ; for inlined constants.
196 VUNSPEC_POOL_END ; `end-of-table'. Used to mark the end of a minipool
197 ; table.
198 VUNSPEC_POOL_1 ; `pool-entry(1)'. An entry in the constant pool for
199 ; an 8-bit object.
200 VUNSPEC_POOL_2 ; `pool-entry(2)'. An entry in the constant pool for
201 ; a 16-bit object.
202 VUNSPEC_POOL_4 ; `pool-entry(4)'. An entry in the constant pool for
203 ; a 32-bit object.
204 VUNSPEC_POOL_8 ; `pool-entry(8)'. An entry in the constant pool for
205 ; a 64-bit object.
206 VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for
207 ; a 128-bit object.
208 VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction.
209 VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction.
210 VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN
211 VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions
212 VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions
213 VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions
214 VUNSPEC_EH_RETURN ; Use to override the return address for exception
215 ; handling.
216 VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap.
217 VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange.
218 VUNSPEC_ATOMIC_OP ; Represent an atomic operation.
219 VUNSPEC_LL ; Represent a load-register-exclusive.
74a00288 220 VUNSPEC_LDRD_ATOMIC ; Represent an LDRD used as an atomic DImode load.
79739965 221 VUNSPEC_SC ; Represent a store-register-exclusive.
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222 VUNSPEC_LAX ; Represent a load-register-acquire-exclusive.
223 VUNSPEC_SLX ; Represent a store-register-release-exclusive.
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224 VUNSPEC_LDA ; Represent a load-register-acquire.
225 VUNSPEC_LDR ; Represent a load-register-relaxed.
5ad29f12 226 VUNSPEC_STL ; Represent a store-register-release.
0731889c 227 VUNSPEC_STR ; Represent a store-register-relaxed.
719c8642 228 VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.
f10743d3 229 VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content.
c3562f81 230 VUNSPEC_SET_FPSCR_NZCVQC ; Represent assign of FPSCR_nzcvqc content.
f58101cf 231 VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
d57daa0c
AV
232 VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
233 VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
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AV
234 VUNSPEC_LDC ; Represent the coprocessor ldc instruction.
235 VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction.
236 VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction.
237 VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction.
238 VUNSPEC_STC ; Represent the coprocessor stc instruction.
239 VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
240 VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
241 VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
ecc9a25b
AV
242 VUNSPEC_MCR ; Represent the coprocessor mcr instruction.
243 VUNSPEC_MCR2 ; Represent the coprocessor mcr2 instruction.
244 VUNSPEC_MRC ; Represent the coprocessor mrc instruction.
245 VUNSPEC_MRC2 ; Represent the coprocessor mrc2 instruction.
f3caa118
AV
246 VUNSPEC_MCRR ; Represent the coprocessor mcrr instruction.
247 VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction.
248 VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction.
249 VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction.
bb8b0096 250 VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
cf16f980 251 VUNSPEC_APSR_WRITE ; Represent writing the APSR.
e0e4be48 252 VUNSPEC_VSTR_VLDR ; Represent the vstr/vldr instruction.
9722215a 253 VUNSPEC_CLRM_APSR ; Represent the clearing of APSR with clrm instruction.
0b1c7b27
MI
254 VUNSPEC_VSCCLRM_VPR ; Represent the clearing of VPR with vscclrm
255 ; instruction.
0ab81d9c
MI
256 VUNSPEC_VLSTM ; Represent the lazy store multiple with vlstm
257 ; instruction.
258 VUNSPEC_VLLDM ; Represent the lazy load multiple with vlldm
259 ; instruction.
651460b4
AC
260 VUNSPEC_PACBTI_NOP ; Represents PAC signing LR + valid landing pad
261 VUNSPEC_AUT_NOP ; Represents PAC verifying LR
db6b9a9d 262 VUNSPEC_BTI_NOP ; Represent BTI
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263])
264
265;; Enumerators for NEON unspecs.
266(define_c_enum "unspec" [
267 UNSPEC_ASHIFT_SIGNED
268 UNSPEC_ASHIFT_UNSIGNED
582e2e43
KT
269 UNSPEC_CRC32B
270 UNSPEC_CRC32H
271 UNSPEC_CRC32W
272 UNSPEC_CRC32CB
273 UNSPEC_CRC32CH
274 UNSPEC_CRC32CW
021b5e6b
KT
275 UNSPEC_AESD
276 UNSPEC_AESE
277 UNSPEC_AESIMC
278 UNSPEC_AESMC
bc13384e 279 UNSPEC_AES_PROTECT
021b5e6b
KT
280 UNSPEC_SHA1C
281 UNSPEC_SHA1M
282 UNSPEC_SHA1P
283 UNSPEC_SHA1H
284 UNSPEC_SHA1SU0
285 UNSPEC_SHA1SU1
286 UNSPEC_SHA256H
287 UNSPEC_SHA256H2
288 UNSPEC_SHA256SU0
289 UNSPEC_SHA256SU1
290 UNSPEC_VMULLP64
79739965 291 UNSPEC_LOAD_COUNT
84ae7213
PW
292 UNSPEC_VABAL_S
293 UNSPEC_VABAL_U
94f0f2cc
JG
294 UNSPEC_VABD_F
295 UNSPEC_VABD_S
296 UNSPEC_VABD_U
297 UNSPEC_VABDL_S
298 UNSPEC_VABDL_U
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299 UNSPEC_VADD
300 UNSPEC_VADDHN
94f0f2cc
JG
301 UNSPEC_VRADDHN
302 UNSPEC_VADDL_S
303 UNSPEC_VADDL_U
304 UNSPEC_VADDW_S
305 UNSPEC_VADDW_U
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306 UNSPEC_VBSL
307 UNSPEC_VCAGE
308 UNSPEC_VCAGT
55a9b91b
MW
309 UNSPEC_VCALE
310 UNSPEC_VCALT
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311 UNSPEC_VCEQ
312 UNSPEC_VCGE
313 UNSPEC_VCGEU
314 UNSPEC_VCGT
315 UNSPEC_VCGTU
316 UNSPEC_VCLS
317 UNSPEC_VCONCAT
318 UNSPEC_VCVT
94f0f2cc
JG
319 UNSPEC_VCVT_S
320 UNSPEC_VCVT_U
321 UNSPEC_VCVT_S_N
322 UNSPEC_VCVT_U_N
d403b8d4
MW
323 UNSPEC_VCVT_HF_S_N
324 UNSPEC_VCVT_HF_U_N
325 UNSPEC_VCVT_SI_S_N
326 UNSPEC_VCVT_SI_U_N
327 UNSPEC_VCVTH_S
328 UNSPEC_VCVTH_U
329 UNSPEC_VCVTA_S
330 UNSPEC_VCVTA_U
331 UNSPEC_VCVTM_S
332 UNSPEC_VCVTM_U
333 UNSPEC_VCVTN_S
334 UNSPEC_VCVTN_U
335 UNSPEC_VCVTP_S
336 UNSPEC_VCVTP_U
79739965 337 UNSPEC_VEXT
94f0f2cc
JG
338 UNSPEC_VHADD_S
339 UNSPEC_VHADD_U
340 UNSPEC_VRHADD_S
341 UNSPEC_VRHADD_U
342 UNSPEC_VHSUB_S
343 UNSPEC_VHSUB_U
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344 UNSPEC_VLD1
345 UNSPEC_VLD1_LANE
346 UNSPEC_VLD2
347 UNSPEC_VLD2_DUP
348 UNSPEC_VLD2_LANE
349 UNSPEC_VLD3
350 UNSPEC_VLD3A
351 UNSPEC_VLD3B
352 UNSPEC_VLD3_DUP
353 UNSPEC_VLD3_LANE
354 UNSPEC_VLD4
355 UNSPEC_VLD4A
356 UNSPEC_VLD4B
357 UNSPEC_VLD4_DUP
358 UNSPEC_VLD4_LANE
359 UNSPEC_VMAX
94f0f2cc 360 UNSPEC_VMAX_U
0a18c19f 361 UNSPEC_VMAXNM
79739965 362 UNSPEC_VMIN
94f0f2cc 363 UNSPEC_VMIN_U
0a18c19f 364 UNSPEC_VMINNM
79739965 365 UNSPEC_VMLA
79739965 366 UNSPEC_VMLA_LANE
94f0f2cc
JG
367 UNSPEC_VMLAL_S
368 UNSPEC_VMLAL_U
369 UNSPEC_VMLAL_S_LANE
370 UNSPEC_VMLAL_U_LANE
79739965 371 UNSPEC_VMLS
79739965 372 UNSPEC_VMLS_LANE
94f0f2cc
JG
373 UNSPEC_VMLSL_S
374 UNSPEC_VMLSL_U
375 UNSPEC_VMLSL_S_LANE
376 UNSPEC_VMLSL_U_LANE
79739965 377 UNSPEC_VMLSL_LANE
55a9b91b
MW
378 UNSPEC_VFMA_LANE
379 UNSPEC_VFMS_LANE
94f0f2cc
JG
380 UNSPEC_VMOVL_S
381 UNSPEC_VMOVL_U
79739965
KT
382 UNSPEC_VMOVN
383 UNSPEC_VMUL
94f0f2cc
JG
384 UNSPEC_VMULL_P
385 UNSPEC_VMULL_S
386 UNSPEC_VMULL_U
79739965 387 UNSPEC_VMUL_LANE
94f0f2cc
JG
388 UNSPEC_VMULL_S_LANE
389 UNSPEC_VMULL_U_LANE
390 UNSPEC_VPADAL_S
391 UNSPEC_VPADAL_U
79739965 392 UNSPEC_VPADD
94f0f2cc
JG
393 UNSPEC_VPADDL_S
394 UNSPEC_VPADDL_U
79739965 395 UNSPEC_VPMAX
94f0f2cc 396 UNSPEC_VPMAX_U
79739965 397 UNSPEC_VPMIN
94f0f2cc 398 UNSPEC_VPMIN_U
79739965
KT
399 UNSPEC_VPSMAX
400 UNSPEC_VPSMIN
401 UNSPEC_VPUMAX
402 UNSPEC_VPUMIN
403 UNSPEC_VQABS
94f0f2cc
JG
404 UNSPEC_VQADD_S
405 UNSPEC_VQADD_U
79739965
KT
406 UNSPEC_VQDMLAL
407 UNSPEC_VQDMLAL_LANE
408 UNSPEC_VQDMLSL
409 UNSPEC_VQDMLSL_LANE
410 UNSPEC_VQDMULH
411 UNSPEC_VQDMULH_LANE
94f0f2cc
JG
412 UNSPEC_VQRDMULH
413 UNSPEC_VQRDMULH_LANE
79739965
KT
414 UNSPEC_VQDMULL
415 UNSPEC_VQDMULL_LANE
94f0f2cc
JG
416 UNSPEC_VQMOVN_S
417 UNSPEC_VQMOVN_U
79739965
KT
418 UNSPEC_VQMOVUN
419 UNSPEC_VQNEG
94f0f2cc
JG
420 UNSPEC_VQSHL_S
421 UNSPEC_VQSHL_U
422 UNSPEC_VQRSHL_S
423 UNSPEC_VQRSHL_U
424 UNSPEC_VQSHL_S_N
425 UNSPEC_VQSHL_U_N
79739965 426 UNSPEC_VQSHLU_N
94f0f2cc
JG
427 UNSPEC_VQSHRN_S_N
428 UNSPEC_VQSHRN_U_N
429 UNSPEC_VQRSHRN_S_N
430 UNSPEC_VQRSHRN_U_N
79739965 431 UNSPEC_VQSHRUN_N
94f0f2cc
JG
432 UNSPEC_VQRSHRUN_N
433 UNSPEC_VQSUB_S
434 UNSPEC_VQSUB_U
79739965
KT
435 UNSPEC_VRECPE
436 UNSPEC_VRECPS
437 UNSPEC_VREV16
438 UNSPEC_VREV32
439 UNSPEC_VREV64
440 UNSPEC_VRSQRTE
441 UNSPEC_VRSQRTS
94f0f2cc
JG
442 UNSPEC_VSHL_S
443 UNSPEC_VSHL_U
444 UNSPEC_VRSHL_S
445 UNSPEC_VRSHL_U
446 UNSPEC_VSHLL_S_N
447 UNSPEC_VSHLL_U_N
79739965 448 UNSPEC_VSHL_N
94f0f2cc
JG
449 UNSPEC_VSHR_S_N
450 UNSPEC_VSHR_U_N
451 UNSPEC_VRSHR_S_N
452 UNSPEC_VRSHR_U_N
79739965 453 UNSPEC_VSHRN_N
94f0f2cc 454 UNSPEC_VRSHRN_N
79739965 455 UNSPEC_VSLI
94f0f2cc
JG
456 UNSPEC_VSRA_S_N
457 UNSPEC_VSRA_U_N
458 UNSPEC_VRSRA_S_N
459 UNSPEC_VRSRA_U_N
79739965
KT
460 UNSPEC_VSRI
461 UNSPEC_VST1
462 UNSPEC_VST1_LANE
463 UNSPEC_VST2
464 UNSPEC_VST2_LANE
465 UNSPEC_VST3
466 UNSPEC_VST3A
467 UNSPEC_VST3B
468 UNSPEC_VST3_LANE
469 UNSPEC_VST4
470 UNSPEC_VST4A
471 UNSPEC_VST4B
472 UNSPEC_VST4_LANE
473 UNSPEC_VSTRUCTDUMMY
474 UNSPEC_VSUB
475 UNSPEC_VSUBHN
94f0f2cc
JG
476 UNSPEC_VRSUBHN
477 UNSPEC_VSUBL_S
478 UNSPEC_VSUBL_U
479 UNSPEC_VSUBW_S
480 UNSPEC_VSUBW_U
79739965
KT
481 UNSPEC_VTBL
482 UNSPEC_VTBX
483 UNSPEC_VTRN1
484 UNSPEC_VTRN2
485 UNSPEC_VTST
486 UNSPEC_VUZP1
487 UNSPEC_VUZP2
488 UNSPEC_VZIP1
489 UNSPEC_VZIP2
490 UNSPEC_MISALIGNED_ACCESS
491 UNSPEC_VCLE
492 UNSPEC_VCLT
493 UNSPEC_NVRINTZ
494 UNSPEC_NVRINTP
495 UNSPEC_NVRINTM
496 UNSPEC_NVRINTX
497 UNSPEC_NVRINTA
498 UNSPEC_NVRINTN
5f2ca3b2
MW
499 UNSPEC_VQRDMLAH
500 UNSPEC_VQRDMLSH
d403b8d4
MW
501 UNSPEC_VRND
502 UNSPEC_VRNDA
503 UNSPEC_VRNDI
504 UNSPEC_VRNDM
505 UNSPEC_VRNDN
506 UNSPEC_VRNDP
507 UNSPEC_VRNDX
f8e109ba
TC
508 UNSPEC_DOT_S
509 UNSPEC_DOT_U
f348846e
SMW
510 UNSPEC_DOT_US
511 UNSPEC_DOT_SU
06e95715
KT
512 UNSPEC_VFML_LO
513 UNSPEC_VFML_HI
c2b7062d
TC
514 UNSPEC_VCADD90
515 UNSPEC_VCADD270
516 UNSPEC_VCMLA
517 UNSPEC_VCMLA90
518 UNSPEC_VCMLA180
519 UNSPEC_VCMLA270
389b67fe
TC
520 UNSPEC_VCMLA_CONJ
521 UNSPEC_VCMLA180_CONJ
db253e8b
TC
522 UNSPEC_VCMUL
523 UNSPEC_VCMUL90
524 UNSPEC_VCMUL180
525 UNSPEC_VCMUL270
389b67fe 526 UNSPEC_VCMUL_CONJ
436016f4
DZ
527 UNSPEC_MATMUL_S
528 UNSPEC_MATMUL_U
529 UNSPEC_MATMUL_US
8e6d0dba
DZ
530 UNSPEC_BFCVT
531 UNSPEC_BFCVT_HIGH
2d22ab64
KT
532 UNSPEC_BFMMLA
533 UNSPEC_BFMAB
534 UNSPEC_BFMAT
79739965 535])
a9a88a0a
SP
536
537;; Enumerators for MVE unspecs.
538(define_c_enum "unspec" [
539 VST4Q
540 VRNDXQ_F
541 VRNDQ_F
542 VRNDPQ_F
543 VRNDNQ_F
544 VRNDMQ_F
545 VRNDAQ_F
546 VREV64Q_F
a9a88a0a 547 VDUPQ_N_F
a9a88a0a
SP
548 VREV32Q_F
549 VCVTTQ_F32_F16
550 VCVTBQ_F32_F16
551 VCVTQ_TO_F_S
552 VQNEGQ_S
553 VCVTQ_TO_F_U
554 VREV16Q_S
555 VREV16Q_U
556 VADDLVQ_S
557 VMVNQ_N_S
558 VMVNQ_N_U
559 VCVTAQ_S
560 VCVTAQ_U
561 VREV64Q_S
562 VREV64Q_U
563 VQABSQ_S
a9a88a0a
SP
564 VDUPQ_N_U
565 VDUPQ_N_S
a9a88a0a
SP
566 VCLSQ_S
567 VADDVQ_S
568 VADDVQ_U
a9a88a0a
SP
569 VREV32Q_U
570 VREV32Q_S
571 VMOVLTQ_U
572 VMOVLTQ_S
573 VMOVLBQ_S
574 VMOVLBQ_U
575 VCVTQ_FROM_F_S
576 VCVTQ_FROM_F_U
577 VCVTPQ_S
578 VCVTPQ_U
579 VCVTNQ_S
580 VCVTNQ_U
581 VCVTMQ_S
582 VCVTMQ_U
583 VADDLVQ_U
e0bc13d3
AV
584 VCTP
585 VCTP_M
a9a88a0a
SP
586 VPNOT
587 VCREATEQ_F
588 VCVTQ_N_TO_F_S
589 VCVTQ_N_TO_F_U
590 VBRSRQ_N_F
591 VSUBQ_N_F
592 VCREATEQ_U
593 VCREATEQ_S
594 VSHRQ_N_S
595 VSHRQ_N_U
596 VCVTQ_N_FROM_F_S
597 VCVTQ_N_FROM_F_U
598 VADDLVQ_P_S
599 VADDLVQ_P_U
a9a88a0a
SP
600 VSHLQ_S
601 VSHLQ_U
602 VABDQ_S
603 VADDQ_N_S
604 VADDVAQ_S
605 VADDVQ_P_S
a9a88a0a 606 VBRSRQ_N_S
a9a88a0a
SP
607 VHADDQ_S
608 VHADDQ_N_S
609 VHSUBQ_S
610 VHSUBQ_N_S
611 VMAXQ_S
612 VMAXVQ_S
613 VMINQ_S
614 VMINVQ_S
615 VMLADAVQ_S
616 VMULHQ_S
617 VMULLBQ_INT_S
618 VMULLTQ_INT_S
619 VMULQ_S
620 VMULQ_N_S
a9a88a0a
SP
621 VQADDQ_S
622 VQADDQ_N_S
623 VQRSHLQ_S
624 VQRSHLQ_N_S
625 VQSHLQ_S
626 VQSHLQ_N_S
627 VQSHLQ_R_S
628 VQSUBQ_S
629 VQSUBQ_N_S
630 VRHADDQ_S
631 VRMULHQ_S
632 VRSHLQ_S
633 VRSHLQ_N_S
634 VRSHRQ_N_S
635 VSHLQ_N_S
636 VSHLQ_R_S
637 VSUBQ_S
638 VSUBQ_N_S
639 VABDQ_U
640 VADDQ_N_U
641 VADDVAQ_U
642 VADDVQ_P_U
a9a88a0a 643 VBRSRQ_N_U
a9a88a0a
SP
644 VHADDQ_U
645 VHADDQ_N_U
646 VHSUBQ_U
647 VHSUBQ_N_U
648 VMAXQ_U
649 VMAXVQ_U
650 VMINQ_U
651 VMINVQ_U
652 VMLADAVQ_U
653 VMULHQ_U
654 VMULLBQ_INT_U
655 VMULLTQ_INT_U
656 VMULQ_U
657 VMULQ_N_U
a9a88a0a
SP
658 VQADDQ_U
659 VQADDQ_N_U
660 VQRSHLQ_U
661 VQRSHLQ_N_U
662 VQSHLQ_U
663 VQSHLQ_N_U
664 VQSHLQ_R_U
665 VQSUBQ_U
666 VQSUBQ_N_U
667 VRHADDQ_U
668 VRMULHQ_U
669 VRSHLQ_U
670 VRSHLQ_N_U
671 VRSHRQ_N_U
672 VSHLQ_N_U
673 VSHLQ_R_U
674 VSUBQ_U
675 VSUBQ_N_U
a9a88a0a
SP
676 VHCADDQ_ROT270_S
677 VHCADDQ_ROT90_S
678 VMAXAQ_S
679 VMAXAVQ_S
680 VMINAQ_S
681 VMINAVQ_S
682 VMLADAVXQ_S
683 VMLSDAVQ_S
684 VMLSDAVXQ_S
685 VQDMULHQ_N_S
686 VQDMULHQ_S
687 VQRDMULHQ_N_S
688 VQRDMULHQ_S
689 VQSHLUQ_N_S
a9a88a0a
SP
690 VABDQ_M_S
691 VABDQ_M_U
692 VABDQ_F
693 VADDQ_N_F
a9a88a0a
SP
694 VMAXNMAQ_F
695 VMAXNMAVQ_F
696 VMAXNMQ_F
697 VMAXNMVQ_F
698 VMINNMAQ_F
699 VMINNMAVQ_F
700 VMINNMQ_F
701 VMINNMVQ_F
702 VMULQ_F
703 VMULQ_N_F
a9a88a0a
SP
704 VSUBQ_F
705 VADDLVAQ_U
706 VADDLVAQ_S
707 VBICQ_N_U
708 VBICQ_N_S
a9a88a0a
SP
709 VCVTBQ_F16_F32
710 VCVTTQ_F16_F32
711 VMLALDAVQ_U
712 VMLALDAVXQ_U
713 VMLALDAVXQ_S
714 VMLALDAVQ_S
715 VMLSLDAVQ_S
716 VMLSLDAVXQ_S
717 VMOVNBQ_U
718 VMOVNBQ_S
719 VMOVNTQ_U
720 VMOVNTQ_S
721 VORRQ_N_S
722 VORRQ_N_U
723 VQDMULLBQ_N_S
724 VQDMULLBQ_S
725 VQDMULLTQ_N_S
726 VQDMULLTQ_S
727 VQMOVNBQ_U
728 VQMOVNBQ_S
729 VQMOVUNBQ_S
730 VQMOVUNTQ_S
731 VRMLALDAVHXQ_S
732 VRMLSLDAVHQ_S
733 VRMLSLDAVHXQ_S
734 VSHLLBQ_S
735 VSHLLBQ_U
736 VSHLLTQ_U
737 VSHLLTQ_S
738 VQMOVNTQ_U
739 VQMOVNTQ_S
740 VSHLLBQ_N_S
741 VSHLLBQ_N_U
742 VSHLLTQ_N_U
743 VSHLLTQ_N_S
744 VRMLALDAVHQ_U
745 VRMLALDAVHQ_S
746 VMULLTQ_POLY_P
747 VMULLBQ_POLY_P
748 VBICQ_M_N_S
749 VBICQ_M_N_U
750 VCMPEQQ_M_F
751 VCVTAQ_M_S
752 VCVTAQ_M_U
753 VCVTQ_M_TO_F_S
754 VCVTQ_M_TO_F_U
755 VQRSHRNBQ_N_U
756 VQRSHRNBQ_N_S
757 VQRSHRUNBQ_N_S
758 VRMLALDAVHAQ_S
759 VABAVQ_S
760 VABAVQ_U
761 VSHLCQ_S
762 VSHLCQ_U
763 VRMLALDAVHAQ_U
764 VABSQ_M_S
765 VADDVAQ_P_S
766 VADDVAQ_P_U
767 VCLSQ_M_S
768 VCLZQ_M_S
769 VCLZQ_M_U
770 VCMPCSQ_M_N_U
771 VCMPCSQ_M_U
772 VCMPEQQ_M_N_S
773 VCMPEQQ_M_N_U
774 VCMPEQQ_M_S
775 VCMPEQQ_M_U
776 VCMPGEQ_M_N_S
777 VCMPGEQ_M_S
778 VCMPGTQ_M_N_S
779 VCMPGTQ_M_S
780 VCMPHIQ_M_N_U
781 VCMPHIQ_M_U
782 VCMPLEQ_M_N_S
783 VCMPLEQ_M_S
784 VCMPLTQ_M_N_S
785 VCMPLTQ_M_S
786 VCMPNEQ_M_N_S
787 VCMPNEQ_M_N_U
788 VCMPNEQ_M_S
789 VCMPNEQ_M_U
790 VDUPQ_M_N_S
791 VDUPQ_M_N_U
792 VDWDUPQ_N_U
793 VDWDUPQ_WB_U
794 VIWDUPQ_N_U
795 VIWDUPQ_WB_U
796 VMAXAQ_M_S
797 VMAXAVQ_P_S
798 VMAXVQ_P_S
799 VMAXVQ_P_U
800 VMINAQ_M_S
801 VMINAVQ_P_S
802 VMINVQ_P_S
803 VMINVQ_P_U
804 VMLADAVAQ_S
805 VMLADAVAQ_U
806 VMLADAVQ_P_S
807 VMLADAVQ_P_U
808 VMLADAVXQ_P_S
809 VMLAQ_N_S
810 VMLAQ_N_U
811 VMLASQ_N_S
812 VMLASQ_N_U
813 VMLSDAVQ_P_S
814 VMLSDAVXQ_P_S
815 VMVNQ_M_S
816 VMVNQ_M_U
817 VNEGQ_M_S
818 VPSELQ_S
819 VPSELQ_U
820 VQABSQ_M_S
821 VQDMLAHQ_N_S
afb198ee 822 VQDMLASHQ_N_S
a9a88a0a
SP
823 VQNEGQ_M_S
824 VQRDMLADHQ_S
825 VQRDMLADHXQ_S
826 VQRDMLAHQ_N_S
a9a88a0a 827 VQRDMLASHQ_N_S
a9a88a0a
SP
828 VQRDMLSDHQ_S
829 VQRDMLSDHXQ_S
830 VQRSHLQ_M_N_S
831 VQRSHLQ_M_N_U
832 VQSHLQ_M_R_S
833 VQSHLQ_M_R_U
834 VREV64Q_M_S
835 VREV64Q_M_U
836 VRSHLQ_M_N_S
837 VRSHLQ_M_N_U
838 VSHLQ_M_R_S
839 VSHLQ_M_R_U
840 VSLIQ_N_S
841 VSLIQ_N_U
842 VSRIQ_N_S
843 VSRIQ_N_U
844 VQDMLSDHXQ_S
845 VQDMLSDHQ_S
846 VQDMLADHXQ_S
847 VQDMLADHQ_S
848 VMLSDAVAXQ_S
849 VMLSDAVAQ_S
850 VMLADAVAXQ_S
851 VCMPGEQ_M_F
852 VCMPGTQ_M_N_F
853 VMLSLDAVQ_P_S
854 VRMLALDAVHAXQ_S
855 VMLSLDAVXQ_P_S
856 VFMAQ_F
857 VMLSLDAVAQ_S
858 VQSHRUNBQ_N_S
859 VQRSHRUNTQ_N_S
a9a88a0a
SP
860 VMINNMAQ_M_F
861 VFMASQ_N_F
862 VDUPQ_M_N_F
863 VCMPGTQ_M_F
864 VCMPLTQ_M_F
865 VRMLSLDAVHQ_P_S
866 VQSHRUNTQ_N_S
867 VABSQ_M_F
868 VMAXNMAVQ_P_F
869 VFMAQ_N_F
870 VRMLSLDAVHXQ_P_S
871 VREV32Q_M_F
872 VRMLSLDAVHAQ_S
873 VRMLSLDAVHAXQ_S
874 VCMPLTQ_M_N_F
875 VCMPNEQ_M_F
876 VRNDAQ_M_F
877 VRNDPQ_M_F
878 VADDLVAQ_P_S
879 VQMOVUNBQ_M_S
880 VCMPLEQ_M_F
a9a88a0a
SP
881 VMLSLDAVAXQ_S
882 VRNDXQ_M_F
883 VFMSQ_F
884 VMINNMVQ_P_F
885 VMAXNMVQ_P_F
886 VPSELQ_F
a9a88a0a
SP
887 VQMOVUNTQ_M_S
888 VREV64Q_M_F
889 VNEGQ_M_F
890 VRNDMQ_M_F
891 VCMPLEQ_M_N_F
892 VCMPGEQ_M_N_F
893 VRNDNQ_M_F
894 VMINNMAVQ_P_F
895 VCMPNEQ_M_N_F
896 VRMLALDAVHQ_P_S
897 VRMLALDAVHXQ_P_S
898 VCMPEQQ_M_N_F
a9a88a0a
SP
899 VMAXNMAQ_M_F
900 VRNDQ_M_F
901 VMLALDAVQ_P_U
902 VMLALDAVQ_P_S
903 VQMOVNBQ_M_S
904 VQMOVNBQ_M_U
905 VMOVLTQ_M_U
906 VMOVLTQ_M_S
907 VMOVNBQ_M_U
908 VMOVNBQ_M_S
909 VRSHRNTQ_N_U
910 VRSHRNTQ_N_S
911 VORRQ_M_N_S
912 VORRQ_M_N_U
913 VREV32Q_M_S
914 VREV32Q_M_U
915 VQRSHRNTQ_N_U
916 VQRSHRNTQ_N_S
917 VMOVNTQ_M_U
918 VMOVNTQ_M_S
919 VMOVLBQ_M_U
920 VMOVLBQ_M_S
921 VMLALDAVAQ_S
922 VMLALDAVAQ_U
923 VQSHRNBQ_N_U
924 VQSHRNBQ_N_S
925 VSHRNBQ_N_U
926 VSHRNBQ_N_S
927 VRSHRNBQ_N_S
928 VRSHRNBQ_N_U
929 VMLALDAVXQ_P_U
930 VMLALDAVXQ_P_S
931 VQMOVNTQ_M_U
932 VQMOVNTQ_M_S
933 VMVNQ_M_N_U
934 VMVNQ_M_N_S
935 VQSHRNTQ_N_U
936 VQSHRNTQ_N_S
937 VMLALDAVAXQ_S
938 VMLALDAVAXQ_U
939 VSHRNTQ_N_S
940 VSHRNTQ_N_U
941 VCVTBQ_M_F16_F32
942 VCVTBQ_M_F32_F16
943 VCVTTQ_M_F16_F32
944 VCVTTQ_M_F32_F16
945 VCVTMQ_M_S
946 VCVTMQ_M_U
947 VCVTNQ_M_S
948 VCVTPQ_M_S
949 VCVTPQ_M_U
950 VCVTQ_M_N_FROM_F_S
951 VCVTNQ_M_U
952 VREV16Q_M_S
953 VREV16Q_M_U
954 VREV32Q_M
955 VCVTQ_M_FROM_F_U
956 VCVTQ_M_FROM_F_S
957 VRMLALDAVHQ_P_U
958 VADDLVAQ_P_U
959 VCVTQ_M_N_FROM_F_U
960 VQSHLUQ_M_N_S
961 VABAVQ_P_S
962 VABAVQ_P_U
963 VSHLQ_M_S
964 VSHLQ_M_U
965 VSRIQ_M_N_S
966 VSRIQ_M_N_U
967 VSUBQ_M_U
968 VSUBQ_M_S
969 VCVTQ_M_N_TO_F_U
970 VCVTQ_M_N_TO_F_S
971 VQADDQ_M_U
972 VQADDQ_M_S
973 VRSHRQ_M_N_S
974 VSUBQ_M_N_S
975 VSUBQ_M_N_U
976 VBRSRQ_M_N_S
977 VSUBQ_M_N_F
978 VBICQ_M_F
979 VHADDQ_M_U
980 VBICQ_M_U
981 VBICQ_M_S
982 VMULQ_M_N_U
983 VHADDQ_M_S
984 VORNQ_M_F
985 VMLAQ_M_N_S
986 VQSUBQ_M_U
987 VQSUBQ_M_S
988 VMLAQ_M_N_U
989 VQSUBQ_M_N_U
990 VQSUBQ_M_N_S
991 VMULLTQ_INT_M_S
992 VMULLTQ_INT_M_U
993 VMULQ_M_N_S
994 VMULQ_M_N_F
995 VMLASQ_M_N_U
996 VMLASQ_M_N_S
997 VMAXQ_M_U
998 VQRDMLAHQ_M_N_U
999 VCADDQ_ROT270_M_F
68ec7d75 1000 VCADDQ_ROT270_M
a9a88a0a
SP
1001 VQRSHLQ_M_S
1002 VMULQ_M_F
1003 VRHADDQ_M_U
1004 VSHRQ_M_N_U
1005 VRHADDQ_M_S
1006 VMULQ_M_S
1007 VMULQ_M_U
afb198ee 1008 VQDMLASHQ_M_N_S
a9a88a0a
SP
1009 VQRDMLASHQ_M_N_S
1010 VRSHLQ_M_S
1011 VRSHLQ_M_U
1012 VRSHRQ_M_N_U
1013 VADDQ_M_N_F
1014 VADDQ_M_N_S
1015 VADDQ_M_N_U
1016 VQRDMLASHQ_M_N_U
1017 VMAXQ_M_S
1018 VQRDMLAHQ_M_N_S
1019 VORRQ_M_S
1020 VORRQ_M_U
1021 VORRQ_M_F
1022 VQRSHLQ_M_U
1023 VRMULHQ_M_U
1024 VRMULHQ_M_S
1025 VMINQ_M_S
1026 VMINQ_M_U
1027 VANDQ_M_F
1028 VANDQ_M_U
1029 VANDQ_M_S
1030 VHSUBQ_M_N_S
1031 VHSUBQ_M_N_U
1032 VMULHQ_M_S
1033 VMULHQ_M_U
1034 VMULLBQ_INT_M_U
1035 VMULLBQ_INT_M_S
1036 VCADDQ_ROT90_M_F
1037 VSHRQ_M_N_S
1038 VADDQ_M_U
1039 VSLIQ_M_N_U
1040 VQADDQ_M_N_S
1041 VBRSRQ_M_N_F
1042 VABDQ_M_F
1043 VBRSRQ_M_N_U
1044 VEORQ_M_F
1045 VSHLQ_M_N_S
1046 VQDMLAHQ_M_N_U
1047 VQDMLAHQ_M_N_S
1048 VSHLQ_M_N_U
1049 VMLADAVAQ_P_U
1050 VMLADAVAQ_P_S
1051 VSLIQ_M_N_S
1052 VQSHLQ_M_U
1053 VQSHLQ_M_S
68ec7d75 1054 VCADDQ_ROT90_M
a9a88a0a
SP
1055 VORNQ_M_U
1056 VORNQ_M_S
1057 VQSHLQ_M_N_S
1058 VQSHLQ_M_N_U
1059 VADDQ_M_S
1060 VHADDQ_M_N_S
1061 VADDQ_M_F
1062 VQADDQ_M_N_U
1063 VEORQ_M_S
1064 VEORQ_M_U
1065 VHSUBQ_M_S
1066 VHSUBQ_M_U
1067 VHADDQ_M_N_U
1068 VHCADDQ_ROT90_M_S
1069 VQRDMLSDHQ_M_S
1070 VQRDMLSDHXQ_M_S
1071 VQRDMLADHXQ_M_S
1072 VQDMULHQ_M_S
1073 VMLADAVAXQ_P_S
1074 VQDMLADHXQ_M_S
1075 VQRDMULHQ_M_S
1076 VMLSDAVAXQ_P_S
1077 VQDMULHQ_M_N_S
1078 VHCADDQ_ROT270_M_S
1079 VQDMLSDHQ_M_S
1080 VQDMLSDHXQ_M_S
1081 VMLSDAVAQ_P_S
1082 VQRDMLADHQ_M_S
1083 VQDMLADHQ_M_S
1084 VMLALDAVAQ_P_U
1085 VMLALDAVAQ_P_S
a9a88a0a
SP
1086 VQRSHRNBQ_M_N_U
1087 VQRSHRNBQ_M_N_S
1088 VQRSHRNTQ_M_N_S
1089 VQSHRNBQ_M_N_U
1090 VQSHRNBQ_M_N_S
1091 VQSHRNTQ_M_N_S
1092 VRSHRNBQ_M_N_U
1093 VRSHRNBQ_M_N_S
1094 VRSHRNTQ_M_N_U
1095 VSHLLBQ_M_N_U
1096 VSHLLBQ_M_N_S
1097 VSHLLTQ_M_N_U
1098 VSHLLTQ_M_N_S
1099 VSHRNBQ_M_N_S
1100 VSHRNBQ_M_N_U
1101 VSHRNTQ_M_N_S
1102 VSHRNTQ_M_N_U
1103 VMLALDAVAXQ_P_S
1104 VQRSHRNTQ_M_N_U
1105 VQSHRNTQ_M_N_U
1106 VRSHRNTQ_M_N_S
1107 VQRDMULHQ_M_N_S
1108 VRMLALDAVHAQ_P_S
1109 VMLSLDAVAQ_P_S
1110 VMLSLDAVAXQ_P_S
1111 VMULLBQ_POLY_M_P
1112 VMULLTQ_POLY_M_P
1113 VQDMULLBQ_M_N_S
1114 VQDMULLBQ_M_S
1115 VQDMULLTQ_M_N_S
1116 VQDMULLTQ_M_S
1117 VQRSHRUNBQ_M_N_S
1118 VQSHRUNBQ_M_N_S
1119 VQSHRUNTQ_M_N_S
1120 VRMLALDAVHAQ_P_U
1121 VRMLALDAVHAXQ_P_S
1122 VRMLSLDAVHAQ_P_S
1123 VRMLSLDAVHAXQ_P_S
1124 VQRSHRUNTQ_M_N_S
1125 VCMLAQ_M_F
1126 VCMLAQ_ROT180_M_F
1127 VCMLAQ_ROT270_M_F
1128 VCMLAQ_ROT90_M_F
1129 VCMULQ_M_F
1130 VCMULQ_ROT180_M_F
1131 VCMULQ_ROT270_M_F
1132 VCMULQ_ROT90_M_F
1133 VFMAQ_M_F
1134 VFMAQ_M_N_F
1135 VFMASQ_M_N_F
1136 VFMSQ_M_F
1137 VMAXNMQ_M_F
1138 VMINNMQ_M_F
1139 VSUBQ_M_F
1140 VSTRWQSB_S
1141 VSTRWQSB_U
1142 VSTRBQSO_S
1143 VSTRBQSO_U
1144 VSTRBQ_S
1145 VSTRBQ_U
1146 VLDRBQGO_S
1147 VLDRBQGO_U
1148 VLDRBQ_S
1149 VLDRBQ_U
1150 VLDRWQGB_S
1151 VLDRWQGB_U
1152 VLD1Q_F
1153 VLD1Q_S
1154 VLD1Q_U
1155 VLDRHQ_F
1156 VLDRHQGO_S
1157 VLDRHQGO_U
1158 VLDRHQGSO_S
1159 VLDRHQGSO_U
1160 VLDRHQ_S
1161 VLDRHQ_U
1162 VLDRWQ_F
1163 VLDRWQ_S
1164 VLDRWQ_U
1165 VLDRDQGB_S
1166 VLDRDQGB_U
1167 VLDRDQGO_S
1168 VLDRDQGO_U
1169 VLDRDQGSO_S
1170 VLDRDQGSO_U
1171 VLDRHQGO_F
1172 VLDRHQGSO_F
1173 VLDRWQGB_F
1174 VLDRWQGO_F
1175 VLDRWQGO_S
1176 VLDRWQGO_U
1177 VLDRWQGSO_F
1178 VLDRWQGSO_S
1179 VLDRWQGSO_U
1180 VSTRHQ_F
1181 VST1Q_S
1182 VST1Q_U
1183 VSTRHQSO_S
1184 VSTRHQ_U
1185 VSTRWQ_S
1186 VSTRWQ_U
1187 VSTRWQ_F
1188 VST1Q_F
1189 VSTRDQSB_S
1190 VSTRDQSB_U
1191 VSTRDQSO_S
1192 VSTRDQSO_U
1193 VSTRDQSSO_S
1194 VSTRDQSSO_U
1195 VSTRWQSO_S
1196 VSTRWQSO_U
1197 VSTRWQSSO_S
1198 VSTRWQSSO_U
1199 VSTRHQSO_F
1200 VSTRHQSSO_F
1201 VSTRWQSB_F
1202 VSTRWQSO_F
1203 VSTRWQSSO_F
1204 VDDUPQ
1205 VDDUPQ_M
1206 VDWDUPQ
1207 VDWDUPQ_M
1208 VIDUPQ
1209 VIDUPQ_M
1210 VIWDUPQ
1211 VIWDUPQ_M
1212 VSTRWQSBWB_S
1213 VSTRWQSBWB_U
1214 VLDRWQGBWB_S
1215 VLDRWQGBWB_U
1216 VSTRWQSBWB_F
1217 VLDRWQGBWB_F
1218 VSTRDQSBWB_S
1219 VSTRDQSBWB_U
1220 VLDRDQGBWB_S
1221 VLDRDQGBWB_U
1222 VADCQ_U
1223 VADCQ_M_U
1224 VADCQ_S
1225 VADCQ_M_S
1226 VSBCIQ_U
1227 VSBCIQ_S
1228 VSBCIQ_M_U
1229 VSBCIQ_M_S
1230 VSBCQ_U
1231 VSBCQ_S
1232 VSBCQ_M_U
1233 VSBCQ_M_S
1234 VADCIQ_U
1235 VADCIQ_M_U
1236 VADCIQ_S
1237 VADCIQ_M_S
1238 VLD2Q
1239 VLD4Q
1240 VST2Q
1241 VSHLCQ_M_U
1242 VSHLCQ_M_S
1243 VSTRHQSO_U
1244 VSTRHQSSO_S
1245 VSTRHQSSO_U
1246 VSTRHQ_S
1247 SRSHRL
1248 SRSHR
1249 URSHR
1250 URSHRL
1251 SQRSHR
1252 UQRSHL
1253 UQRSHLL_64
1254 UQRSHLL_48
1255 SQRSHRL_64
1256 SQRSHRL_48
1257 VSHLCQ_M_
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