[thirdparty/gcc.git] / gcc / config / csky / csky_insn_fpuv2.md

;; C-SKY FPUV2 instruction descriptions.
;; Copyright (C) 2018-2022 Free Software Foundation, Inc.
;; Contributed by C-SKY Microsystems and Mentor Graphics.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.  */

;; -------------------------------------------------------------------------
;; Float Abs instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_abssf2"
  [(set (match_operand:SF	 0 "register_operand" "=v,a,r")
	(abs:SF (match_operand:SF 1 "register_operand" "v, 0,r")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "@
    fabss\t%0, %1
    bclri\t%0, %1, 31
    bclri\t%0, %1, 31"
  [(set_attr "length" "4,2,4")])

(define_insn "*fpuv2_absdf2"
  [(set (match_operand:DF	 0 "register_operand" "=v")
	(abs:DF (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fabsd\t%0, %1")


;; -------------------------------------------------------------------------
;; Float Neg instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_negsf2"
  [(set (match_operand:SF	 0 "register_operand" "=v")
	(neg:SF (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fnegs\t%0, %1")

(define_insn "*fpuv2_negdf2"
  [(set (match_operand:DF	 0 "register_operand" "=v")
	(neg:DF (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fnegd\t%0, %1")


;; -------------------------------------------------------------------------
;; Float Sqrt instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_sqrtsf2"
  [(set (match_operand:SF	  0 "register_operand" "=v")
	(sqrt:SF (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fsqrts\t%0, %1")

(define_insn "*fpuv2_sqrtdf2"
  [(set (match_operand:DF	  0 "register_operand" "=v")
	(sqrt:DF (match_operand:DF 1 "register_operand" "v")))]
 "CSKY_ISA_FEATURE (fpv2_divd)"
 "fsqrtd\t%0, %1")


;; -------------------------------------------------------------------------
;; Float Add instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_addsf3"
  [(set (match_operand:SF	  0 "register_operand" "=v")
	(plus:SF (match_operand:SF 1 "register_operand" "v")
		 (match_operand:SF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fadds\t%0, %1, %2")

(define_insn "*fpuv2_adddf3"
  [(set (match_operand:DF	  0 "register_operand" "=v")
	(plus:DF (match_operand:DF 1 "register_operand" "v")
		 (match_operand:DF 2 "register_operand" "v")))]
 "CSKY_ISA_FEATURE (fpv2_df)"
 "faddd\t%0, %1, %2")


;; -------------------------------------------------------------------------
;; Float Sub instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_subsf3"
  [(set (match_operand:SF	   0 "register_operand" "=v")
	(minus:SF (match_operand:SF 1 "register_operand" "v")
		  (match_operand:SF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fsubs\t%0, %1, %2")

(define_insn "*fpuv2_subdf3"
  [(set (match_operand:DF	   0 "register_operand" "=v")
	(minus:DF (match_operand:DF 1 "register_operand" "v")
		  (match_operand:DF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fsubd\t%0, %1, %2")


;; -------------------------------------------------------------------------
;; Float Mul instructions
;; -------------------------------------------------------------------------

(define_insn "*fpv2_mulsf3"
  [(set (match_operand:SF	  0 "register_operand" "=v")
	(mult:SF (match_operand:SF 1 "register_operand" "v")
		 (match_operand:SF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fmuls\t%0, %1, %2")

(define_insn "*fpv2_muldf3"
  [(set (match_operand:DF	  0 "register_operand" "=v")
	(mult:DF (match_operand:DF 1 "register_operand" "v")
		 (match_operand:DF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fmuld\t%0, %1, %2")

(define_insn "*fpuv2_nmulsf3_1"
  [(set (match_operand:SF		  0 "register_operand" "=v")
	(mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v"))
		 (match_operand:SF	 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf) && !flag_rounding_math"
  "fnmuls\t%0, %1, %2")

(define_insn "*fpuv2_nmulsf3_2"
  [(set (match_operand:SF		  0 "register_operand" "=v")
	(neg:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
			 (match_operand:SF 2 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fnmuls\t%0, %1, %2")

(define_insn "*fpuv2_nmuldf3_1"
  [(set (match_operand:DF		  0 "register_operand" "=v")
	(mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v"))
		 (match_operand:DF	 2 "register_operand" "v")))]
 "CSKY_ISA_FEATURE (fpv2_df) && !flag_rounding_math"
 "fnmuld\t%0, %1, %2")

(define_insn "*fpuv2_nmuldf3_2"
  [(set (match_operand:DF		  0 "register_operand" "=v")
	(neg:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
			 (match_operand:DF 2 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fnmuld\t%0, %1, %2")


;; -------------------------------------------------------------------------
;; Float Div instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_divsf3"
  [(set (match_operand:SF	 0 "register_operand" "=v")
	(div:SF (match_operand:SF 1 "register_operand" "v")
		(match_operand:SF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fdivs\t%0, %1, %2")

(define_insn "*fpuv2_1_divsf3"
  [(set (match_operand:SF	 0 "register_operand"	  "=v")
	(div:SF (match_operand:SF 1 "csky_const_float1_operand" "i")
		(match_operand:SF 2 "register_operand"	  "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "frecips\t%0, %2")

(define_insn "*fpuv2_divdf3"
  [(set (match_operand:DF	 0 "register_operand" "=v")
	(div:DF (match_operand:DF 1 "register_operand" "v")
		(match_operand:DF 2 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_divd)"
  "fdivd\t%0, %1, %2")

(define_insn "*fpuv2_1_divdf3"
  [(set (match_operand:DF	 0 "register_operand"	  "=v")
	(div:DF (match_operand:DF 1 "csky_const_float1_operand" "i")
		(match_operand:DF 2 "register_operand"	  "v")))]
  "CSKY_ISA_FEATURE (fpv2_divd)"
  "frecipd\t%0, %2")


;; -------------------------------------------------------------------------
;; Float add(sub) with mult instructions
;; -------------------------------------------------------------------------

;; vrz <= vrz + vrx * vry
(define_insn "*fpuv2_fmacs"
  [(set (match_operand:SF		   0 "register_operand" "=v")
	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
			  (match_operand:SF 2 "register_operand" "v"))
		 (match_operand:SF	  3 "register_operand" "0")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fmacs\t%0, %1, %2")

(define_insn "*fpuv2_fmacd"
  [(set (match_operand:DF		   0 "register_operand" "=v")
	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
			  (match_operand:DF 2 "register_operand" "v"))
		 (match_operand:DF	  3 "register_operand" "0")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fmacd\t%0, %1, %2")

;; vrz <= vrz - vrx * vry
(define_insn "*fpuv2_fnmacs"
  [(set (match_operand:SF		    0 "register_operand" "=v")
	(minus:SF (match_operand:SF	  1 "register_operand" "0")
		  (mult:SF (match_operand:SF 2 "register_operand" "v")
			   (match_operand:SF 3 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fnmacs\t%0, %2, %3")

(define_insn "*fpuv2_fnmacd"
  [(set (match_operand:DF		    0 "register_operand" "=v")
	(minus:DF (match_operand:DF	  1 "register_operand" "0")
		  (mult:DF (match_operand:DF 2 "register_operand" "v")
			   (match_operand:DF 3 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fnmacd\t%0, %2, %3")

;; vrz <= vrx * vry - vrz
(define_insn "*fpuv2_fmscs"
  [(set (match_operand:SF		    0 "register_operand" "=v")
	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
			   (match_operand:SF 2 "register_operand" "v"))
		  (match_operand:SF	  3 "register_operand" "0")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fmscs\t%0, %1, %2")

(define_insn "*fpuv2_fmscd"
  [(set (match_operand:DF 0 "register_operand" "=v")
	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
			   (match_operand:DF 2 "register_operand" "v"))
		  (match_operand:DF 3 "register_operand" "0")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fmscd\t%0, %1, %2")

;; vrz = - (vrz + vrx * vry)
(define_insn "*fpuv2_fnmscs_1"
  [(set (match_operand:SF			    0 "register_operand" "=v")
	(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v"))
			   (match_operand:SF	 2 "register_operand" "v"))
		  (match_operand:SF		  3 "register_operand" "0")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fnmscs\t%0, %1, %2")

(define_insn "*fpuv2_fnmscs_2"
  [(set (match_operand:SF			   0 "register_operand" "=v")
	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
				  (match_operand:SF 2 "register_operand" "v"))
			 (match_operand:SF	  3 "register_operand" "0"))))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fnmscs\t%0, %1, %2")

(define_insn "*fpuv2_fnmscd_1"
  [(set (match_operand:DF 0 "register_operand" "=v")
	(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v"))
			   (match_operand:DF 2 "register_operand" "v"))
		  (match_operand:DF 3 "register_operand" "0")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fnmscd\t%0, %1, %2")

(define_insn "*fpuv2_fnmscd_2"
  [(set (match_operand:DF 0 "register_operand" "=v")
	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
				  (match_operand:DF 2 "register_operand" "v"))
			 (match_operand:DF 3 "register_operand" "0"))))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fnmscd\t%0, %1, %2")


;; -------------------------------------------------------------------------
;; Float compare instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_unordered"
  [(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v")
				  (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmpuos\t%0, %1")

(define_insn "*fpuv2_unordered_zero"
  [(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v")
				  (match_operand:SF 1 "csky_const_float0_operand" "i")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmpuos\t%0, %0")

(define_insn "*fpuv2_ne"
  [(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v")
			   (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmpnes\t%0, %1")

(define_insn "*fpuv2_gt"
  [(set (reg:CC 33) (gt:CC (match_operand:SF 0 "register_operand" "v")
			   (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmplts\t%1, %0")

(define_insn "*fpuv2_ge"
  [(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v")
			   (match_operand:SF 1 "register_operand" "v")))]
 "CSKY_ISA_FEATURE (fpv2_sf)"
 "fcmphss\t%0, %1")

(define_insn "*fpuv2_lt"
  [(set (reg:CC 33) (lt:CC (match_operand:SF 0 "register_operand" "v")
			   (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmplts\t%0, %1")

(define_insn "*fpuv2_le"
  [(set (reg:CC 33) (le:CC (match_operand:SF 0 "register_operand" "v")
			   (match_operand:SF 1 "register_operand" "v")))]
 "CSKY_ISA_FEATURE (fpv2_sf)"
 "fcmphss\t%1, %0")

(define_insn "*fpuv2_gez"
  [(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand"	  "v")
			   (match_operand:SF 1 "csky_const_float0_operand" "i")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmpzhss\t%0")

(define_insn "*fpuv2_nez"
  [(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand"	  "v")
			   (match_operand:SF 1 "csky_const_float0_operand" "i")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fcmpznes\t%0")

(define_insn "*fpuv2_dunordered"
  [(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v")
				  (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmpuod\t%0, %1")

(define_insn "*fpuv2_dunordered_zero"
  [(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v")
				  (match_operand:DF 1 "csky_const_float0_operand" "i")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmpuod\t%0, %0")

(define_insn "*fpuv2_dne"
  [(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v")
			   (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmpned\t%0, %1")

(define_insn "*fpuv2_dgt"
  [(set (reg:CC 33) (gt:CC (match_operand:DF 0 "register_operand" "v")
			   (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmpltd\t%1, %0")

(define_insn "*fpuv2_dge"
  [(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v")
			   (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmphsd\t%0, %1")

(define_insn "*fpuv2_dlt"
  [(set (reg:CC 33) (lt:CC (match_operand:DF 0 "register_operand" "v")
			   (match_operand:DF 1 "register_operand" "v")))]
 "CSKY_ISA_FEATURE (fpv2_df)"
 "fcmpltd\t%0, %1")

(define_insn "*fpuv2_dle"
  [(set (reg:CC 33) (le:CC (match_operand:DF 0 "register_operand" "v")
			   (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmphsd\t%1, %0")

(define_insn "*fpuv2_dgez"
  [(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand"	  "v")
			   (match_operand:DF 1 "csky_const_float0_operand" "i")))]
 "CSKY_ISA_FEATURE (fpv2_df)"
 "fcmpzhsd\t%0")

(define_insn "*fpuv2_dnez"
  [(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand"	  "v")
			   (match_operand:DF 1 "csky_const_float0_operand" "i")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fcmpzned\t%0")


;; -------------------------------------------------------------------------
;; Float convert instructions
;; -------------------------------------------------------------------------

;; DF <- SF
(define_insn "*fpuv2_extendsfdf2"
  [(set (match_operand:DF		  0 "register_operand" "=v")
	(float_extend:DF (match_operand:SF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fstod\t%0, %1")

;; SF <- DF
(define_insn "*fpuv2_truncdfsf2"
  [(set (match_operand:SF		    0 "register_operand" "=v")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fdtos\t%0, %1")

;; SF <- SI
(define_insn "*fpuv2_floatsisf2"
  [(set (match_operand:SF	   0 "register_operand" "=v")
	(float:SF (match_operand:SI 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fsitos\t%0, %1")

;; DF <- SI
(define_insn "*fpuv2_floatsidf2"
  [(set (match_operand:DF	   0 "register_operand" "=v")
	(float:DF (match_operand:SI 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fsitod\t%0, %1")

;; SF <- unsigned SI
(define_insn "*fpuv2_floatunssisf2"
  [(set (match_operand:SF		    0 "register_operand" "=v")
	(unsigned_float:SF (match_operand:SI 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fuitos\t%0, %1")

;; DF <- unsigned SI
(define_insn "*fpuv2_floatunssidf2"
  [(set (match_operand:DF		    0 "register_operand" "=v")
	(unsigned_float:DF (match_operand:SI 1 "register_operand" "v")))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fuitod\t%0, %1")

;; SI <- SF
(define_insn "*fpuv2_fix_truncsfsi2"
  [(set (match_operand:SI	 0 "register_operand" "=v")
	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fstosi.rz\t%0, %1")

;; SI <- DF
(define_insn "*fpuv2_fix_truncdfsi2"
  [(set (match_operand:SI	 0 "register_operand" "=v")
	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fdtosi.rz\t%0, %1")

;; unsigned SI <- SF
(define_insn "*fpuv2_fixuns_truncsfsi2"
  [(set (match_operand:SI		  0 "register_operand" "=v")
	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "fstoui.rz\t%0, %1")

;; unsigned SI <- DF
(define_insn "*fpuv2_fixuns_truncdfsi2"
  [(set (match_operand:SI		  0 "register_operand" "=v")
	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "v"))))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "fdtoui.rz\t%0, %1")


;; -------------------------------------------------------------------------
;; Float mov instructions
;; -------------------------------------------------------------------------

(define_insn "*fpuv2_movsf"
  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r, r,m,v,r,Q,v,v,v")
	(match_operand:SF 1 "general_operand"      " r,m,mF,r,r,v,v,Q,v,W"))]
  "CSKY_ISA_FEATURE (fpv2_sf)"
  "* return csky_output_move(insn, operands, SFmode);"
)

(define_insn "*fpuv2_movdf"
  [(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v,r, r,Y")
	(match_operand:DF 1 "general_operand"      " r,?r, v,v,Q,v,m,Y,YF,r"))]
  "CSKY_ISA_FEATURE (fpv2_df)"
  "* return csky_output_movedouble(operands, DFmode);"
  [(set (attr "length")
	(symbol_ref "csky_get_movedouble_length (operands)"))]
)
Commit	Line	Data
45d5c476	1	;; C-SKY FPUV2 instruction descriptions.
7adcbafe	2	;; Copyright (C) 2018-2022 Free Software Foundation, Inc.
45d5c476 CQ	3	;; Contributed by C-SKY Microsystems and Mentor Graphics.
	4	;;
	5	;; This file is part of GCC.
	6	;;
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published by
	9	;; the Free Software Foundation; either version 3, or (at your option)
	10	;; any later version.
	11	;;
	12	;; GCC is distributed in the hope that it will be useful, but
	13	;; WITHOUT ANY WARRANTY; without even the implied warranty of
	14	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	;; General Public License for more details.
	16	;;
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>. */
db92bd22 GQ	20
	21	;; -------------------------------------------------------------------------
	22	;; Float Abs instructions
	23	;; -------------------------------------------------------------------------
	24
	25	(define_insn "*fpuv2_abssf2"
	26	[(set (match_operand:SF 0 "register_operand" "=v,a,r")
	27	(abs:SF (match_operand:SF 1 "register_operand" "v, 0,r")))]
	28	"CSKY_ISA_FEATURE (fpv2_sf)"
	29	"@
	30	fabss\t%0, %1
	31	bclri\t%0, %1, 31
	32	bclri\t%0, %1, 31"
	33	[(set_attr "length" "4,2,4")])
	34
	35	(define_insn "*fpuv2_absdf2"
	36	[(set (match_operand:DF 0 "register_operand" "=v")
	37	(abs:DF (match_operand:DF 1 "register_operand" "v")))]
	38	"CSKY_ISA_FEATURE (fpv2_df)"
	39	"fabsd\t%0, %1")
	40
	41
	42	;; -------------------------------------------------------------------------
	43	;; Float Neg instructions
	44	;; -------------------------------------------------------------------------
	45
	46	(define_insn "*fpuv2_negsf2"
	47	[(set (match_operand:SF 0 "register_operand" "=v")
	48	(neg:SF (match_operand:SF 1 "register_operand" "v")))]
	49	"CSKY_ISA_FEATURE (fpv2_sf)"
	50	"fnegs\t%0, %1")
	51
	52	(define_insn "*fpuv2_negdf2"
	53	[(set (match_operand:DF 0 "register_operand" "=v")
	54	(neg:DF (match_operand:DF 1 "register_operand" "v")))]
	55	"CSKY_ISA_FEATURE (fpv2_df)"
	56	"fnegd\t%0, %1")
	57
	58
	59	;; -------------------------------------------------------------------------
	60	;; Float Sqrt instructions
	61	;; -------------------------------------------------------------------------
	62
	63	(define_insn "*fpuv2_sqrtsf2"
	64	[(set (match_operand:SF 0 "register_operand" "=v")
	65	(sqrt:SF (match_operand:SF 1 "register_operand" "v")))]
	66	"CSKY_ISA_FEATURE (fpv2_sf)"
	67	"fsqrts\t%0, %1")
	68
	69	(define_insn "*fpuv2_sqrtdf2"
	70	[(set (match_operand:DF 0 "register_operand" "=v")
	71	(sqrt:DF (match_operand:DF 1 "register_operand" "v")))]
	72	"CSKY_ISA_FEATURE (fpv2_divd)"
	73	"fsqrtd\t%0, %1")
	74
	75
	76	;; -------------------------------------------------------------------------
	77	;; Float Add instructions
	78	;; -------------------------------------------------------------------------
	79
	80	(define_insn "*fpuv2_addsf3"
	81	[(set (match_operand:SF 0 "register_operand" "=v")
	82	(plus:SF (match_operand:SF 1 "register_operand" "v")
	83	(match_operand:SF 2 "register_operand" "v")))]
84	"CSKY_ISA_FEATURE (fpv2_sf)"
85	"fadds\t%0, %1, %2")
86
87	(define_insn "*fpuv2_adddf3"
88	[(set (match_operand:DF 0 "register_operand" "=v")
89	(plus:DF (match_operand:DF 1 "register_operand" "v")
90	(match_operand:DF 2 "register_operand" "v")))]
91	"CSKY_ISA_FEATURE (fpv2_df)"
92	"faddd\t%0, %1, %2")
93
94
95	;; -------------------------------------------------------------------------
96	;; Float Sub instructions
97	;; -------------------------------------------------------------------------
98
99	(define_insn "*fpuv2_subsf3"
100	[(set (match_operand:SF 0 "register_operand" "=v")
101	(minus:SF (match_operand:SF 1 "register_operand" "v")
102	(match_operand:SF 2 "register_operand" "v")))]
103	"CSKY_ISA_FEATURE (fpv2_sf)"
104	"fsubs\t%0, %1, %2")
105
106	(define_insn "*fpuv2_subdf3"
107	[(set (match_operand:DF 0 "register_operand" "=v")
108	(minus:DF (match_operand:DF 1 "register_operand" "v")
109	(match_operand:DF 2 "register_operand" "v")))]
110	"CSKY_ISA_FEATURE (fpv2_df)"
111	"fsubd\t%0, %1, %2")
112
113
114	;; -------------------------------------------------------------------------
115	;; Float Mul instructions
116	;; -------------------------------------------------------------------------
117
118	(define_insn "*fpv2_mulsf3"
119	[(set (match_operand:SF 0 "register_operand" "=v")
120	(mult:SF (match_operand:SF 1 "register_operand" "v")
121	(match_operand:SF 2 "register_operand" "v")))]
122	"CSKY_ISA_FEATURE (fpv2_sf)"
123	"fmuls\t%0, %1, %2")
124
125	(define_insn "*fpv2_muldf3"
126	[(set (match_operand:DF 0 "register_operand" "=v")
127	(mult:DF (match_operand:DF 1 "register_operand" "v")
128	(match_operand:DF 2 "register_operand" "v")))]
129	"CSKY_ISA_FEATURE (fpv2_df)"
130	"fmuld\t%0, %1, %2")
131
132	(define_insn "*fpuv2_nmulsf3_1"
133	[(set (match_operand:SF 0 "register_operand" "=v")
134	(mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v"))
135	(match_operand:SF 2 "register_operand" "v")))]
136	"CSKY_ISA_FEATURE (fpv2_sf) && !flag_rounding_math"
137	"fnmuls\t%0, %1, %2")
138
139	(define_insn "*fpuv2_nmulsf3_2"
140	[(set (match_operand:SF 0 "register_operand" "=v")
141	(neg:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
142	(match_operand:SF 2 "register_operand" "v"))))]
143	"CSKY_ISA_FEATURE (fpv2_sf)"
144	"fnmuls\t%0, %1, %2")
145
146	(define_insn "*fpuv2_nmuldf3_1"
147	[(set (match_operand:DF 0 "register_operand" "=v")
148	(mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v"))
149	(match_operand:DF 2 "register_operand" "v")))]
150	"CSKY_ISA_FEATURE (fpv2_df) && !flag_rounding_math"
151	"fnmuld\t%0, %1, %2")
152
153	(define_insn "*fpuv2_nmuldf3_2"
154	[(set (match_operand:DF 0 "register_operand" "=v")
155	(neg:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
156	(match_operand:DF 2 "register_operand" "v"))))]
157	"CSKY_ISA_FEATURE (fpv2_df)"
158	"fnmuld\t%0, %1, %2")
159
160
161	;; -------------------------------------------------------------------------
162	;; Float Div instructions
163	;; -------------------------------------------------------------------------
164
165	(define_insn "*fpuv2_divsf3"
166	[(set (match_operand:SF 0 "register_operand" "=v")
167	(div:SF (match_operand:SF 1 "register_operand" "v")
168	(match_operand:SF 2 "register_operand" "v")))]
169	"CSKY_ISA_FEATURE (fpv2_sf)"
170	"fdivs\t%0, %1, %2")
171
172	(define_insn "*fpuv2_1_divsf3"
173	[(set (match_operand:SF 0 "register_operand" "=v")
174	(div:SF (match_operand:SF 1 "csky_const_float1_operand" "i")
175	(match_operand:SF 2 "register_operand" "v")))]
176	"CSKY_ISA_FEATURE (fpv2_sf)"
177	"frecips\t%0, %2")
178
179	(define_insn "*fpuv2_divdf3"
180	[(set (match_operand:DF 0 "register_operand" "=v")
181	(div:DF (match_operand:DF 1 "register_operand" "v")
182	(match_operand:DF 2 "register_operand" "v")))]
183	"CSKY_ISA_FEATURE (fpv2_divd)"
184	"fdivd\t%0, %1, %2")
185
186	(define_insn "*fpuv2_1_divdf3"
187	[(set (match_operand:DF 0 "register_operand" "=v")
188	(div:DF (match_operand:DF 1 "csky_const_float1_operand" "i")
189	(match_operand:DF 2 "register_operand" "v")))]
190	"CSKY_ISA_FEATURE (fpv2_divd)"
191	"frecipd\t%0, %2")
192
193
194	;; -------------------------------------------------------------------------
195	;; Float add(sub) with mult instructions
196	;; -------------------------------------------------------------------------
197
198	;; vrz <= vrz + vrx * vry
199	(define_insn "*fpuv2_fmacs"
200	[(set (match_operand:SF 0 "register_operand" "=v")
201	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
202	(match_operand:SF 2 "register_operand" "v"))
203	(match_operand:SF 3 "register_operand" "0")))]
204	"CSKY_ISA_FEATURE (fpv2_sf)"
205	"fmacs\t%0, %1, %2")
206
207	(define_insn "*fpuv2_fmacd"
208	[(set (match_operand:DF 0 "register_operand" "=v")
209	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
210	(match_operand:DF 2 "register_operand" "v"))
211	(match_operand:DF 3 "register_operand" "0")))]
212	"CSKY_ISA_FEATURE (fpv2_df)"
213	"fmacd\t%0, %1, %2")
214
215	;; vrz <= vrz - vrx * vry
216	(define_insn "*fpuv2_fnmacs"
217	[(set (match_operand:SF 0 "register_operand" "=v")
218	(minus:SF (match_operand:SF 1 "register_operand" "0")
219	(mult:SF (match_operand:SF 2 "register_operand" "v")
220	(match_operand:SF 3 "register_operand" "v"))))]
221	"CSKY_ISA_FEATURE (fpv2_sf)"
222	"fnmacs\t%0, %2, %3")
223
224	(define_insn "*fpuv2_fnmacd"
225	[(set (match_operand:DF 0 "register_operand" "=v")
226	(minus:DF (match_operand:DF 1 "register_operand" "0")
227	(mult:DF (match_operand:DF 2 "register_operand" "v")
228	(match_operand:DF 3 "register_operand" "v"))))]
229	"CSKY_ISA_FEATURE (fpv2_df)"
230	"fnmacd\t%0, %2, %3")
231
232	;; vrz <= vrx * vry - vrz
233	(define_insn "*fpuv2_fmscs"
234	[(set (match_operand:SF 0 "register_operand" "=v")
235	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
236	(match_operand:SF 2 "register_operand" "v"))
237	(match_operand:SF 3 "register_operand" "0")))]
238	"CSKY_ISA_FEATURE (fpv2_sf)"
239	"fmscs\t%0, %1, %2")
240
241	(define_insn "*fpuv2_fmscd"
242	[(set (match_operand:DF 0 "register_operand" "=v")
243	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
244	(match_operand:DF 2 "register_operand" "v"))
245	(match_operand:DF 3 "register_operand" "0")))]
246	"CSKY_ISA_FEATURE (fpv2_df)"
247	"fmscd\t%0, %1, %2")
248
249	;; vrz = - (vrz + vrx * vry)
250	(define_insn "*fpuv2_fnmscs_1"
251	[(set (match_operand:SF 0 "register_operand" "=v")
252	(minus:SF (mult:SF (neg:SF (match_operand:SF 1 "register_operand" "%v"))
253	(match_operand:SF 2 "register_operand" "v"))
254	(match_operand:SF 3 "register_operand" "0")))]
255	"CSKY_ISA_FEATURE (fpv2_sf)"
256	"fnmscs\t%0, %1, %2")
257
258	(define_insn "*fpuv2_fnmscs_2"
259	[(set (match_operand:SF 0 "register_operand" "=v")
260	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "v")
261	(match_operand:SF 2 "register_operand" "v"))
262	(match_operand:SF 3 "register_operand" "0"))))]
263	"CSKY_ISA_FEATURE (fpv2_sf)"
264	"fnmscs\t%0, %1, %2")
265
266	(define_insn "*fpuv2_fnmscd_1"
267	[(set (match_operand:DF 0 "register_operand" "=v")
268	(minus:DF (mult:DF (neg:DF (match_operand:DF 1 "register_operand" "%v"))
269	(match_operand:DF 2 "register_operand" "v"))
270	(match_operand:DF 3 "register_operand" "0")))]
271	"CSKY_ISA_FEATURE (fpv2_df)"
272	"fnmscd\t%0, %1, %2")
273
274	(define_insn "*fpuv2_fnmscd_2"
275	[(set (match_operand:DF 0 "register_operand" "=v")
276	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "v")
277	(match_operand:DF 2 "register_operand" "v"))
278	(match_operand:DF 3 "register_operand" "0"))))]
279	"CSKY_ISA_FEATURE (fpv2_df)"
280	"fnmscd\t%0, %1, %2")
281
282
283	;; -------------------------------------------------------------------------
284	;; Float compare instructions
285	;; -------------------------------------------------------------------------
286
287	(define_insn "*fpuv2_unordered"
288	[(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v")
289	(match_operand:SF 1 "register_operand" "v")))]
290	"CSKY_ISA_FEATURE (fpv2_sf)"
291	"fcmpuos\t%0, %1")
292
293	(define_insn "*fpuv2_unordered_zero"
294	[(set (reg:CC 33) (unordered:CC (match_operand:SF 0 "register_operand" "v")
295	(match_operand:SF 1 "csky_const_float0_operand" "i")))]
296	"CSKY_ISA_FEATURE (fpv2_sf)"
297	"fcmpuos\t%0, %0")
298
299	(define_insn "*fpuv2_ne"
300	[(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v")
301	(match_operand:SF 1 "register_operand" "v")))]
302	"CSKY_ISA_FEATURE (fpv2_sf)"
303	"fcmpnes\t%0, %1")
304
305	(define_insn "*fpuv2_gt"
306	[(set (reg:CC 33) (gt:CC (match_operand:SF 0 "register_operand" "v")
307	(match_operand:SF 1 "register_operand" "v")))]
308	"CSKY_ISA_FEATURE (fpv2_sf)"
309	"fcmplts\t%1, %0")
310
311	(define_insn "*fpuv2_ge"
312	[(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v")
313	(match_operand:SF 1 "register_operand" "v")))]
314	"CSKY_ISA_FEATURE (fpv2_sf)"
315	"fcmphss\t%0, %1")
316
317	(define_insn "*fpuv2_lt"
318	[(set (reg:CC 33) (lt:CC (match_operand:SF 0 "register_operand" "v")
319	(match_operand:SF 1 "register_operand" "v")))]
320	"CSKY_ISA_FEATURE (fpv2_sf)"
321	"fcmplts\t%0, %1")
322
323	(define_insn "*fpuv2_le"
324	[(set (reg:CC 33) (le:CC (match_operand:SF 0 "register_operand" "v")
325	(match_operand:SF 1 "register_operand" "v")))]
326	"CSKY_ISA_FEATURE (fpv2_sf)"
327	"fcmphss\t%1, %0")
328
329	(define_insn "*fpuv2_gez"
330	[(set (reg:CC 33) (ge:CC (match_operand:SF 0 "register_operand" "v")
331	(match_operand:SF 1 "csky_const_float0_operand" "i")))]
332	"CSKY_ISA_FEATURE (fpv2_sf)"
333	"fcmpzhss\t%0")
334
335	(define_insn "*fpuv2_nez"
336	[(set (reg:CC 33) (ne:CC (match_operand:SF 0 "register_operand" "v")
337	(match_operand:SF 1 "csky_const_float0_operand" "i")))]
338	"CSKY_ISA_FEATURE (fpv2_sf)"
339	"fcmpznes\t%0")
340
341	(define_insn "*fpuv2_dunordered"
342	[(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v")
343	(match_operand:DF 1 "register_operand" "v")))]
344	"CSKY_ISA_FEATURE (fpv2_df)"
345	"fcmpuod\t%0, %1")
346
347	(define_insn "*fpuv2_dunordered_zero"
348	[(set (reg:CC 33) (unordered:CC (match_operand:DF 0 "register_operand" "v")
349	(match_operand:DF 1 "csky_const_float0_operand" "i")))]
350	"CSKY_ISA_FEATURE (fpv2_df)"
351	"fcmpuod\t%0, %0")
352
353	(define_insn "*fpuv2_dne"
354	[(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v")
355	(match_operand:DF 1 "register_operand" "v")))]
356	"CSKY_ISA_FEATURE (fpv2_df)"
357	"fcmpned\t%0, %1")
358
359	(define_insn "*fpuv2_dgt"
360	[(set (reg:CC 33) (gt:CC (match_operand:DF 0 "register_operand" "v")
361	(match_operand:DF 1 "register_operand" "v")))]
362	"CSKY_ISA_FEATURE (fpv2_df)"
363	"fcmpltd\t%1, %0")
364
365	(define_insn "*fpuv2_dge"
366	[(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v")
367	(match_operand:DF 1 "register_operand" "v")))]
368	"CSKY_ISA_FEATURE (fpv2_df)"
369	"fcmphsd\t%0, %1")
370
371	(define_insn "*fpuv2_dlt"
372	[(set (reg:CC 33) (lt:CC (match_operand:DF 0 "register_operand" "v")
373	(match_operand:DF 1 "register_operand" "v")))]
374	"CSKY_ISA_FEATURE (fpv2_df)"
375	"fcmpltd\t%0, %1")
376
377	(define_insn "*fpuv2_dle"
378	[(set (reg:CC 33) (le:CC (match_operand:DF 0 "register_operand" "v")
379	(match_operand:DF 1 "register_operand" "v")))]
380	"CSKY_ISA_FEATURE (fpv2_df)"
381	"fcmphsd\t%1, %0")
382
383	(define_insn "*fpuv2_dgez"
384	[(set (reg:CC 33) (ge:CC (match_operand:DF 0 "register_operand" "v")
385	(match_operand:DF 1 "csky_const_float0_operand" "i")))]
386	"CSKY_ISA_FEATURE (fpv2_df)"
387	"fcmpzhsd\t%0")
388
389	(define_insn "*fpuv2_dnez"
390	[(set (reg:CC 33) (ne:CC (match_operand:DF 0 "register_operand" "v")
391	(match_operand:DF 1 "csky_const_float0_operand" "i")))]
392	"CSKY_ISA_FEATURE (fpv2_df)"
393	"fcmpzned\t%0")
394
395
396	;; -------------------------------------------------------------------------
397	;; Float convert instructions
398	;; -------------------------------------------------------------------------
399
400	;; DF <- SF
401	(define_insn "*fpuv2_extendsfdf2"
402	[(set (match_operand:DF 0 "register_operand" "=v")
403	(float_extend:DF (match_operand:SF 1 "register_operand" "v")))]
404	"CSKY_ISA_FEATURE (fpv2_df)"
405	"fstod\t%0, %1")
406
407	;; SF <- DF
408	(define_insn "*fpuv2_truncdfsf2"
409	[(set (match_operand:SF 0 "register_operand" "=v")
410	(float_truncate:SF (match_operand:DF 1 "register_operand" "v")))]
411	"CSKY_ISA_FEATURE (fpv2_df)"
412	"fdtos\t%0, %1")
413
414	;; SF <- SI
415	(define_insn "*fpuv2_floatsisf2"
416	[(set (match_operand:SF 0 "register_operand" "=v")
417	(float:SF (match_operand:SI 1 "register_operand" "v")))]
418	"CSKY_ISA_FEATURE (fpv2_sf)"
419	"fsitos\t%0, %1")
420
421	;; DF <- SI
422	(define_insn "*fpuv2_floatsidf2"
423	[(set (match_operand:DF 0 "register_operand" "=v")
424	(float:DF (match_operand:SI 1 "register_operand" "v")))]
425	"CSKY_ISA_FEATURE (fpv2_df)"
426	"fsitod\t%0, %1")
427
428	;; SF <- unsigned SI
429	(define_insn "*fpuv2_floatunssisf2"
430	[(set (match_operand:SF 0 "register_operand" "=v")
431	(unsigned_float:SF (match_operand:SI 1 "register_operand" "v")))]
432	"CSKY_ISA_FEATURE (fpv2_sf)"
433	"fuitos\t%0, %1")
434
435	;; DF <- unsigned SI
436	(define_insn "*fpuv2_floatunssidf2"
437	[(set (match_operand:DF 0 "register_operand" "=v")
438	(unsigned_float:DF (match_operand:SI 1 "register_operand" "v")))]
439	"CSKY_ISA_FEATURE (fpv2_df)"
440	"fuitod\t%0, %1")
441
442	;; SI <- SF
443	(define_insn "*fpuv2_fix_truncsfsi2"
444	[(set (match_operand:SI 0 "register_operand" "=v")
445	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "v"))))]
446	"CSKY_ISA_FEATURE (fpv2_sf)"
447	"fstosi.rz\t%0, %1")
448
449	;; SI <- DF
450	(define_insn "*fpuv2_fix_truncdfsi2"
451	[(set (match_operand:SI 0 "register_operand" "=v")
452	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "v"))))]
453	"CSKY_ISA_FEATURE (fpv2_df)"
454	"fdtosi.rz\t%0, %1")
455
456	;; unsigned SI <- SF
457	(define_insn "*fpuv2_fixuns_truncsfsi2"
458	[(set (match_operand:SI 0 "register_operand" "=v")
459	(unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "v"))))]
460	"CSKY_ISA_FEATURE (fpv2_sf)"
461	"fstoui.rz\t%0, %1")
462
463	;; unsigned SI <- DF
464	(define_insn "*fpuv2_fixuns_truncdfsi2"
465	[(set (match_operand:SI 0 "register_operand" "=v")
466	(unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "v"))))]
467	"CSKY_ISA_FEATURE (fpv2_df)"
468	"fdtoui.rz\t%0, %1")
469
470
471	;; -------------------------------------------------------------------------
472	;; Float mov instructions
473	;; -------------------------------------------------------------------------
474
475	(define_insn "*fpuv2_movsf"
476	[(set (match_operand:SF 0 "nonimmediate_operand" "=r,r, r,m,v,r,Q,v,v,v")
477	(match_operand:SF 1 "general_operand" " r,m,mF,r,r,v,v,Q,v,W"))]
478	"CSKY_ISA_FEATURE (fpv2_sf)"
479	"* return csky_output_move(insn, operands, SFmode);"
480	)
481
482	(define_insn "*fpuv2_movdf"
41eba35b GQ	483	[(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v,r, r,Y")
41eba35b GQ	484	(match_operand:DF 1 "general_operand" " r,?r, v,v,Q,v,m,Y,YF,r"))]
db92bd22 GQ	485	"CSKY_ISA_FEATURE (fpv2_df)"
	486	"* return csky_output_movedouble(operands, DFmode);"
	487	[(set (attr "length")
	488	(symbol_ref "csky_get_movedouble_length (operands)"))]
	489	)