]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/gcn/gcn-opts.h
amdgcn: Add gfx1103 target
[thirdparty/gcc.git] / gcc / config / gcn / gcn-opts.h
CommitLineData
a945c346 1/* Copyright (C) 2016-2024 Free Software Foundation, Inc.
5326695a
AS
2
3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 3 of the License, or (at your option)
6 any later version.
7
8 This file is distributed in the hope that it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 for more details.
12
13 You should have received a copy of the GNU General Public License
14 along with GCC; see the file COPYING3. If not see
15 <http://www.gnu.org/licenses/>. */
16
17#ifndef GCN_OPTS_H
18#define GCN_OPTS_H
19
20/* Which processor to generate code or schedule for. */
21enum processor_type
22{
f062c3f1
AS
23 PROCESSOR_FIJI, // gfx803
24 PROCESSOR_VEGA10, // gfx900
3535402e 25 PROCESSOR_VEGA20, // gfx906
cde52d3a 26 PROCESSOR_GFX908,
c7ec7bd1 27 PROCESSOR_GFX90a,
52a2c659 28 PROCESSOR_GFX1030,
1bf18629
AS
29 PROCESSOR_GFX1100,
30 PROCESSOR_GFX1103
5326695a
AS
31};
32
e41b2433
PAA
33#define TARGET_FIJI (gcn_arch == PROCESSOR_FIJI)
34#define TARGET_VEGA10 (gcn_arch == PROCESSOR_VEGA10)
35#define TARGET_VEGA20 (gcn_arch == PROCESSOR_VEGA20)
36#define TARGET_GFX908 (gcn_arch == PROCESSOR_GFX908)
37#define TARGET_GFX90a (gcn_arch == PROCESSOR_GFX90a)
c7ec7bd1 38#define TARGET_GFX1030 (gcn_arch == PROCESSOR_GFX1030)
52a2c659 39#define TARGET_GFX1100 (gcn_arch == PROCESSOR_GFX1100)
1bf18629 40#define TARGET_GFX1103 (gcn_arch == PROCESSOR_GFX1103)
e41b2433 41
5326695a 42/* Set in gcn_option_override. */
cde52d3a
AS
43extern enum gcn_isa {
44 ISA_UNKNOWN,
45 ISA_GCN3,
46 ISA_GCN5,
c7ec7bd1 47 ISA_RDNA2,
52a2c659 48 ISA_RDNA3,
cde52d3a
AS
49 ISA_CDNA1,
50 ISA_CDNA2
51} gcn_isa;
52
53#define TARGET_GCN3 (gcn_isa == ISA_GCN3)
54#define TARGET_GCN3_PLUS (gcn_isa >= ISA_GCN3)
55#define TARGET_GCN5 (gcn_isa == ISA_GCN5)
56#define TARGET_GCN5_PLUS (gcn_isa >= ISA_GCN5)
57#define TARGET_CDNA1 (gcn_isa == ISA_CDNA1)
58#define TARGET_CDNA1_PLUS (gcn_isa >= ISA_CDNA1)
59#define TARGET_CDNA2 (gcn_isa == ISA_CDNA2)
60#define TARGET_CDNA2_PLUS (gcn_isa >= ISA_CDNA2)
c7ec7bd1 61#define TARGET_RDNA2 (gcn_isa == ISA_RDNA2)
52a2c659
TB
62#define TARGET_RDNA2_PLUS (gcn_isa >= ISA_RDNA2 && gcn_isa < ISA_CDNA1)
63#define TARGET_RDNA3 (gcn_isa == ISA_RDNA3)
c7ec7bd1 64
cde52d3a
AS
65
66#define TARGET_M0_LDS_LIMIT (TARGET_GCN3)
99890e15 67#define TARGET_PACKED_WORK_ITEMS (TARGET_CDNA2_PLUS || TARGET_RDNA3)
5326695a 68
366e3d30
TB
69#define TARGET_XNACK (flag_xnack != HSACO_ATTR_OFF)
70
71enum hsaco_attr_type
aad32a00 72{
366e3d30
TB
73 HSACO_ATTR_OFF,
74 HSACO_ATTR_ON,
4c12bcbe
AS
75 HSACO_ATTR_ANY,
76 HSACO_ATTR_DEFAULT
aad32a00
AS
77};
78
5326695a 79#endif