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amdgcn: Add gfx1103 target
[thirdparty/gcc.git] / gcc / config / gcn / gcn.h
CommitLineData
a945c346 1/* Copyright (C) 2016-2024 Free Software Foundation, Inc.
5326695a
AS		 2
3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 3 of the License, or (at your option)
6 any later version.
7
8 This file is distributed in the hope that it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 for more details.
12
13 You should have received a copy of the GNU General Public License
14 along with GCC; see the file COPYING3. If not see
15 <http://www.gnu.org/licenses/>. */
16
17#include "config/gcn/gcn-opts.h"
18
e41b2433
PAA		 19#define TARGET_CPU_CPP_BUILTINS() \
20 do \
21 { \
22 builtin_define ("__AMDGCN__"); \
23 if (TARGET_GCN3) \
24 builtin_define ("__GCN3__"); \
25 else if (TARGET_GCN5) \
26 builtin_define ("__GCN5__"); \
27 else if (TARGET_CDNA1) \
28 builtin_define ("__CDNA1__"); \
29 else if (TARGET_CDNA2) \
30 builtin_define ("__CDNA2__"); \
c7ec7bd1
AS		 31 else if (TARGET_RDNA2) \
32 builtin_define ("__RDNA2__"); \
52a2c659
TB		 33 else if (TARGET_RDNA3) \
34 builtin_define ("__RDNA3__"); \
159174f2
TS		 35 else \
36 gcc_unreachable (); \
e41b2433
PAA		 37 if (TARGET_FIJI) \
38 { \
39 builtin_define ("__fiji__"); \
40 builtin_define ("__gfx803__"); \
41 } \
42 else if (TARGET_VEGA10) \
43 builtin_define ("__gfx900__"); \
44 else if (TARGET_VEGA20) \
45 builtin_define ("__gfx906__"); \
46 else if (TARGET_GFX908) \
47 builtin_define ("__gfx908__"); \
159174f2
TS		 48 else if (TARGET_GFX90a) \
49 builtin_define ("__gfx90a__"); \
52a2c659
TB		 50 else if (TARGET_GFX1030) \
51 builtin_define ("__gfx1030"); \
52 else if (TARGET_GFX1100) \
53 builtin_define ("__gfx1100__"); \
1bf18629
AS		 54 else if (TARGET_GFX1103) \
55 builtin_define ("__gfx1103__"); \
159174f2
TS		 56 else \
57 gcc_unreachable (); \
e41b2433 58 } while (0)
5326695a 59
52a2c659 60#define ASSEMBLER_DIALECT (TARGET_RDNA2_PLUS ? 1 : 0)
c7ec7bd1 61
5326695a
AS		 62/* Support for a compile-time default architecture and tuning.
63 The rules are:
64 --with-arch is ignored if -march is specified.
65 --with-tune is ignored if -mtune is specified. */
66#define OPTION_DEFAULT_SPECS \
67 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
68 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }
69
70/* Default target_flags if no switches specified. */
71#ifndef TARGET_DEFAULT
72#define TARGET_DEFAULT 0
73#endif
74
75\f
76/* Storage Layout */
77#define BITS_BIG_ENDIAN 0
78#define BYTES_BIG_ENDIAN 0
79#define WORDS_BIG_ENDIAN 0
80
a8a730cd
JB		 81#ifdef IN_LIBGCC2
82/* We want DImode and TImode helpers. */
83#define UNITS_PER_WORD 8
84#else
85#define UNITS_PER_WORD 4
86#endif
5326695a
AS		 87
88#define POINTER_SIZE 64
89#define PARM_BOUNDARY 64
90#define STACK_BOUNDARY 64
91#define FUNCTION_BOUNDARY 32
92#define BIGGEST_ALIGNMENT 64
93#define EMPTY_FIELD_BOUNDARY 32
a8a730cd 94#define MAX_FIXED_MODE_SIZE 128
5326695a
AS		 95#define MAX_REGS_PER_ADDRESS 2
96#define STACK_SIZE_MODE DImode
97#define Pmode DImode
98#define CASE_VECTOR_MODE DImode
99#define FUNCTION_MODE QImode
100
101#define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
102#define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64)
103#define STACK_SLOT_ALIGNMENT(TYPE,MODE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64)
104#define STRICT_ALIGNMENT 1
105
106/* Type Layout: match what x86_64 does. */
107#define INT_TYPE_SIZE 32
108#define LONG_TYPE_SIZE 64
109#define LONG_LONG_TYPE_SIZE 64
110#define FLOAT_TYPE_SIZE 32
111#define DOUBLE_TYPE_SIZE 64
112#define LONG_DOUBLE_TYPE_SIZE 64
113#define DEFAULT_SIGNED_CHAR 1
114#define PCC_BITFIELD_TYPE_MATTERS 1
115
116/* Frame Layout */
117#define FRAME_GROWS_DOWNWARD 0
118#define ARGS_GROW_DOWNWARD 1
119#define STACK_POINTER_OFFSET 0
120#define FIRST_PARM_OFFSET(FNDECL) 0
121#define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16)
122#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM)
251697a6 123#define DWARF_FRAME_RETURN_COLUMN 16
5326695a
AS		 124#define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size)
125#define ACCUMULATE_OUTGOING_ARGS 1
126#define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \
127 ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, LINK_REGNUM) : NULL_RTX)
128\f
129/* Register Basics */
130#define FIRST_SGPR_REG 0
131#define SGPR_REGNO(N) ((N)+FIRST_SGPR_REG)
132#define LAST_SGPR_REG 101
133
134#define FLAT_SCRATCH_REG 102
135#define FLAT_SCRATCH_LO_REG 102
136#define FLAT_SCRATCH_HI_REG 103
137#define XNACK_MASK_REG 104
138#define XNACK_MASK_LO_REG 104
139#define XNACK_MASK_HI_REG 105
140#define VCC_LO_REG 106
141#define VCC_HI_REG 107
142#define VCCZ_REG 108
143#define TBA_REG 109
144#define TBA_LO_REG 109
145#define TBA_HI_REG 110
146#define TMA_REG 111
147#define TMA_LO_REG 111
148#define TMA_HI_REG 112
149#define TTMP0_REG 113
150#define TTMP11_REG 124
151#define M0_REG 125
152#define EXEC_REG 126
153#define EXEC_LO_REG 126
154#define EXEC_HI_REG 127
155#define EXECZ_REG 128
156#define SCC_REG 129
a5eb246e 157
5326695a 158/* 132-159 are reserved to simplify masks. */
a5eb246e 159
5326695a
AS		 160#define FIRST_VGPR_REG 160
161#define VGPR_REGNO(N) ((N)+FIRST_VGPR_REG)
162#define LAST_VGPR_REG 415
a5eb246e 163
ae0d2c24
AS		 164#define FIRST_AVGPR_REG 416
165#define AVGPR_REGNO(N) ((N)+FIRST_AVGPR_REG)
166#define LAST_AVGPR_REG 671
5326695a 167
a5eb246e
TS		 168#ifndef USED_FOR_TARGET
169STATIC_ASSERT (LAST_SGPR_REG + 1 - FIRST_SGPR_REG == 102);
170STATIC_ASSERT (LAST_VGPR_REG + 1 - FIRST_VGPR_REG == 256);
171STATIC_ASSERT (LAST_AVGPR_REG + 1 - FIRST_AVGPR_REG == 256);
172#endif /* USED_FOR_TARGET */
173
5326695a
AS		 174/* Frame Registers, and other registers */
175
176#define HARD_FRAME_POINTER_REGNUM 14
177#define STACK_POINTER_REGNUM 16
178#define LINK_REGNUM 18
179#define EXEC_SAVE_REG 20
180#define CC_SAVE_REG 22
4e191462 181#define RETURN_VALUE_REG 168 /* Must be divisible by 4. */
5326695a
AS		 182#define STATIC_CHAIN_REGNUM 30
183#define WORK_ITEM_ID_Z_REG 162
ae0d2c24
AS		 184#define SOFT_ARG_REG 672
185#define FRAME_POINTER_REGNUM 674
186#define DWARF_LINK_REGISTER 676
187#define FIRST_PSEUDO_REGISTER 677
5326695a 188
4e191462
AS		 189#define FIRST_PARM_REG (FIRST_SGPR_REG + 24)
190#define FIRST_VPARM_REG (FIRST_VGPR_REG + 8)
5326695a
AS		 191#define NUM_PARM_REGS 6
192
193/* There is no arg pointer. Just choose random fixed register that does
194 not intefere with anything. */
195#define ARG_POINTER_REGNUM SOFT_ARG_REG
196
197#define HARD_FRAME_POINTER_IS_ARG_POINTER 0
198#define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
199
a5eb246e
TS		 200#define SGPR_REGNO_P(N) ((N) >= FIRST_SGPR_REG && (N) <= LAST_SGPR_REG)
201#define VGPR_REGNO_P(N) ((N) >= FIRST_VGPR_REG && (N) <= LAST_VGPR_REG)
202#define AVGPR_REGNO_P(N) ((N) >= FIRST_AVGPR_REG && (N) <= LAST_AVGPR_REG)
5326695a
AS		 203#define SSRC_REGNO_P(N) ((N) <= SCC_REG && (N) != VCCZ_REG)
204#define SDST_REGNO_P(N) ((N) <= EXEC_HI_REG && (N) != VCCZ_REG)
205#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X)))
206#define CC_REGNO_P(X) ((X) == SCC_REG || (X) == VCC_REG)
207#define FUNCTION_ARG_REGNO_P(N) \
4e191462
AS		 208 (((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS)) \
209 || ((N) >= FIRST_VPARM_REG && (N) < (FIRST_VPARM_REG + NUM_PARM_REGS)))
5326695a
AS		 210
211\f
212#define FIXED_REGISTERS { \
213 /* Scalars. */ \
f6fff8a6 214 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
5326695a 215/* fp sp lr. */ \
969089ff 216 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, \
5326695a
AS		 217/* exec_save, cc_save */ \
218 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
223 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
225 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
226 /* Special regs and padding. */ \
227/* flat xnack vcc tba tma ttmp */ \
228 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
229/* m0 exec scc */ \
230 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, \
231 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
232 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
ae0d2c24 233 /* VGPRs */ \
342f9464 234 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5326695a
AS		 235 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
245 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
247 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
248 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
249 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
ae0d2c24
AS		 250 /* Accumulation VGPRs */ \
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
252 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
258 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
259 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
260 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
5326695a 267 /* Other registers. */ \
251697a6 268 1, 1, 1, 1, 1 \
5326695a
AS		 269}
270
271#define CALL_USED_REGISTERS { \
272 /* Scalars. */ \
273 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
969089ff 274 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, \
5326695a
AS		 275 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
276 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
277 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
278 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
279 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
280 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
281 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
282 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
283 /* Special regs and padding. */ \
284 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
285 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
286 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
287 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
ae0d2c24 288 /* VGPRs */ \
5326695a
AS		 289 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
290 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
291 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
292 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
294 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
297 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
298 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
299 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
300 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
301 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
302 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
303 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
304 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
ae0d2c24
AS		 305 /* Accumulation VGPRs */ \
306 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
307 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
308 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
309 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
310 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
311 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
312 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
313 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
314 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
315 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
317 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
318 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
319 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
320 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
321 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
5326695a 322 /* Other registers. */ \
251697a6 323 1, 1, 1, 1, 1 \
5326695a
AS		 324}
325
326\f
327#define HARD_REGNO_RENAME_OK(FROM, TO) \
328 gcn_hard_regno_rename_ok (FROM, TO)
329
330#define HARD_REGNO_CALLER_SAVE_MODE(HARDREG, NREGS, MODE) \
331 gcn_hard_regno_caller_save_mode ((HARDREG), (NREGS), (MODE))
332
333/* Register Classes */
334
335enum reg_class
336{
337 NO_REGS,
338
339 /* SCC */
340 SCC_CONDITIONAL_REG,
341
342 /* VCCZ */
343 VCCZ_CONDITIONAL_REG,
344
345 /* VCC */
346 VCC_CONDITIONAL_REG,
347
348 /* EXECZ */
349 EXECZ_CONDITIONAL_REG,
350
351 /* SCC VCCZ EXECZ */
352 ALL_CONDITIONAL_REGS,
353
354 /* EXEC */
355 EXEC_MASK_REG,
356
357 /* SGPR0-101 */
358 SGPR_REGS,
359
360 /* SGPR0-101 EXEC_LO/EXEC_HI */
361 SGPR_EXEC_REGS,
362
363 /* SGPR0-101, FLAT_SCRATCH_LO/HI, VCC LO/HI, TBA LO/HI, TMA LO/HI, TTMP0-11,
364 M0, VCCZ, SCC
365 (EXEC_LO/HI, EXECZ excluded to prevent compiler misuse.) */
366 SGPR_VOP_SRC_REGS,
367
368 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
369 TMA LO/HI, TTMP0-11 */
370 SGPR_MEM_SRC_REGS,
371
372 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
373 TMA LO/HI, TTMP0-11, M0, EXEC LO/HI */
374 SGPR_DST_REGS,
375
376 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI
377 TMA LO/HI, TTMP0-11 */
378 SGPR_SRC_REGS,
379 GENERAL_REGS,
380 VGPR_REGS,
ae0d2c24
AS		 381 AVGPR_REGS,
382 ALL_VGPR_REGS,
5326695a
AS		 383 ALL_GPR_REGS,
384 SRCDST_REGS,
385 AFP_REGS,
386 ALL_REGS,
387 LIM_REG_CLASSES
388};
389
390#define N_REG_CLASSES (int) LIM_REG_CLASSES
391
392#define REG_CLASS_NAMES \
393{ "NO_REGS", \
394 "SCC_CONDITIONAL_REG", \
395 "VCCZ_CONDITIONAL_REG", \
396 "VCC_CONDITIONAL_REG", \
397 "EXECZ_CONDITIONAL_REG", \
398 "ALL_CONDITIONAL_REGS", \
399 "EXEC_MASK_REG", \
400 "SGPR_REGS", \
401 "SGPR_EXEC_REGS", \
402 "SGPR_VOP3A_SRC_REGS", \
403 "SGPR_MEM_SRC_REGS", \
404 "SGPR_DST_REGS", \
405 "SGPR_SRC_REGS", \
406 "GENERAL_REGS", \
407 "VGPR_REGS", \
ae0d2c24
AS		 408 "AVGPR_REGS", \
409 "ALL_VGPR_REGS", \
5326695a
AS		 410 "ALL_GPR_REGS", \
411 "SRCDST_REGS", \
412 "AFP_REGS", \
413 "ALL_REGS" \
414}
415
416#define NAMED_REG_MASK(N) (1<<((N)-3*32))
417#define NAMED_REG_MASK2(N) (1<<((N)-4*32))
418
419#define REG_CLASS_CONTENTS { \
420 /* NO_REGS. */ \
421 {0, 0, 0, 0, \
ae0d2c24
AS		 422 0, 0, 0, 0, \
423 0, 0, 0, 0, \
5326695a
AS		 424 0, 0, 0, 0, \
425 0, 0, 0, 0, 0, 0}, \
426 /* SCC_CONDITIONAL_REG. */ \
427 {0, 0, 0, 0, \
428 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 429 0, 0, 0, 0, \
430 0, 0, 0, 0, \
431 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 432 /* VCCZ_CONDITIONAL_REG. */ \
433 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \
ae0d2c24
AS		 434 0, 0, 0, 0, \
435 0, 0, 0, 0, \
5326695a
AS		 436 0, 0, 0, 0, \
437 0, 0, 0, 0, 0, 0}, \
438 /* VCC_CONDITIONAL_REG. */ \
439 {0, 0, 0, NAMED_REG_MASK (VCC_LO_REG)|NAMED_REG_MASK (VCC_HI_REG), \
ae0d2c24
AS		 440 0, 0, 0, 0, \
441 0, 0, 0, 0, \
5326695a
AS		 442 0, 0, 0, 0, \
443 0, 0, 0, 0, 0, 0}, \
444 /* EXECZ_CONDITIONAL_REG. */ \
445 {0, 0, 0, 0, \
446 NAMED_REG_MASK2 (EXECZ_REG), 0, 0, 0, \
ae0d2c24
AS		 447 0, 0, 0, 0, \
448 0, 0, 0, 0, \
449 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 450 /* ALL_CONDITIONAL_REGS. */ \
451 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \
452 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 453 0, 0, 0, 0, \
454 0, 0, 0, 0, \
5326695a
AS		 455 0, 0, 0, 0, 0, 0}, \
456 /* EXEC_MASK_REG. */ \
457 {0, 0, 0, NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \
ae0d2c24
AS		 458 0, 0, 0, 0, \
459 0, 0, 0, 0, \
5326695a
AS		 460 0, 0, 0, 0, \
461 0, 0, 0, 0, 0, 0}, \
462 /* SGPR_REGS. */ \
463 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
ae0d2c24
AS		 464 0, 0, 0, 0, \
465 0, 0, 0, 0, \
5326695a
AS		 466 0, 0, 0, 0, \
467 0, 0, 0, 0, 0, 0}, \
468 /* SGPR_EXEC_REGS. */ \
469 {0xffffffff, 0xffffffff, 0xffffffff, \
470 0xf1 | NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \
471 0, 0, 0, 0, \
ae0d2c24
AS		 472 0, 0, 0, 0, \
473 0, 0, 0, 0, \
5326695a
AS		 474 0, 0, 0, 0, 0, 0}, \
475 /* SGPR_VOP_SRC_REGS. */ \
476 {0xffffffff, 0xffffffff, 0xffffffff, \
477 0xffffffff \
478 -NAMED_REG_MASK (EXEC_LO_REG) \
479 -NAMED_REG_MASK (EXEC_HI_REG), \
480 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 481 0, 0, 0, 0, \
482 0, 0, 0, 0, \
5326695a
AS		 483 0, 0, 0, 0, 0, 0}, \
484 /* SGPR_MEM_SRC_REGS. */ \
485 {0xffffffff, 0xffffffff, 0xffffffff, \
486 0xffffffff-NAMED_REG_MASK (VCCZ_REG)-NAMED_REG_MASK (M0_REG) \
487 -NAMED_REG_MASK (EXEC_LO_REG)-NAMED_REG_MASK (EXEC_HI_REG), \
488 0, 0, 0, 0, \
ae0d2c24
AS		 489 0, 0, 0, 0, \
490 0, 0, 0, 0, \
5326695a
AS		 491 0, 0, 0, 0, 0, 0}, \
492 /* SGPR_DST_REGS. */ \
493 {0xffffffff, 0xffffffff, 0xffffffff, \
494 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \
495 0, 0, 0, 0, \
496 0, 0, 0, 0, 0, 0}, \
497 /* SGPR_SRC_REGS. */ \
498 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
499 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \
ae0d2c24
AS		 500 0, 0, 0, 0, \
501 0, 0, 0, 0, \
5326695a
AS		 502 0, 0, 0, 0, 0, 0}, \
503 /* GENERAL_REGS. */ \
504 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
ae0d2c24
AS		 505 0, 0, 0, 0, \
506 0, 0, 0, 0, \
5326695a
AS		 507 0, 0, 0, 0, \
508 0, 0, 0, 0, 0, 0}, \
509 /* VGPR_REGS. */ \
510 {0, 0, 0, 0, \
511 0, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 512 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
513 0xffffffff, 0, 0, 0, \
514 0, 0, 0, 0, 0, 0}, \
515 /* AVGPR_REGS. */ \
516 {0, 0, 0, 0, \
517 0, 0, 0, 0, \
518 0, 0, 0, 0, \
519 0, 0xffffffff, 0xffffffff, 0xffffffff, \
520 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \
521 /* ALL_VGPR_REGS. */ \
522 {0, 0, 0, 0, \
523 0, 0xffffffff, 0xffffffff, 0xffffffff, \
524 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
525 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
5326695a
AS		 526 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \
527 /* ALL_GPR_REGS. */ \
528 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \
529 0, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 530 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
531 0xffffffff, 0, 0, 0, \
532 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 533 /* SRCDST_REGS. */ \
534 {0xffffffff, 0xffffffff, 0xffffffff, \
535 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \
536 0, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 537 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
538 0xffffffff, 0, 0, 0, \
539 0, 0, 0, 0, 0, 0}, \
5326695a
AS		 540 /* AFP_REGS. */ \
541 {0, 0, 0, 0, \
ae0d2c24
AS		 542 0, 0, 0, 0, \
543 0, 0, 0, 0, \
5326695a
AS		 544 0, 0, 0, 0, \
545 0, 0, 0, 0, 0, 0xf}, \
546 /* ALL_REGS. */ \
547 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
ae0d2c24
AS		 548 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
549 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
5326695a
AS		 550 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \
551 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0 }}
552
553#define REGNO_REG_CLASS(REGNO) gcn_regno_reg_class (REGNO)
554#define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
555 gcn_mode_code_base_reg_class (MODE, AS, OUTER, INDEX)
556#define REGNO_MODE_CODE_OK_FOR_BASE_P(NUM, MODE, AS, OUTER, INDEX) \
557 gcn_regno_mode_code_ok_for_base_p (NUM, MODE, AS, OUTER, INDEX)
558#define INDEX_REG_CLASS VGPR_REGS
559#define REGNO_OK_FOR_INDEX_P(regno) regno_ok_for_index_p (regno)
560
561\f
562/* Address spaces. */
563enum gcn_address_spaces
564{
565 ADDR_SPACE_DEFAULT = 0,
566 ADDR_SPACE_FLAT,
567 ADDR_SPACE_SCALAR_FLAT,
568 ADDR_SPACE_FLAT_SCRATCH,
569 ADDR_SPACE_LDS,
570 ADDR_SPACE_GDS,
571 ADDR_SPACE_SCRATCH,
572 ADDR_SPACE_GLOBAL
573};
574#define REGISTER_TARGET_PRAGMAS() do { \
575 c_register_addr_space ("__flat", ADDR_SPACE_FLAT); \
576 c_register_addr_space ("__flat_scratch", ADDR_SPACE_FLAT_SCRATCH); \
577 c_register_addr_space ("__scalar_flat", ADDR_SPACE_SCALAR_FLAT); \
578 c_register_addr_space ("__lds", ADDR_SPACE_LDS); \
579 c_register_addr_space ("__gds", ADDR_SPACE_GDS); \
580 c_register_addr_space ("__global", ADDR_SPACE_GLOBAL); \
581} while (0);
582
583#define STACK_ADDR_SPACE \
584 (TARGET_GCN5_PLUS ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT)
585#define DEFAULT_ADDR_SPACE \
586 ((cfun && cfun->machine && !cfun->machine->use_flat_addressing) \
587 ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT)
588#define AS_SCALAR_FLAT_P(AS) ((AS) == ADDR_SPACE_SCALAR_FLAT)
589#define AS_FLAT_SCRATCH_P(AS) ((AS) == ADDR_SPACE_FLAT_SCRATCH)
590#define AS_FLAT_P(AS) ((AS) == ADDR_SPACE_FLAT \
591 || ((AS) == ADDR_SPACE_DEFAULT \
592 && DEFAULT_ADDR_SPACE == ADDR_SPACE_FLAT))
593#define AS_LDS_P(AS) ((AS) == ADDR_SPACE_LDS)
594#define AS_GDS_P(AS) ((AS) == ADDR_SPACE_GDS)
595#define AS_SCRATCH_P(AS) ((AS) == ADDR_SPACE_SCRATCH)
596#define AS_GLOBAL_P(AS) ((AS) == ADDR_SPACE_GLOBAL \
597 || ((AS) == ADDR_SPACE_DEFAULT \
598 && DEFAULT_ADDR_SPACE == ADDR_SPACE_GLOBAL))
599#define AS_ANY_FLAT_P(AS) (AS_FLAT_SCRATCH_P (AS) || AS_FLAT_P (AS))
600#define AS_ANY_DS_P(AS) (AS_LDS_P (AS) || AS_GDS_P (AS))
601
602\f
603/* Instruction Output */
604#define REGISTER_NAMES \
605 {"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", \
606 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", \
607 "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", \
608 "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", \
609 "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", "s50", \
610 "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59", "s60", \
611 "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69", "s70", \
612 "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", "s80", \
613 "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89", "s90", \
614 "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99", \
615 "s100", "s101", \
616 "flat_scratch_lo", "flat_scratch_hi", "xnack_mask_lo", "xnack_mask_hi", \
617 "vcc_lo", "vcc_hi", "vccz", "tba_lo", "tba_hi", "tma_lo", "tma_hi", \
618 "ttmp0", "ttmp1", "ttmp2", "ttmp3", "ttmp4", "ttmp5", "ttmp6", "ttmp7", \
619 "ttmp8", "ttmp9", "ttmp10", "ttmp11", "m0", "exec_lo", "exec_hi", \
620 "execz", "scc", \
621 "res130", "res131", "res132", "res133", "res134", "res135", "res136", \
622 "res137", "res138", "res139", "res140", "res141", "res142", "res143", \
623 "res144", "res145", "res146", "res147", "res148", "res149", "res150", \
624 "res151", "res152", "res153", "res154", "res155", "res156", "res157", \
625 "res158", "res159", \
626 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", \
627 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", \
628 "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", \
629 "v31", "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", "v40", \
630 "v41", "v42", "v43", "v44", "v45", "v46", "v47", "v48", "v49", "v50", \
631 "v51", "v52", "v53", "v54", "v55", "v56", "v57", "v58", "v59", "v60", \
632 "v61", "v62", "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", \
633 "v71", "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", \
634 "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", "v90", \
635 "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", "v99", "v100", \
636 "v101", "v102", "v103", "v104", "v105", "v106", "v107", "v108", "v109", \
637 "v110", "v111", "v112", "v113", "v114", "v115", "v116", "v117", "v118", \
638 "v119", "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", \
639 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", "v136", \
640 "v137", "v138", "v139", "v140", "v141", "v142", "v143", "v144", "v145", \
641 "v146", "v147", "v148", "v149", "v150", "v151", "v152", "v153", "v154", \
642 "v155", "v156", "v157", "v158", "v159", "v160", "v161", "v162", "v163", \
643 "v164", "v165", "v166", "v167", "v168", "v169", "v170", "v171", "v172", \
644 "v173", "v174", "v175", "v176", "v177", "v178", "v179", "v180", "v181", \
645 "v182", "v183", "v184", "v185", "v186", "v187", "v188", "v189", "v190", \
646 "v191", "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", \
647 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", "v208", \
648 "v209", "v210", "v211", "v212", "v213", "v214", "v215", "v216", "v217", \
649 "v218", "v219", "v220", "v221", "v222", "v223", "v224", "v225", "v226", \
650 "v227", "v228", "v229", "v230", "v231", "v232", "v233", "v234", "v235", \
651 "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \
652 "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \
653 "v254", "v255", \
ae0d2c24
AS		 654 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", "a9", "a10", \
655 "a11", "a12", "a13", "a14", "a15", "a16", "a17", "a18", "a19", "a20", \
656 "a21", "a22", "a23", "a24", "a25", "a26", "a27", "a28", "a29", "a30", \
657 "a31", "a32", "a33", "a34", "a35", "a36", "a37", "a38", "a39", "a40", \
658 "a41", "a42", "a43", "a44", "a45", "a46", "a47", "a48", "a49", "a50", \
659 "a51", "a52", "a53", "a54", "a55", "a56", "a57", "a58", "a59", "a60", \
660 "a61", "a62", "a63", "a64", "a65", "a66", "a67", "a68", "a69", "a70", \
661 "a71", "a72", "a73", "a74", "a75", "a76", "a77", "a78", "a79", "a80", \
662 "a81", "a82", "a83", "a84", "a85", "a86", "a87", "a88", "a89", "a90", \
663 "a91", "a92", "a93", "a94", "a95", "a96", "a97", "a98", "a99", "a100", \
664 "a101", "a102", "a103", "a104", "a105", "a106", "a107", "a108", "a109", \
665 "a110", "a111", "a112", "a113", "a114", "a115", "a116", "a117", "a118", \
666 "a119", "a120", "a121", "a122", "a123", "a124", "a125", "a126", "a127", \
667 "a128", "a129", "a130", "a131", "a132", "a133", "a134", "a135", "a136", \
668 "a137", "a138", "a139", "a140", "a141", "a142", "a143", "a144", "a145", \
669 "a146", "a147", "a148", "a149", "a150", "a151", "a152", "a153", "a154", \
670 "a155", "a156", "a157", "a158", "a159", "a160", "a161", "a162", "a163", \
671 "a164", "a165", "a166", "a167", "a168", "a169", "a170", "a171", "a172", \
672 "a173", "a174", "a175", "a176", "a177", "a178", "a179", "a180", "a181", \
673 "a182", "a183", "a184", "a185", "a186", "a187", "a188", "a189", "a190", \
674 "a191", "a192", "a193", "a194", "a195", "a196", "a197", "a198", "a199", \
675 "a200", "a201", "a202", "a203", "a204", "a205", "a206", "a207", "a208", \
676 "a209", "a210", "a211", "a212", "a213", "a214", "a215", "a216", "a217", \
677 "a218", "a219", "a220", "a221", "a222", "a223", "a224", "a225", "a226", \
678 "a227", "a228", "a229", "a230", "a231", "a232", "a233", "a234", "a235", \
679 "a236", "a237", "a238", "a239", "a240", "a241", "a242", "a243", "a244", \
680 "a245", "a246", "a247", "a248", "a249", "a250", "a251", "a252", "a253", \
681 "a254", "a255", \
251697a6 682 "?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" }
5326695a
AS		 683
684#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE)
685#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
686#define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '^')
687
688\f
689/* Register Arguments */
690
691#ifndef USED_FOR_TARGET
692
f062c3f1 693#define GCN_KERNEL_ARG_TYPES 16
5326695a
AS		 694struct GTY(()) gcn_kernel_args
695{
696 long requested;
697 int reg[GCN_KERNEL_ARG_TYPES];
698 int order[GCN_KERNEL_ARG_TYPES];
699 int nargs, nsgprs;
700};
701
702typedef struct gcn_args
703{
704 /* True if this isn't a kernel (HSA runtime entrypoint). */
705 bool normal_function;
706 tree fntype;
707 struct gcn_kernel_args args;
708 int num;
4e191462 709 int vnum;
5326695a
AS		 710 int offset;
711 int alignment;
712} CUMULATIVE_ARGS;
713#endif
714
715#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
716 gcn_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \
717 (N_NAMED_ARGS) != -1)
718
719\f
720#ifndef USED_FOR_TARGET
721
722#include "hash-table.h"
723#include "hash-map.h"
724#include "vec.h"
725
726struct GTY(()) machine_function
727{
728 struct gcn_kernel_args args;
729 int kernarg_segment_alignment;
730 int kernarg_segment_byte_size;
731 /* Frame layout info for normal functions. */
732 bool normal_function;
733 bool need_frame_pointer;
734 bool lr_needs_saving;
735 HOST_WIDE_INT outgoing_args_size;
736 HOST_WIDE_INT pretend_size;
737 HOST_WIDE_INT local_vars;
738 HOST_WIDE_INT callee_saves;
739
2a3f9f65
JB		 740 unsigned HOST_WIDE_INT reduction_base;
741 unsigned HOST_WIDE_INT reduction_limit;
5326695a
AS		 742
743 bool use_flat_addressing;
744};
745#endif
746
747\f
748/* Codes for all the GCN builtins. */
749
750enum gcn_builtin_codes
751{
752#define DEF_BUILTIN(fcode, icode, name, type, params, expander) \
753 GCN_BUILTIN_ ## fcode,
754#define DEF_BUILTIN_BINOP_INT_FP(fcode, ic, name) \
755 GCN_BUILTIN_ ## fcode ## _V64SI, \
756 GCN_BUILTIN_ ## fcode ## _V64SI_unspec,
757#include "gcn-builtins.def"
758#undef DEF_BUILTIN
759#undef DEF_BUILTIN_BINOP_INT_FP
760 GCN_BUILTIN_MAX
761};
762
763\f
764/* Misc */
765
766/* We can load/store 128-bit quantities, but having this larger than
767 MAX_FIXED_MODE_SIZE (which we want to be 64 bits) causes problems. */
768#define MOVE_MAX 8
769
770#define AVOID_CCMODE_COPIES 1
771#define SLOW_BYTE_ACCESS 0
772#define WORD_REGISTER_OPERATIONS 1
773
dbde9e2d
AS		 774/* Flag values are either BImode or DImode, but either way the compiler
775 should assume that all the bits are live. */
776#define STORE_FLAG_VALUE -1
777
5326695a
AS		 778/* Definitions for register eliminations.
779
780 This is an array of structures. Each structure initializes one pair
781 of eliminable registers. The "from" register number is given first,
782 followed by "to". Eliminations of the same "from" register are listed
783 in order of preference. */
784
785#define ELIMINABLE_REGS \
786{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
787 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
788 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
789 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }}
790
791/* Define the offset between two registers, one to be eliminated, and the
792 other its replacement, at the start of a routine. */
793
794#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
795 ((OFFSET) = gcn_initial_elimination_offset ((FROM), (TO)))
796
797
798/* Define this macro if it is advisable to hold scalars in registers
799 in a wider mode than that declared by the program. In such cases,
800 the value is constrained to be within the bounds of the declared
801 type, but kept valid in the wider mode. The signedness of the
802 extension may differ from that of the type. */
803
804#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
805 if (GET_MODE_CLASS (MODE) == MODE_INT \
806 && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \
807 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
808 { \
809 (MODE) = SImode; \
810 }
811
812/* This needs to match gcn_function_value. */
4e191462 813#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, RETURN_VALUE_REG)
5326695a 814
34bac264
AS		 815/* The s_ff0 and s_flbit instructions return -1 if no input bits are set. */
816#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
817#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2)
818
5326695a
AS		 819\f
820/* Costs. */
821
822/* Branches are to be dicouraged when theres an alternative.
823 FIXME: This number is plucked from the air. */
824#define BRANCH_COST(SPEED_P, PREDICABLE_P) 10
825
826\f
827/* Profiling */
828#define FUNCTION_PROFILER(FILE, LABELNO)
829#define NO_PROFILE_COUNTERS 1
830#define PROFILE_BEFORE_PROLOGUE 0
831
832/* Trampolines */
833#define TRAMPOLINE_SIZE 36
834#define TRAMPOLINE_ALIGNMENT 64
0d8753cf
AS		 835
836/* MD Optimization.
837 The following are intended to be obviously constant at compile time to
838 allow genconditions to eliminate bad patterns at compile time. */
839#define MODE_VF(M) \
840 ((M == V64QImode || M == V64HImode || M == V64HFmode || M == V64SImode \
841 || M == V64SFmode || M == V64DImode || M == V64DFmode) \
842 ? 64 \
843 : (M == V32QImode || M == V32HImode || M == V32HFmode || M == V32SImode \
844 || M == V32SFmode || M == V32DImode || M == V32DFmode) \
845 ? 32 \
846 : (M == V16QImode || M == V16HImode || M == V16HFmode || M == V16SImode \
847 || M == V16SFmode || M == V16DImode || M == V16DFmode) \
848 ? 16 \
849 : (M == V8QImode || M == V8HImode || M == V8HFmode || M == V8SImode \
850 || M == V8SFmode || M == V8DImode || M == V8DFmode) \
851 ? 8 \
852 : (M == V4QImode || M == V4HImode || M == V4HFmode || M == V4SImode \
853 || M == V4SFmode || M == V4DImode || M == V4DFmode) \
854 ? 4 \
855 : (M == V2QImode || M == V2HImode || M == V2HFmode || M == V2SImode \
856 || M == V2SFmode || M == V2DImode || M == V2DFmode) \
857 ? 2 \
858 : 1)
4d9d015c
TS		 859
860/* The C++ front end insists to link against libstdc++ -- which we don't build.
861 Tell it to instead link against the innocuous libgcc. */
862#define LIBSTDCXX "gcc"
Mirror of https://gcc.gnu.org/git/gcc.git