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b6837b94 | 1 | ;; Atom Scheduling |
83ffe9cd | 2 | ;; Copyright (C) 2009-2023 Free Software Foundation, Inc. |
b6837b94 JY |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 3, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GCC; see the file COPYING3. If not see | |
18 | ;; <http://www.gnu.org/licenses/>. | |
19 | ;; | |
20 | ;; Atom is an in-order core with two integer pipelines. | |
21 | ||
22 | ||
23 | (define_attr "atom_unit" "sishuf,simul,jeu,complex,other" | |
24 | (const_string "other")) | |
25 | ||
26 | (define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other" | |
27 | (const_string "other")) | |
28 | ||
29 | (define_automaton "atom") | |
30 | ||
31 | ;; Atom has two ports: port 0 and port 1 connecting to all execution units | |
32 | (define_cpu_unit "atom-port-0,atom-port-1" "atom") | |
33 | ||
34 | ;; EU: Execution Unit | |
35 | ;; Atom EUs are connected by port 0 or port 1. | |
36 | ||
37 | (define_cpu_unit "atom-eu-0, atom-eu-1, | |
38 | atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4" | |
39 | "atom") | |
40 | ||
41 | ;; Some EUs have duplicated copied and can be accessed via either | |
42 | ;; port 0 or port 1 | |
43 | ;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)") | |
44 | ||
45 | ;;; Some instructions is dual-pipe execution, need both ports | |
46 | ;;; Complex multi-op macro-instructoins need both ports and all EUs | |
47 | (define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)") | |
48 | (define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 + | |
49 | atom-imul-1 + atom-imul-2 + atom-imul-3 + | |
50 | atom-imul-4)") | |
51 | ||
52 | ;;; Most of simple instructions have 1 cycle latency. Some of them | |
53 | ;;; issue in port 0, some in port 0 and some in either port. | |
54 | (define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)") | |
55 | (define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)") | |
56 | (define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)") | |
57 | ||
58 | ;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput | |
59 | (define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)") | |
60 | ||
61 | ;;; fmul insn can have 4 or 5 cycles latency | |
62 | (define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4") | |
63 | (define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3") | |
64 | ||
65 | ;;; fadd can has 5 cycles latency depends on instruction forms | |
66 | (define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5") | |
67 | ||
68 | ;;; imul insn has 5 cycles latency | |
69 | (define_reservation "atom-imul-32" | |
70 | "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4, | |
71 | atom-port-0") | |
72 | ;;; imul instruction excludes other non-FP instructions. | |
73 | (exclusion_set "atom-eu-0, atom-eu-1" | |
74 | "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4") | |
75 | ||
76 | ;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on | |
77 | ;;; instruction forms | |
78 | (define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)") | |
79 | (define_reservation "atom-dual-2c" | |
80 | "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)") | |
81 | (define_reservation "atom-dual-5c" | |
82 | "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)") | |
83 | ||
84 | ;;; Complex macro-instruction has variants of latency, and uses both ports. | |
85 | (define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)") | |
86 | ||
87 | (define_insn_reservation "atom_other" 9 | |
88 | (and (eq_attr "cpu" "atom") | |
89 | (and (eq_attr "type" "other") | |
90 | (eq_attr "atom_unit" "!jeu"))) | |
91 | "atom-complex, atom-all-eu*8") | |
92 | ||
93 | ;; return has type "other" with atom_unit "jeu" | |
94 | (define_insn_reservation "atom_other_2" 1 | |
95 | (and (eq_attr "cpu" "atom") | |
96 | (and (eq_attr "type" "other") | |
97 | (eq_attr "atom_unit" "jeu"))) | |
98 | "atom-dual-1c") | |
99 | ||
100 | (define_insn_reservation "atom_multi" 9 | |
101 | (and (eq_attr "cpu" "atom") | |
102 | (eq_attr "type" "multi")) | |
103 | "atom-complex, atom-all-eu*8") | |
104 | ||
105 | ;; Normal alu insns without carry | |
106 | (define_insn_reservation "atom_alu" 1 | |
107 | (and (eq_attr "cpu" "atom") | |
108 | (and (eq_attr "type" "alu") | |
109 | (and (eq_attr "memory" "none") | |
110 | (eq_attr "use_carry" "0")))) | |
111 | "atom-simple-either") | |
112 | ||
113 | ;; Normal alu insns without carry | |
114 | (define_insn_reservation "atom_alu_mem" 1 | |
115 | (and (eq_attr "cpu" "atom") | |
116 | (and (eq_attr "type" "alu") | |
117 | (and (eq_attr "memory" "!none") | |
118 | (eq_attr "use_carry" "0")))) | |
119 | "atom-simple-either") | |
120 | ||
121 | ;; Alu insn consuming CF, such as add/sbb | |
122 | (define_insn_reservation "atom_alu_carry" 1 | |
123 | (and (eq_attr "cpu" "atom") | |
124 | (and (eq_attr "type" "alu") | |
125 | (and (eq_attr "memory" "none") | |
126 | (eq_attr "use_carry" "1")))) | |
127 | "atom-simple-either") | |
128 | ||
129 | ;; Alu insn consuming CF, such as add/sbb | |
130 | (define_insn_reservation "atom_alu_carry_mem" 1 | |
131 | (and (eq_attr "cpu" "atom") | |
132 | (and (eq_attr "type" "alu") | |
133 | (and (eq_attr "memory" "!none") | |
134 | (eq_attr "use_carry" "1")))) | |
135 | "atom-simple-either") | |
136 | ||
137 | (define_insn_reservation "atom_alu1" 1 | |
138 | (and (eq_attr "cpu" "atom") | |
139 | (and (eq_attr "type" "alu1") | |
140 | (eq_attr "memory" "none"))) | |
141 | "atom-simple-either") | |
142 | ||
143 | (define_insn_reservation "atom_alu1_mem" 1 | |
144 | (and (eq_attr "cpu" "atom") | |
145 | (and (eq_attr "type" "alu1") | |
146 | (eq_attr "memory" "!none"))) | |
147 | "atom-simple-either") | |
148 | ||
149 | (define_insn_reservation "atom_negnot" 1 | |
150 | (and (eq_attr "cpu" "atom") | |
151 | (and (eq_attr "type" "negnot") | |
152 | (eq_attr "memory" "none"))) | |
153 | "atom-simple-either") | |
154 | ||
155 | (define_insn_reservation "atom_negnot_mem" 1 | |
156 | (and (eq_attr "cpu" "atom") | |
157 | (and (eq_attr "type" "negnot") | |
158 | (eq_attr "memory" "!none"))) | |
159 | "atom-simple-either") | |
160 | ||
161 | (define_insn_reservation "atom_imov" 1 | |
162 | (and (eq_attr "cpu" "atom") | |
163 | (and (eq_attr "type" "imov") | |
164 | (eq_attr "memory" "none"))) | |
165 | "atom-simple-either") | |
166 | ||
167 | (define_insn_reservation "atom_imov_mem" 1 | |
168 | (and (eq_attr "cpu" "atom") | |
169 | (and (eq_attr "type" "imov") | |
170 | (eq_attr "memory" "!none"))) | |
171 | "atom-simple-either") | |
172 | ||
173 | ;; 16<-16, 32<-32 | |
174 | (define_insn_reservation "atom_imovx" 1 | |
175 | (and (eq_attr "cpu" "atom") | |
176 | (and (eq_attr "type" "imovx") | |
177 | (and (eq_attr "memory" "none") | |
178 | (ior (and (match_operand:HI 0 "register_operand") | |
179 | (match_operand:HI 1 "general_operand")) | |
180 | (and (match_operand:SI 0 "register_operand") | |
181 | (match_operand:SI 1 "general_operand")))))) | |
182 | "atom-simple-either") | |
183 | ||
184 | ;; 16<-16, 32<-32, mem | |
185 | (define_insn_reservation "atom_imovx_mem" 1 | |
186 | (and (eq_attr "cpu" "atom") | |
187 | (and (eq_attr "type" "imovx") | |
188 | (and (eq_attr "memory" "!none") | |
189 | (ior (and (match_operand:HI 0 "register_operand") | |
190 | (match_operand:HI 1 "general_operand")) | |
191 | (and (match_operand:SI 0 "register_operand") | |
192 | (match_operand:SI 1 "general_operand")))))) | |
193 | "atom-simple-either") | |
194 | ||
195 | ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8 | |
196 | (define_insn_reservation "atom_imovx_2" 1 | |
197 | (and (eq_attr "cpu" "atom") | |
198 | (and (eq_attr "type" "imovx") | |
199 | (and (eq_attr "memory" "none") | |
200 | (ior (match_operand:QI 0 "register_operand") | |
201 | (ior (and (match_operand:SI 0 "register_operand") | |
202 | (not (match_operand:SI 1 "general_operand"))) | |
203 | (match_operand:DI 0 "register_operand")))))) | |
204 | "atom-simple-0") | |
205 | ||
206 | ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem | |
207 | (define_insn_reservation "atom_imovx_2_mem" 1 | |
208 | (and (eq_attr "cpu" "atom") | |
209 | (and (eq_attr "type" "imovx") | |
210 | (and (eq_attr "memory" "!none") | |
211 | (ior (match_operand:QI 0 "register_operand") | |
212 | (ior (and (match_operand:SI 0 "register_operand") | |
213 | (not (match_operand:SI 1 "general_operand"))) | |
214 | (match_operand:DI 0 "register_operand")))))) | |
215 | "atom-simple-0") | |
216 | ||
217 | ;; 16<-8 | |
218 | (define_insn_reservation "atom_imovx_3" 3 | |
219 | (and (eq_attr "cpu" "atom") | |
220 | (and (eq_attr "type" "imovx") | |
221 | (and (match_operand:HI 0 "register_operand") | |
222 | (match_operand:QI 1 "general_operand")))) | |
223 | "atom-complex, atom-all-eu*2") | |
224 | ||
225 | (define_insn_reservation "atom_lea" 1 | |
226 | (and (eq_attr "cpu" "atom") | |
227 | (and (eq_attr "type" "lea") | |
228 | (eq_attr "mode" "!HI"))) | |
229 | "atom-simple-either") | |
230 | ||
231 | ;; lea 16bit address is complex insn | |
232 | (define_insn_reservation "atom_lea_2" 2 | |
233 | (and (eq_attr "cpu" "atom") | |
234 | (and (eq_attr "type" "lea") | |
235 | (eq_attr "mode" "HI"))) | |
236 | "atom-complex, atom-all-eu") | |
237 | ||
238 | (define_insn_reservation "atom_incdec" 1 | |
239 | (and (eq_attr "cpu" "atom") | |
240 | (and (eq_attr "type" "incdec") | |
241 | (eq_attr "memory" "none"))) | |
242 | "atom-simple-either") | |
243 | ||
244 | (define_insn_reservation "atom_incdec_mem" 1 | |
245 | (and (eq_attr "cpu" "atom") | |
246 | (and (eq_attr "type" "incdec") | |
247 | (eq_attr "memory" "!none"))) | |
248 | "atom-simple-either") | |
249 | ||
250 | ;; simple shift instruction use SHIFT eu, none memory | |
251 | (define_insn_reservation "atom_ishift" 1 | |
252 | (and (eq_attr "cpu" "atom") | |
253 | (and (eq_attr "type" "ishift") | |
254 | (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))) | |
255 | "atom-simple-0") | |
256 | ||
257 | ;; simple shift instruction use SHIFT eu, memory | |
258 | (define_insn_reservation "atom_ishift_mem" 1 | |
259 | (and (eq_attr "cpu" "atom") | |
260 | (and (eq_attr "type" "ishift") | |
261 | (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0")))) | |
262 | "atom-simple-0") | |
263 | ||
264 | ;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles | |
265 | (define_insn_reservation "atom_ishift_3" 7 | |
266 | (and (eq_attr "cpu" "atom") | |
267 | (and (eq_attr "type" "ishift") | |
268 | (eq_attr "prefix_0f" "1"))) | |
269 | "atom-complex, atom-all-eu*6") | |
270 | ||
271 | (define_insn_reservation "atom_ishift1" 1 | |
272 | (and (eq_attr "cpu" "atom") | |
273 | (and (eq_attr "type" "ishift1") | |
274 | (eq_attr "memory" "none"))) | |
275 | "atom-simple-0") | |
276 | ||
277 | (define_insn_reservation "atom_ishift1_mem" 1 | |
278 | (and (eq_attr "cpu" "atom") | |
279 | (and (eq_attr "type" "ishift1") | |
280 | (eq_attr "memory" "!none"))) | |
281 | "atom-simple-0") | |
282 | ||
283 | (define_insn_reservation "atom_rotate" 1 | |
284 | (and (eq_attr "cpu" "atom") | |
285 | (and (eq_attr "type" "rotate") | |
286 | (eq_attr "memory" "none"))) | |
287 | "atom-simple-0") | |
288 | ||
289 | (define_insn_reservation "atom_rotate_mem" 1 | |
290 | (and (eq_attr "cpu" "atom") | |
291 | (and (eq_attr "type" "rotate") | |
292 | (eq_attr "memory" "!none"))) | |
293 | "atom-simple-0") | |
294 | ||
295 | (define_insn_reservation "atom_rotate1" 1 | |
296 | (and (eq_attr "cpu" "atom") | |
297 | (and (eq_attr "type" "rotate1") | |
298 | (eq_attr "memory" "none"))) | |
299 | "atom-simple-0") | |
300 | ||
301 | (define_insn_reservation "atom_rotate1_mem" 1 | |
302 | (and (eq_attr "cpu" "atom") | |
303 | (and (eq_attr "type" "rotate1") | |
304 | (eq_attr "memory" "!none"))) | |
305 | "atom-simple-0") | |
306 | ||
307 | (define_insn_reservation "atom_imul" 5 | |
308 | (and (eq_attr "cpu" "atom") | |
309 | (and (eq_attr "type" "imul") | |
310 | (and (eq_attr "memory" "none") (eq_attr "mode" "SI")))) | |
311 | "atom-imul-32") | |
312 | ||
313 | (define_insn_reservation "atom_imul_mem" 5 | |
314 | (and (eq_attr "cpu" "atom") | |
315 | (and (eq_attr "type" "imul") | |
316 | (and (eq_attr "memory" "!none") (eq_attr "mode" "SI")))) | |
317 | "atom-imul-32") | |
318 | ||
319 | ;; latency set to 10 as common 64x64 imul | |
320 | (define_insn_reservation "atom_imul_3" 10 | |
321 | (and (eq_attr "cpu" "atom") | |
322 | (and (eq_attr "type" "imul") | |
323 | (eq_attr "mode" "!SI"))) | |
324 | "atom-complex, atom-all-eu*9") | |
325 | ||
326 | (define_insn_reservation "atom_idiv" 65 | |
327 | (and (eq_attr "cpu" "atom") | |
328 | (eq_attr "type" "idiv")) | |
329 | "atom-complex, atom-all-eu*32, nothing*32") | |
330 | ||
331 | (define_insn_reservation "atom_icmp" 1 | |
332 | (and (eq_attr "cpu" "atom") | |
333 | (and (eq_attr "type" "icmp") | |
334 | (eq_attr "memory" "none"))) | |
335 | "atom-simple-either") | |
336 | ||
337 | (define_insn_reservation "atom_icmp_mem" 1 | |
338 | (and (eq_attr "cpu" "atom") | |
339 | (and (eq_attr "type" "icmp") | |
340 | (eq_attr "memory" "!none"))) | |
341 | "atom-simple-either") | |
342 | ||
343 | (define_insn_reservation "atom_test" 1 | |
344 | (and (eq_attr "cpu" "atom") | |
345 | (and (eq_attr "type" "test") | |
346 | (eq_attr "memory" "none"))) | |
347 | "atom-simple-either") | |
348 | ||
349 | (define_insn_reservation "atom_test_mem" 1 | |
350 | (and (eq_attr "cpu" "atom") | |
351 | (and (eq_attr "type" "test") | |
352 | (eq_attr "memory" "!none"))) | |
353 | "atom-simple-either") | |
354 | ||
355 | (define_insn_reservation "atom_ibr" 1 | |
356 | (and (eq_attr "cpu" "atom") | |
357 | (and (eq_attr "type" "ibr") | |
358 | (eq_attr "memory" "!load"))) | |
359 | "atom-simple-1") | |
360 | ||
361 | ;; complex if jump target is from address | |
362 | (define_insn_reservation "atom_ibr_2" 2 | |
363 | (and (eq_attr "cpu" "atom") | |
364 | (and (eq_attr "type" "ibr") | |
365 | (eq_attr "memory" "load"))) | |
366 | "atom-complex, atom-all-eu") | |
367 | ||
368 | (define_insn_reservation "atom_setcc" 1 | |
369 | (and (eq_attr "cpu" "atom") | |
370 | (and (eq_attr "type" "setcc") | |
371 | (eq_attr "memory" "!store"))) | |
372 | "atom-simple-either") | |
373 | ||
374 | ;; 2 cycles complex if target is in memory | |
375 | (define_insn_reservation "atom_setcc_2" 2 | |
376 | (and (eq_attr "cpu" "atom") | |
377 | (and (eq_attr "type" "setcc") | |
378 | (eq_attr "memory" "store"))) | |
379 | "atom-complex, atom-all-eu") | |
380 | ||
381 | (define_insn_reservation "atom_icmov" 1 | |
382 | (and (eq_attr "cpu" "atom") | |
383 | (and (eq_attr "type" "icmov") | |
384 | (eq_attr "memory" "none"))) | |
385 | "atom-simple-either") | |
386 | ||
387 | (define_insn_reservation "atom_icmov_mem" 1 | |
388 | (and (eq_attr "cpu" "atom") | |
389 | (and (eq_attr "type" "icmov") | |
390 | (eq_attr "memory" "!none"))) | |
391 | "atom-simple-either") | |
392 | ||
393 | ;; UCODE if segreg, ignored | |
394 | (define_insn_reservation "atom_push" 2 | |
395 | (and (eq_attr "cpu" "atom") | |
396 | (eq_attr "type" "push")) | |
397 | "atom-dual-2c") | |
398 | ||
399 | ;; pop r64 is 1 cycle. UCODE if segreg, ignored | |
400 | (define_insn_reservation "atom_pop" 1 | |
401 | (and (eq_attr "cpu" "atom") | |
402 | (and (eq_attr "type" "pop") | |
403 | (eq_attr "mode" "DI"))) | |
404 | "atom-dual-1c") | |
405 | ||
406 | ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored | |
407 | (define_insn_reservation "atom_pop_2" 2 | |
408 | (and (eq_attr "cpu" "atom") | |
409 | (and (eq_attr "type" "pop") | |
410 | (eq_attr "mode" "!DI"))) | |
411 | "atom-dual-2c") | |
412 | ||
413 | ;; UCODE if segreg, ignored | |
414 | (define_insn_reservation "atom_call" 1 | |
415 | (and (eq_attr "cpu" "atom") | |
416 | (eq_attr "type" "call")) | |
417 | "atom-dual-1c") | |
418 | ||
419 | (define_insn_reservation "atom_callv" 1 | |
420 | (and (eq_attr "cpu" "atom") | |
421 | (eq_attr "type" "callv")) | |
422 | "atom-dual-1c") | |
423 | ||
424 | (define_insn_reservation "atom_leave" 3 | |
425 | (and (eq_attr "cpu" "atom") | |
426 | (eq_attr "type" "leave")) | |
427 | "atom-complex, atom-all-eu*2") | |
428 | ||
429 | (define_insn_reservation "atom_str" 3 | |
430 | (and (eq_attr "cpu" "atom") | |
431 | (eq_attr "type" "str")) | |
432 | "atom-complex, atom-all-eu*2") | |
433 | ||
434 | (define_insn_reservation "atom_sselog" 1 | |
435 | (and (eq_attr "cpu" "atom") | |
eb2f2b44 | 436 | (and (eq_attr "type" "sselog,sseshuf") |
b6837b94 JY |
437 | (eq_attr "memory" "none"))) |
438 | "atom-simple-either") | |
439 | ||
440 | (define_insn_reservation "atom_sselog_mem" 1 | |
441 | (and (eq_attr "cpu" "atom") | |
eb2f2b44 | 442 | (and (eq_attr "type" "sselog,sseshuf") |
b6837b94 JY |
443 | (eq_attr "memory" "!none"))) |
444 | "atom-simple-either") | |
445 | ||
446 | (define_insn_reservation "atom_sselog1" 1 | |
447 | (and (eq_attr "cpu" "atom") | |
eb2f2b44 | 448 | (and (eq_attr "type" "sselog1,sseshuf1") |
b6837b94 JY |
449 | (eq_attr "memory" "none"))) |
450 | "atom-simple-0") | |
451 | ||
452 | (define_insn_reservation "atom_sselog1_mem" 1 | |
453 | (and (eq_attr "cpu" "atom") | |
eb2f2b44 | 454 | (and (eq_attr "type" "sselog1,sseshuf1") |
b6837b94 JY |
455 | (eq_attr "memory" "!none"))) |
456 | "atom-simple-0") | |
457 | ||
458 | ;; not pmad, not psad | |
459 | (define_insn_reservation "atom_sseiadd" 1 | |
460 | (and (eq_attr "cpu" "atom") | |
461 | (and (eq_attr "type" "sseiadd") | |
462 | (and (not (match_operand:V2DI 0 "register_operand")) | |
463 | (and (eq_attr "atom_unit" "!simul") | |
464 | (eq_attr "atom_unit" "!complex"))))) | |
465 | "atom-simple-either") | |
466 | ||
467 | ;; pmad, psad and 64 | |
468 | (define_insn_reservation "atom_sseiadd_2" 4 | |
469 | (and (eq_attr "cpu" "atom") | |
470 | (and (eq_attr "type" "sseiadd") | |
471 | (and (not (match_operand:V2DI 0 "register_operand")) | |
472 | (and (eq_attr "atom_unit" "simul" ) | |
473 | (eq_attr "mode" "DI"))))) | |
474 | "atom-fmul-4c") | |
475 | ||
476 | ;; pmad, psad and 128 | |
477 | (define_insn_reservation "atom_sseiadd_3" 5 | |
478 | (and (eq_attr "cpu" "atom") | |
479 | (and (eq_attr "type" "sseiadd") | |
480 | (and (not (match_operand:V2DI 0 "register_operand")) | |
481 | (and (eq_attr "atom_unit" "simul" ) | |
482 | (eq_attr "mode" "TI"))))) | |
483 | "atom-fmul-5c") | |
484 | ||
485 | ;; if paddq(64 bit op), phadd/phsub | |
486 | (define_insn_reservation "atom_sseiadd_4" 6 | |
487 | (and (eq_attr "cpu" "atom") | |
488 | (and (eq_attr "type" "sseiadd") | |
489 | (ior (match_operand:V2DI 0 "register_operand") | |
490 | (eq_attr "atom_unit" "complex")))) | |
491 | "atom-complex, atom-all-eu*5") | |
492 | ||
493 | ;; if immediate op. | |
494 | (define_insn_reservation "atom_sseishft" 1 | |
495 | (and (eq_attr "cpu" "atom") | |
496 | (and (eq_attr "type" "sseishft") | |
497 | (and (eq_attr "atom_unit" "!sishuf") | |
498 | (match_operand 2 "immediate_operand")))) | |
499 | "atom-simple-either") | |
500 | ||
501 | ;; if palignr or psrldq | |
502 | (define_insn_reservation "atom_sseishft_2" 1 | |
503 | (and (eq_attr "cpu" "atom") | |
c1b157a6 L |
504 | (ior (eq_attr "type" "sseishft1") |
505 | (and (eq_attr "type" "sseishft") | |
506 | (and (eq_attr "atom_unit" "sishuf") | |
507 | (match_operand 2 "immediate_operand"))))) | |
b6837b94 JY |
508 | "atom-simple-0") |
509 | ||
510 | ;; if reg/mem op | |
511 | (define_insn_reservation "atom_sseishft_3" 2 | |
512 | (and (eq_attr "cpu" "atom") | |
513 | (and (eq_attr "type" "sseishft") | |
514 | (not (match_operand 2 "immediate_operand")))) | |
515 | "atom-complex, atom-all-eu") | |
516 | ||
517 | (define_insn_reservation "atom_sseimul" 1 | |
518 | (and (eq_attr "cpu" "atom") | |
519 | (eq_attr "type" "sseimul")) | |
520 | "atom-simple-0") | |
521 | ||
522 | ;; rcpss or rsqrtss | |
523 | (define_insn_reservation "atom_sse" 4 | |
524 | (and (eq_attr "cpu" "atom") | |
525 | (and (eq_attr "type" "sse") | |
526 | (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF")))) | |
527 | "atom-fmul-4c") | |
528 | ||
529 | ;; movshdup, movsldup. Suggest to type sseishft | |
530 | (define_insn_reservation "atom_sse_2" 1 | |
531 | (and (eq_attr "cpu" "atom") | |
532 | (and (eq_attr "type" "sse") | |
533 | (eq_attr "atom_sse_attr" "movdup"))) | |
534 | "atom-simple-0") | |
535 | ||
536 | ;; lfence | |
537 | (define_insn_reservation "atom_sse_3" 1 | |
538 | (and (eq_attr "cpu" "atom") | |
539 | (and (eq_attr "type" "sse") | |
540 | (eq_attr "atom_sse_attr" "lfence"))) | |
541 | "atom-simple-either") | |
542 | ||
543 | ;; sfence,clflush,mfence, prefetch | |
544 | (define_insn_reservation "atom_sse_4" 1 | |
545 | (and (eq_attr "cpu" "atom") | |
546 | (and (eq_attr "type" "sse") | |
69e3f332 | 547 | (eq_attr "atom_sse_attr" "fence,prefetch"))) |
b6837b94 JY |
548 | "atom-simple-0") |
549 | ||
550 | ;; rcpps, rsqrtss, sqrt, ldmxcsr | |
551 | (define_insn_reservation "atom_sse_5" 7 | |
552 | (and (eq_attr "cpu" "atom") | |
553 | (and (eq_attr "type" "sse") | |
69e3f332 | 554 | (ior (eq_attr "atom_sse_attr" "sqrt,mxcsr") |
b6837b94 JY |
555 | (and (eq_attr "atom_sse_attr" "rcp") |
556 | (eq_attr "mode" "V4SF"))))) | |
557 | "atom-complex, atom-all-eu*6") | |
558 | ||
559 | ;; xmm->xmm | |
560 | (define_insn_reservation "atom_ssemov" 1 | |
561 | (and (eq_attr "cpu" "atom") | |
562 | (and (eq_attr "type" "ssemov") | |
563 | (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy")))) | |
564 | "atom-simple-either") | |
565 | ||
566 | ;; reg->xmm | |
567 | (define_insn_reservation "atom_ssemov_2" 1 | |
568 | (and (eq_attr "cpu" "atom") | |
569 | (and (eq_attr "type" "ssemov") | |
570 | (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r")))) | |
571 | "atom-simple-0") | |
572 | ||
573 | ;; xmm->reg | |
574 | (define_insn_reservation "atom_ssemov_3" 3 | |
575 | (and (eq_attr "cpu" "atom") | |
576 | (and (eq_attr "type" "ssemov") | |
577 | (and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy")))) | |
578 | "atom-eu-0-3-1") | |
579 | ||
580 | ;; mov mem | |
581 | (define_insn_reservation "atom_ssemov_4" 1 | |
582 | (and (eq_attr "cpu" "atom") | |
583 | (and (eq_attr "type" "ssemov") | |
584 | (and (eq_attr "movu" "0") (eq_attr "memory" "!none")))) | |
585 | "atom-simple-0") | |
586 | ||
587 | ;; movu mem | |
588 | (define_insn_reservation "atom_ssemov_5" 2 | |
589 | (and (eq_attr "cpu" "atom") | |
590 | (and (eq_attr "type" "ssemov") | |
591 | (ior (eq_attr "movu" "1") (eq_attr "memory" "!none")))) | |
592 | "atom-complex, atom-all-eu") | |
593 | ||
594 | ;; no memory simple | |
595 | (define_insn_reservation "atom_sseadd" 5 | |
596 | (and (eq_attr "cpu" "atom") | |
b790dea2 | 597 | (and (eq_attr "type" "sseadd,sseadd1") |
b6837b94 JY |
598 | (and (eq_attr "memory" "none") |
599 | (and (eq_attr "mode" "!V2DF") | |
600 | (eq_attr "atom_unit" "!complex"))))) | |
601 | "atom-fadd-5c") | |
602 | ||
603 | ;; memory simple | |
604 | (define_insn_reservation "atom_sseadd_mem" 5 | |
605 | (and (eq_attr "cpu" "atom") | |
b790dea2 | 606 | (and (eq_attr "type" "sseadd,sseadd1") |
b6837b94 JY |
607 | (and (eq_attr "memory" "!none") |
608 | (and (eq_attr "mode" "!V2DF") | |
609 | (eq_attr "atom_unit" "!complex"))))) | |
610 | "atom-dual-5c") | |
611 | ||
612 | ;; maxps, minps, *pd, hadd, hsub | |
613 | (define_insn_reservation "atom_sseadd_3" 8 | |
614 | (and (eq_attr "cpu" "atom") | |
b790dea2 | 615 | (and (eq_attr "type" "sseadd,sseadd1") |
b6837b94 JY |
616 | (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex")))) |
617 | "atom-complex, atom-all-eu*7") | |
618 | ||
619 | ;; Except dppd/dpps | |
620 | (define_insn_reservation "atom_ssemul" 5 | |
621 | (and (eq_attr "cpu" "atom") | |
622 | (and (eq_attr "type" "ssemul") | |
623 | (eq_attr "mode" "!SF"))) | |
624 | "atom-fmul-5c") | |
625 | ||
626 | ;; Except dppd/dpps, 4 cycle if mulss | |
627 | (define_insn_reservation "atom_ssemul_2" 4 | |
628 | (and (eq_attr "cpu" "atom") | |
629 | (and (eq_attr "type" "ssemul") | |
630 | (eq_attr "mode" "SF"))) | |
631 | "atom-fmul-4c") | |
632 | ||
633 | (define_insn_reservation "atom_ssecmp" 1 | |
634 | (and (eq_attr "cpu" "atom") | |
635 | (eq_attr "type" "ssecmp")) | |
636 | "atom-simple-either") | |
637 | ||
638 | (define_insn_reservation "atom_ssecomi" 10 | |
639 | (and (eq_attr "cpu" "atom") | |
640 | (eq_attr "type" "ssecomi")) | |
641 | "atom-complex, atom-all-eu*9") | |
642 | ||
643 | ;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi | |
644 | (define_insn_reservation "atom_ssecvt" 5 | |
645 | (and (eq_attr "cpu" "atom") | |
646 | (and (eq_attr "type" "ssecvt") | |
647 | (ior (and (match_operand:V2SI 0 "register_operand") | |
648 | (match_operand:V4SF 1 "register_operand")) | |
649 | (and (match_operand:V4SF 0 "register_operand") | |
650 | (match_operand:V2SI 1 "register_operand"))))) | |
651 | "atom-fadd-5c") | |
652 | ||
653 | ;; memory and cvtpi2ps, cvtps2pi, cvttps2pi | |
654 | (define_insn_reservation "atom_ssecvt_2" 5 | |
655 | (and (eq_attr "cpu" "atom") | |
656 | (and (eq_attr "type" "ssecvt") | |
657 | (ior (and (match_operand:V2SI 0 "register_operand") | |
658 | (match_operand:V4SF 1 "memory_operand")) | |
659 | (and (match_operand:V4SF 0 "register_operand") | |
660 | (match_operand:V2SI 1 "memory_operand"))))) | |
661 | "atom-dual-5c") | |
662 | ||
663 | ;; otherwise. 7 cycles average for cvtss2sd | |
664 | (define_insn_reservation "atom_ssecvt_3" 7 | |
665 | (and (eq_attr "cpu" "atom") | |
666 | (and (eq_attr "type" "ssecvt") | |
667 | (not (ior (and (match_operand:V2SI 0 "register_operand") | |
668 | (match_operand:V4SF 1 "nonimmediate_operand")) | |
669 | (and (match_operand:V4SF 0 "register_operand") | |
670 | (match_operand:V2SI 1 "nonimmediate_operand")))))) | |
671 | "atom-complex, atom-all-eu*6") | |
672 | ||
673 | ;; memory and cvtsi2sd | |
674 | (define_insn_reservation "atom_sseicvt" 5 | |
675 | (and (eq_attr "cpu" "atom") | |
676 | (and (eq_attr "type" "sseicvt") | |
677 | (and (match_operand:V2DF 0 "register_operand") | |
678 | (match_operand:SI 1 "memory_operand")))) | |
679 | "atom-dual-5c") | |
680 | ||
681 | ;; otherwise. 8 cycles average for cvtsd2si | |
682 | (define_insn_reservation "atom_sseicvt_2" 8 | |
683 | (and (eq_attr "cpu" "atom") | |
684 | (and (eq_attr "type" "sseicvt") | |
685 | (not (and (match_operand:V2DF 0 "register_operand") | |
686 | (match_operand:SI 1 "memory_operand"))))) | |
687 | "atom-complex, atom-all-eu*7") | |
688 | ||
689 | (define_insn_reservation "atom_ssediv" 62 | |
690 | (and (eq_attr "cpu" "atom") | |
691 | (eq_attr "type" "ssediv")) | |
692 | "atom-complex, atom-all-eu*12, nothing*49") | |
693 | ||
694 | ;; simple for fmov | |
695 | (define_insn_reservation "atom_fmov" 1 | |
696 | (and (eq_attr "cpu" "atom") | |
697 | (and (eq_attr "type" "fmov") | |
698 | (eq_attr "memory" "none"))) | |
699 | "atom-simple-either") | |
700 | ||
701 | ;; simple for fmov | |
702 | (define_insn_reservation "atom_fmov_mem" 1 | |
703 | (and (eq_attr "cpu" "atom") | |
704 | (and (eq_attr "type" "fmov") | |
705 | (eq_attr "memory" "!none"))) | |
706 | "atom-simple-either") | |
707 | ||
708 | ;; Define bypass here | |
709 | ||
710 | ;; There will be no stall from lea to non-mem EX insns | |
711 | (define_bypass 0 "atom_lea" | |
712 | "atom_alu_carry, | |
713 | atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
714 | atom_incdec, atom_setcc, atom_icmov, atom_pop") | |
715 | ||
716 | (define_bypass 0 "atom_lea" | |
717 | "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
718 | atom_imovx_mem, atom_imovx_2_mem, | |
719 | atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
720 | "!ix86_agi_dependent") | |
721 | ||
722 | ;; There will be 3 cycles stall from EX insns to AGAN insns LEA | |
723 | (define_bypass 4 "atom_alu_carry, | |
724 | atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
725 | atom_incdec,atom_ishift,atom_ishift1,atom_rotate, | |
726 | atom_rotate1, atom_setcc, atom_icmov, atom_pop, | |
727 | atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
728 | atom_imovx_mem, atom_imovx_2_mem, | |
729 | atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
730 | "atom_lea") | |
731 | ||
732 | ;; There will be 3 cycles stall from EX insns to insns need addr calculation | |
733 | (define_bypass 4 "atom_alu_carry, | |
734 | atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
735 | atom_incdec,atom_ishift,atom_ishift1,atom_rotate, | |
736 | atom_rotate1, atom_setcc, atom_icmov, atom_pop, | |
737 | atom_imovx_mem, atom_imovx_2_mem, | |
738 | atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
739 | atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
740 | "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
741 | atom_negnot_mem, atom_imov_mem, atom_incdec_mem, | |
742 | atom_imovx_mem, atom_imovx_2_mem, | |
743 | atom_imul_mem, atom_icmp_mem, | |
744 | atom_test_mem, atom_icmov_mem, atom_sselog_mem, | |
745 | atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem, | |
746 | atom_ishift_mem, atom_ishift1_mem, | |
747 | atom_rotate_mem, atom_rotate1_mem" | |
748 | "ix86_agi_dependent") | |
749 | ||
750 | ;; Stall from imul to lea is 8 cycles. | |
751 | (define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea") | |
752 | ||
753 | ;; Stall from imul to memory address is 8 cycles. | |
754 | (define_bypass 9 "atom_imul, atom_imul_mem" | |
755 | "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
756 | atom_negnot_mem, atom_imov_mem, atom_incdec_mem, | |
757 | atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem, | |
758 | atom_rotate1_mem, atom_imul_mem, atom_icmp_mem, | |
759 | atom_test_mem, atom_icmov_mem, atom_sselog_mem, | |
760 | atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem" | |
761 | "ix86_agi_dependent") | |
762 | ||
763 | ;; There will be 0 cycle stall from cmp/test to jcc | |
764 | ||
765 | ;; There will be 1 cycle stall from flag producer to cmov and adc/sbb | |
766 | (define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry, | |
767 | atom_alu1, atom_negnot, atom_incdec, atom_ishift, | |
768 | atom_ishift1, atom_rotate, atom_rotate1" | |
769 | "atom_icmov, atom_alu_carry") | |
6ff078d4 JY |
770 | |
771 | ;; lea to shift count stall is 2 cycles | |
772 | (define_bypass 3 "atom_lea" | |
773 | "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1, | |
774 | atom_ishift_mem, atom_ishift1_mem, | |
775 | atom_rotate_mem, atom_rotate1_mem" | |
776 | "ix86_dep_by_shift_count") | |
777 | ||
778 | ;; lea to shift source stall is 1 cycle | |
779 | (define_bypass 2 "atom_lea" | |
780 | "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1" | |
781 | "!ix86_dep_by_shift_count") | |
782 | ||
783 | ;; non-lea to shift count stall is 1 cycle | |
784 | (define_bypass 2 "atom_alu_carry, | |
785 | atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
786 | atom_incdec,atom_ishift,atom_ishift1,atom_rotate, | |
787 | atom_rotate1, atom_setcc, atom_icmov, atom_pop, | |
788 | atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
789 | atom_imovx_mem, atom_imovx_2_mem, | |
790 | atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
791 | "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1, | |
792 | atom_ishift_mem, atom_ishift1_mem, | |
793 | atom_rotate_mem, atom_rotate1_mem" | |
794 | "ix86_dep_by_shift_count") |