projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| a5381466 | 1 | /* Definitions of target machine GNU compiler. IA-64 version. |
| 99dee823 | 2 | Copyright (C) 2002-2021 Free Software Foundation, Inc. |
| a5381466 ZW |
3 | Contributed by James E. Wilson <wilson@cygnus.com> and |
| 4 | David Mosberger <davidm@hpl.hp.com>. | |
| 5 | ||
| 3bed2930 | 6 | This file is part of GCC. |
| a5381466 | 7 | |
| 3bed2930 | 8 | GCC is free software; you can redistribute it and/or modify |
| a5381466 | 9 | it under the terms of the GNU General Public License as published by |
| 2f83c7d6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
| a5381466 ZW |
11 | any later version. |
| 12 | ||
| 3bed2930 | 13 | GCC is distributed in the hope that it will be useful, |
| a5381466 ZW |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | GNU General Public License for more details. | |
| 17 | ||
| 18 | You should have received a copy of the GNU General Public License | |
| 2f83c7d6 NC |
19 | along with GCC; see the file COPYING3. If not see |
| 20 | <http://www.gnu.org/licenses/>. */ | |
| a5381466 | 21 | |
| 02befdf4 ZW |
22 | /* IA64 requires both XF and TF modes. |
| 23 | XFmode is __float80 is IEEE extended; TFmode is __float128 | |
| 968a7562 | 24 | is IEEE quad. Both these modes occupy 16 bytes, but XFmode |
| 4de67c26 JM |
25 | only has 80 significant bits. RFmode is __fpreg is IA64 internal |
| 26 | register format with 82 significant bits but otherwise handled like | |
| 27 | XFmode. */ | |
| 02befdf4 | 28 | |
| 968a7562 | 29 | FRACTIONAL_FLOAT_MODE (XF, 80, 16, ieee_extended_intel_128_format); |
| 4de67c26 | 30 | FRACTIONAL_FLOAT_MODE (RF, 82, 16, ieee_extended_intel_128_format); |
| 02befdf4 ZW |
31 | FLOAT_MODE (TF, 16, ieee_quad_format); |
| 32 | ||
| 33 | /* The above produces: | |
| 34 | ||
| 35 | mode ILP32 size/align LP64 size/align | |
| 968a7562 | 36 | XF 16/16 16/16 |
| 02befdf4 ZW |
37 | TF 16/16 16/16 |
| 38 | ||
| 39 | psABI expectations: | |
| 40 | ||
| 41 | mode ILP32 size/align LP64 size/align | |
| 968a7562 | 42 | XF 12/4 - |
| 02befdf4 ZW |
43 | TF - - |
| 44 | ||
| 45 | HPUX expectations: | |
| 46 | ||
| 47 | mode ILP32 size/align LP64 size/align | |
| 968a7562 | 48 | XF - - |
| 02befdf4 ZW |
49 | TF 16/8 - |
| 50 | ||
| 51 | We fix this up here. */ | |
| 52 | ||
| 968a7562 ZW |
53 | ADJUST_FLOAT_FORMAT (XF, (TARGET_ILP32 && !TARGET_HPUX) |
| 54 | ? &ieee_extended_intel_96_format | |
| 55 | : &ieee_extended_intel_128_format); | |
| 02befdf4 ZW |
56 | ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16); |
| 57 | ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16); | |
| 58 | ||
| 4de67c26 JM |
59 | ADJUST_FLOAT_FORMAT (RF, (TARGET_ILP32 && !TARGET_HPUX) |
| 60 | ? &ieee_extended_intel_96_format | |
| 61 | : &ieee_extended_intel_128_format); | |
| 62 | ADJUST_BYTESIZE (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16); | |
| 63 | ADJUST_ALIGNMENT (RF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16); | |
| 64 | ||
| 02befdf4 | 65 | ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16); |
| 94134f42 ZW |
66 | |
| 67 | /* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */ | |
| 68 | INT_MODE (OI, 32); | |
| 69 | ||
| a5381466 ZW |
70 | /* Add any extra modes needed to represent the condition code. |
| 71 | ||
| 72 | CCImode is used to mark a single predicate register instead | |
| 73 | of a register pair. This is currently only used in reg_raw_mode | |
| 74 | so that flow doesn't do something stupid. */ | |
| 75 | ||
| 94134f42 | 76 | CC_MODE (CCI); |
| f61134e8 RH |
77 | |
| 78 | /* Vector modes. */ | |
| 79 | VECTOR_MODES (INT, 4); /* V4QI V2HI */ | |
| 80 | VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ | |
| 81 | VECTOR_MODE (INT, QI, 16); | |
| 82 | VECTOR_MODE (INT, HI, 8); | |
| 83 | VECTOR_MODE (INT, SI, 4); | |
| 84 | VECTOR_MODE (FLOAT, SF, 2); | |
| b4e3537b RH |
85 | VECTOR_MODE (FLOAT, SF, 4); |
| 86 |