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Merge tree-ssa-20020619-branch into mainline.
[thirdparty/gcc.git] / gcc / config / ip2k / ip2k.h
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77094862 1/* Definitions of target machine for GCC,
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DC		 2 For Ubicom IP2022 Communications Controller
3
49ca372c 4 Copyright (C) 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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DC		 5 Contributed by Red Hat, Inc and Ubicom, Inc.
6
77094862 7This file is part of GCC.
e3223ea2 8
77094862 9GCC is free software; you can redistribute it and/or modify
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DC		 10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
77094862 14GCC is distributed in the hope that it will be useful,
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DC		 15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
77094862 20along with GCC; see the file COPYING. If not, write to
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DC		 21the Free Software Foundation, 59 Temple Place - Suite 330,
22Boston, MA 02111-1307, USA. */
23
24\f
9cd598aa 25#undef ASM_SPEC /* We have a GAS assembler. */
e3223ea2 26
cc956ba2
NB		 27#define TARGET_CPU_CPP_BUILTINS() \
28 do \
29 { \
30 builtin_define_std ("IP2K"); \
31 builtin_define ("_DOUBLE_IS_32BITS"); \
32 builtin_define ("_BUFSIZ=512"); \
33 builtin_define ("__FILENAME_MAX__=128"); \
34 } \
35 while (0)
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DC		 36
37/* This declaration should be present. */
38extern int target_flags;
39
e3223ea2 40#define TARGET_SWITCHES {{"",0, NULL}}
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DC		 41
42#define TARGET_VERSION fprintf (stderr, " (ip2k, GNU assembler syntax)")
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DC		 43
44/* Caller-saves is not a win for the IP2K. Pretty much anywhere that
45 a register is permitted allows SP-relative addresses too.
46
47 This machine doesn't have PIC addressing modes, so disable that also. */
48
49#define OVERRIDE_OPTIONS \
50 do { \
51 flag_caller_saves = 0; \
52 flag_pic = 0; \
53 } while (0)
54
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DC		 55/* Put each function in its own section so that PAGE-instruction
56 relaxation can do its best. */
57#define OPTIMIZATION_OPTIONS(LEVEL, SIZEFLAG) \
58 do { \
59 if ((LEVEL) || (SIZEFLAG)) \
60 flag_function_sections = 1; \
61 } while (0)
62
e3223ea2 63#define BITS_BIG_ENDIAN 0
e3223ea2 64#define BYTES_BIG_ENDIAN 1
e3223ea2 65#define WORDS_BIG_ENDIAN 1
e3223ea2 66#define BITS_PER_WORD 8
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DC		 67#define UNITS_PER_WORD (BITS_PER_WORD / BITS_PER_UNIT)
68
69/* Width in bits of a pointer.
70 See also the macro `Pmode' defined below. */
71#define POINTER_SIZE 16
72
73/* Maximum sized of reasonable data type DImode or Dfmode ... */
74#define MAX_FIXED_MODE_SIZE 64
75
e3223ea2 76#define PARM_BOUNDARY 8
e3223ea2 77#define FUNCTION_BOUNDARY 16
e3223ea2 78#define EMPTY_FIELD_BOUNDARY 8
e3223ea2
DC		 79#define BIGGEST_ALIGNMENT 8
80
81#define STRICT_ALIGNMENT 0
82
83#define PCC_BITFIELD_TYPE_MATTERS 1
84
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DC		 85#undef INT_TYPE_SIZE
86#define INT_TYPE_SIZE 16
87
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DC		 88#undef SHORT_TYPE_SIZE
89#define SHORT_TYPE_SIZE 16
90
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DC		 91#undef LONG_TYPE_SIZE
92#define LONG_TYPE_SIZE 32
e3223ea2 93
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DC		 94#undef LONG_LONG_TYPE_SIZE
95#define LONG_LONG_TYPE_SIZE 64
96
97#undef CHAR_TYPE_SIZE
98#define CHAR_TYPE_SIZE 8
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DC		 99
100#undef FLOAT_TYPE_SIZE
101#define FLOAT_TYPE_SIZE 32
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DC		 102
103#undef DOUBLE_TYPE_SIZE
104#define DOUBLE_TYPE_SIZE 32
e3223ea2 105
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DC		 106#undef LONG_DOUBLE_TYPE_SIZE
107#define LONG_DOUBLE_TYPE_SIZE 32
108
109#define DEFAULT_SIGNED_CHAR 1
e3223ea2 110
e3223ea2 111#define SIZE_TYPE "unsigned int"
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DC		 112
113#define PTRDIFF_TYPE "int"
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DC		 114
115#undef WCHAR_TYPE
116#define WCHAR_TYPE "int"
117#undef WCHAR_TYPE_SIZE
118#define WCHAR_TYPE_SIZE 16
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DC		 119
120#define HARD_REG_SIZE (UNITS_PER_WORD)
121/* Standard register usage.
122
123 for the IP2K, we are going to have a LOT of registers, but only some of them
124 are named. */
125
126#define FIRST_PSEUDO_REGISTER (0x104) /* Skip over physical regs, VFP, AP. */
127
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DC		 128#define REG_IP 0x4
129#define REG_IPH REG_IP
130#define REG_IPL 0x5
131
132#define REG_SP 0x6
133#define REG_SPH REG_SP
134#define REG_SPL 0x7
135
136#define REG_PCH 0x8
137#define REG_PCL 0x9
138
139#define REG_W 0xa
140#define REG_STATUS 0xb
141
142#define REG_DP 0xc
143#define REG_DPH REG_DP
144#define REG_DPL 0xd
145
146#define REG_MULH 0xf
147
148#define REG_CALLH 0x7e /* Call-stack readout. */
149#define REG_CALLL 0x7f
150
151
152#define REG_RESULT 0x80 /* Result register (upto 8 bytes). */
153#define REG_FP 0xfd /* 2 bytes for FRAME chain */
154
155#define REG_ZERO 0xff /* Initialized to zero by runtime. */
156
157#define REG_VFP 0x100 /* Virtual frame pointer. */
158#define REG_AP 0x102 /* Virtual arg pointer. */
159
160/* Status register bits. */
161#define Z_FLAG 0x2
162#define DC_FLAG 0x1
163#define C_FLAG 0x0
164
165#define FIXED_REGISTERS {\
1661,1,1,1,0,0,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r0.. r31*/\
1671,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r32.. r63*/\
1681,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r64.. r95*/\
1691,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r96..r127*/\
1700,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,/*r128..r159*/\
1711,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r160..r191*/\
1721,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r192..r223*/\
1731,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r224..r255*/\
1741,1,1,1}
175
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DC		 176#define CALL_USED_REGISTERS { \
1771,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r0.. r31*/\
1781,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r32.. r63*/\
1791,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r64.. r95*/\
1801,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/* r96..r127*/\
1811,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r128..r159*/\
1821,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r160..r191*/\
1831,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r192..r223*/\
1841,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,/*r224..r255*/\
1851,1,1,1}
186
e3223ea2 187#define NON_SAVING_SETJMP 0
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DC		 188
189#define REG_ALLOC_ORDER { \
190 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f, \
191 0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, \
192 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f, \
193 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
194 0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, \
195 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf, \
196 0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, \
197 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf, \
198 0xc0,0xc1,0xc2,0xc3,0xc4,0xc5,0xc6,0xc7, \
199 0xc8,0xc9,0xca,0xcb,0xcc,0xcd,0xce,0xcf, \
200 0xd0,0xd1,0xd2,0xd3,0xd4,0xd5,0xd6,0xd7, \
201 0xd8,0xd9,0xda,0xdb,0xdc,0xdd,0xde,0xdf, \
202 0xe0,0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7, \
203 0xe8,0xe9,0xea,0xeb,0xec,0xed,0xee,0xef, \
204 0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, \
205 0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff, \
206 0x00,0x01,0x02,0x03,0x0c,0x0d,0x06,0x07, \
207 0x08,0x09,0x0a,0x0b,0x04,0x05,0x0e,0x0f, \
208 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, \
209 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f, \
210 0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, \
211 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f, \
212 0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, \
213 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, \
214 0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, \
215 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f, \
216 0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, \
217 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f, \
218 0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, \
219 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f, \
220 0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, \
221 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f, \
222 0x100,0x101,0x102,0x103}
223
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DC		 224
225#define ORDER_REGS_FOR_LOCAL_ALLOC ip2k_init_local_alloc (reg_alloc_order)
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DC		 226
227/* Are we allowed to rename registers? For some reason, regrename was
228 changing DP to IP (when it appeared in addresses like (plus:HI
229 (reg: DP) (const_int 37)) - and that's bad because IP doesn't
230 permit offsets! */
231
232#define HARD_REGNO_RENAME_OK(REG, NREG) \
233 (((REG) == REG_DPH) ? 0 \
234 : ((REG) == REG_IPH) ? ((NREG) == REG_DPH) \
235 : (((NREG) == REG_IPL) || ((NREG) == REG_DPL)) ? 0 : 1)
236
237#define HARD_REGNO_NREGS(REGNO, MODE) \
238 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
239
e3223ea2 240#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
e3223ea2
DC		 241
242#define MODES_TIEABLE_P(MODE1, MODE2) \
243 (((MODE1) == QImode && (MODE2) == HImode) \
244 || ((MODE2) == QImode && (MODE1) == HImode))
245/* We originally had this as follows - this isn't a win on the IP2k
246 though as registers just get in our way!
247
248 #define MODES_TIEABLE_P(MODE1, MODE2) \
249 (((MODE1) > HImode && (MODE2) == HImode)
250 || ((MODE1) == HImode && (MODE2) > HImode)) */
251
e3223ea2
DC		 252enum reg_class {
253 NO_REGS,
254 DPH_REGS,
255 DPL_REGS,
256 DP_REGS,
257 SP_REGS,
258 IPH_REGS,
259 IPL_REGS,
260 IP_REGS,
261 DP_SP_REGS,
262 PTR_REGS,
263 NONPTR_REGS,
264 NONSP_REGS,
265 GENERAL_REGS,
266 ALL_REGS = GENERAL_REGS,
267 LIM_REG_CLASSES
268};
269
e3223ea2 270#define N_REG_CLASSES (int)LIM_REG_CLASSES
e3223ea2
DC		 271
272#define REG_CLASS_NAMES { \
273 "NO_REGS", \
274 "DPH_REGS", \
275 "DPL_REGS", \
276 "DP_REGS", \
277 "SP_REGS", \
278 "IPH_REGS", \
279 "IPL_REGS", \
280 "IP_REGS", \
281 "DP_SP_REGS", \
282 "PTR_REGS", \
283 "NONPTR_REGS", \
284 "NONSP_REGS", \
285 "GENERAL_REGS" \
286 }
e3223ea2
DC		 287
288
289#define REG_CLASS_CONTENTS { \
290{0x00000000, 0, 0, 0, 0, 0, 0, 0, 0}, /* NO_REGS */ \
291{0x00001000, 0, 0, 0, 0, 0, 0, 0, 0}, /* DPH_REGS */ \
292{0x00002000, 0, 0, 0, 0, 0, 0, 0, 0}, /* DPL_REGS */ \
293{0x00003000, 0, 0, 0, 0, 0, 0, 0, 0}, /* DP_REGS */ \
294{0x000000c0, 0, 0, 0, 0, 0, 0, 0, 0}, /* SP_REGS */ \
295{0x00000010, 0, 0, 0, 0, 0, 0, 0, 0}, /* IPH_REGS */ \
296{0x00000020, 0, 0, 0, 0, 0, 0, 0, 0}, /* IPL_REGS */ \
297{0x00000030, 0, 0, 0, 0, 0, 0, 0, 0}, /* IP_REGS */ \
298{0x000030c0, 0, 0, 0, 0, 0, 0, 0, 0}, /* DP_SP_REGS */ \
299{0x000030f0, 0, 0, 0, 0, 0, 0, 0, 0}, /* PTR_REGS */ \
300{0xffffcf0f,-1,-1,-1,-1,-1,-1,-1, 0}, /* NONPTR_REGS */ \
301{0xffffff3f,-1,-1,-1,-1,-1,-1,-1, 0}, /* NONSP_REGS */ \
302{0xffffffff,-1,-1,-1,-1,-1,-1,-1,15} /* GENERAL_REGS */ \
303}
304
e3223ea2
DC		 305#define REGNO_REG_CLASS(R) \
306 ( (R) == REG_IPH ? IPH_REGS \
307 : (R) == REG_IPL ? IPL_REGS \
308 : (R) == REG_DPH ? DPH_REGS \
309 : (R) == REG_DPL ? DPL_REGS \
310 : (R) == REG_SPH ? SP_REGS \
311 : (R) == REG_SPL ? SP_REGS \
312 : NONPTR_REGS)
313
e3223ea2 314#define MODE_BASE_REG_CLASS(MODE) ((MODE) == QImode ? PTR_REGS : DP_SP_REGS)
e3223ea2
DC		 315
316#define BASE_REG_CLASS PTR_REGS
e3223ea2
DC		 317
318#define INDEX_REG_CLASS NO_REGS
e3223ea2
DC		 319
320#define REG_CLASS_FROM_LETTER(C) \
321 ( (C) == 'j' ? IPH_REGS \
322 : (C) == 'k' ? IPL_REGS \
323 : (C) == 'f' ? IP_REGS \
324 : (C) == 'y' ? DPH_REGS \
325 : (C) == 'z' ? DPL_REGS \
326 : (C) == 'b' ? DP_REGS \
327 : (C) == 'u' ? NONSP_REGS \
328 : (C) == 'q' ? SP_REGS \
329 : (C) == 'c' ? DP_SP_REGS \
330 : (C) == 'a' ? PTR_REGS \
331 : (C) == 'd' ? NONPTR_REGS \
332 : NO_REGS)
333
e3223ea2
DC		 334#define REGNO_OK_FOR_BASE_P(R) \
335 ((R) == REG_DP || (R) == REG_IP || (R) == REG_SP)
e3223ea2
DC		 336
337#define REGNO_MODE_OK_FOR_BASE_P(R,M) \
338 ((R) == REG_DP || (R) == REG_SP \
339 || ((R) == REG_IP && GET_MODE_SIZE (M) <= 1))
e3223ea2
DC		 340
341#define REGNO_OK_FOR_INDEX_P(NUM) 0
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DC		 342
343#define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
e3223ea2
DC		 344
345#define SMALL_REGISTER_CLASSES 1
e3223ea2
DC		 346
347#define CLASS_LIKELY_SPILLED_P(CLASS) class_likely_spilled_p(CLASS)
e3223ea2
DC		 348
349#define CLASS_MAX_NREGS(CLASS, MODE) GET_MODE_SIZE (MODE)
e3223ea2
DC		 350
351#define CONST_OK_FOR_LETTER_P(VALUE, C) \
352 ((C) == 'I' ? (VALUE) >= -255 && (VALUE) <= -1 : \
353 (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 7 : \
354 (C) == 'K' ? (VALUE) >= 0 && (VALUE) <= 127 : \
355 (C) == 'L' ? (VALUE) > 0 && (VALUE) < 128: \
356 (C) == 'M' ? (VALUE) == -1: \
357 (C) == 'N' ? (VALUE) == 1: \
358 (C) == 'O' ? (VALUE) == 0: \
359 (C) == 'P' ? (VALUE) >= 0 && (VALUE) <= 255: \
360 0)
361
e3223ea2
DC		 362#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
363
e3223ea2
DC		 364#define EXTRA_CONSTRAINT(X, C) ip2k_extra_constraint (X, C)
365
e3223ea2
DC		 366/* This is an undocumented variable which describes
367 how GCC will pop a data. */
368#define STACK_POP_CODE PRE_INC
369
370#define STACK_PUSH_CODE POST_DEC
e3223ea2
DC		 371
372#define STACK_CHECK_BUILTIN 1
373/* Prologue code will do stack checking as necessary. */
374
375#define STARTING_FRAME_OFFSET (0)
e3223ea2
DC		 376
377#define FRAME_GROWS_DOWNWARD 1
378#define STACK_GROWS_DOWNWARD 1
379
380/* On IP2K arg pointer is virtual and resolves to either SP or FP
381 after we've resolved what registers are saved (fp chain, return
382 pc, etc. */
383
384#define FIRST_PARM_OFFSET(FUNDECL) 0
e3223ea2
DC		 385
386#define STACK_POINTER_OFFSET 1
387/* IP2K stack is post-decremented, so 0(sp) is address of open space
388 and 1(sp) is offset to the location avobe the forst location at which
389 outgoing arguments are placed. */
390
391#define STACK_BOUNDARY 8
e3223ea2
DC		 392
393#define STACK_POINTER_REGNUM REG_SP
e3223ea2
DC		 394
395#define FRAME_POINTER_REGNUM REG_VFP
e3223ea2
DC		 396#define HARD_FRAME_POINTER_REGNUM REG_FP
397
398#define ARG_POINTER_REGNUM REG_AP
e3223ea2
DC		 399
400/* We don't really want to support nested functions. But we'll crash
401 in various testsuite tests if we don't at least define the register
402 to contain the static chain. The return value register is about as
403 bad a place as any for this. */
404
405#define STATIC_CHAIN_REGNUM REG_RESULT
e3223ea2
DC		 406
407#define FRAME_POINTER_REQUIRED (!flag_omit_frame_pointer)
e3223ea2
DC		 408
409#define ELIMINABLE_REGS { \
410 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
411 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
412 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
413 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
414 {HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
415}
e3223ea2
DC		 416
417#define CAN_ELIMINATE(FROM, TO) \
418 ((FROM) == HARD_FRAME_POINTER_REGNUM \
419 ? (flag_omit_frame_pointer && !frame_pointer_needed) : 1)
420/* Don't eliminate FP unless we EXPLICITLY_ASKED */
421
e3223ea2
DC		 422#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
423 ((OFFSET) = ip2k_init_elim_offset ((FROM), (TO)))
424
e3223ea2
DC		 425#define RETURN_ADDR_RTX(COUNT, X) \
426 (((COUNT) == 0) ? gen_rtx_REG (HImode, REG_CALLH) : NULL_RTX)
e3223ea2
DC		 427
428#define PUSH_ROUNDING(NPUSHED) (NPUSHED)
e3223ea2
DC		 429
430#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \
431 ip2k_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE))
e3223ea2
DC		 432
433#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
e3223ea2
DC		 434
435#define CUMULATIVE_ARGS int
436
0f6937fe 437#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
e3223ea2
DC		 438 ((CUM) = 0)
439
e3223ea2
DC		 440#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)
441
442/* All arguments are passed on stack - do nothing here. */
443
e3223ea2 444#define FUNCTION_ARG_REGNO_P(R) 0
e3223ea2
DC		 445
446#define FUNCTION_VALUE(VALTYPE, FUNC) \
447 ((TYPE_MODE (VALTYPE) == QImode) \
448 ? gen_rtx_REG (TYPE_MODE (VALTYPE), REG_RESULT + 1) \
449 : gen_rtx_REG (TYPE_MODE (VALTYPE), REG_RESULT))
450
451/* Because functions returning 'char' actually widen to 'int', we have to
452 use $81 as the return location if we think we only have a 'char'. */
453
e3223ea2 454#define LIBCALL_VALUE(MODE) gen_rtx_REG ((MODE), REG_RESULT)
e3223ea2
DC		 455
456#define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_RESULT)
e3223ea2 457
e3223ea2
DC		 458/* Indicate that large structures are passed by reference. */
459#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) 0
460
e3223ea2 461#define DEFAULT_PCC_STRUCT_RETURN 0
e3223ea2 462
e3223ea2 463#define EPILOGUE_USES(REGNO) 0
e3223ea2 464
e3223ea2
DC		 465
466/* Hmmm. We don't actually like constants as addresses - they always need
467 to be loaded to a register, except for function calls which take an
468 address by immediate value. But changing this to zero had negative
469 effects, causing the compiler to get very confused.... */
470
471#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
472
e3223ea2 473#define MAX_REGS_PER_ADDRESS 1
e3223ea2
DC		 474
475#ifdef REG_OK_STRICT
476# define GO_IF_LEGITIMATE_ADDRESS(MODE, OPERAND, ADDR) \
477{ \
478 if (legitimate_address_p ((MODE), (OPERAND), 1)) \
479 goto ADDR; \
480}
481#else
482# define GO_IF_LEGITIMATE_ADDRESS(MODE, OPERAND, ADDR) \
483{ \
484 if (legitimate_address_p ((MODE), (OPERAND), 0)) \
485 goto ADDR; \
486}
487#endif
e3223ea2
DC		 488
489#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
490
491#define REG_OK_FOR_BASE_NOSTRICT_P(X) \
492 (REGNO (X) >= FIRST_PSEUDO_REGISTER \
493 || (REGNO (X) == REG_FP) \
494 || (REGNO (X) == REG_VFP) \
495 || (REGNO (X) == REG_AP) \
496 || REG_OK_FOR_BASE_STRICT_P(X))
497
498#ifdef REG_OK_STRICT
499# define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X)
500#else
501# define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NOSTRICT_P (X)
502#endif
503
504#define REG_OK_FOR_INDEX_P(X) 0
e3223ea2
DC		 505
506#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
507do { rtx orig_x = (X); \
508 (X) = legitimize_address ((X), (OLDX), (MODE), 0); \
509 if ((X) != orig_x && memory_address_p ((MODE), (X))) \
510 goto WIN; \
511} while (0)
512
513/* Is X a legitimate register to reload, or is it a pseudo stack-temp
514 that is problematic for push_reload() ? */
515
516#define LRA_REG(X) \
517 (! (reg_equiv_memory_loc[REGNO (X)] \
518 && (reg_equiv_address[REGNO (X)] \
519 || num_not_at_initial_offset)))
520
521/* Given a register X that failed the LRA_REG test, replace X
522 by its memory equivalent, find the reloads needed for THAT memory
523 location and substitute that back for the higher-level reload
524 that we're conducting... */
525
526/* WARNING: we reference 'ind_levels' and 'insn' which are local variables
527 in find_reloads_address (), where the LEGITIMIZE_RELOAD_ADDRESS macro
528 expands. */
529
530#define FRA_REG(X,MODE,OPNUM,TYPE) \
531do { \
532 rtx tem = make_memloc ((X), REGNO (X)); \
533 \
534 if (! strict_memory_address_p (GET_MODE (tem), XEXP (tem, 0))) \
535 { \
536 /* Note that we're doing address in address - cf. ADDR_TYPE */ \
537 find_reloads_address (GET_MODE (tem), &tem, XEXP (tem, 0), \
538 &XEXP (tem, 0), (OPNUM), \
539 ADDR_TYPE (TYPE), ind_levels, insn); \
540 } \
541 (X) = tem; \
542} while (0)
543
544
545/* For the IP2K, we want to be clever about picking IP vs DP for a
546 base pointer since IP only directly supports a zero displacement.
547 (Note that we have modified all the HI patterns to correctly handle
548 IP references by manipulating iph:ipl as we fetch the pieces). */
549#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND,WIN) \
550{ \
551 if (GET_CODE (X) == PLUS \
552 && REG_P (XEXP (X, 0)) \
553 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
554 { \
555 int disp = INTVAL (XEXP (X, 1)); \
556 int fit = (disp >= 0 && disp <= (127 - 2 * GET_MODE_SIZE (MODE))); \
557 rtx reg = XEXP (X, 0); \
558 if (!fit) \
559 { \
560 push_reload ((X), NULL_RTX, &(X), \
561 NULL, MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
562 VOIDmode, 0, 0, OPNUM, TYPE); \
563 goto WIN; \
564 } \
565 if (reg_equiv_memory_loc[REGNO (reg)] \
566 && (reg_equiv_address[REGNO (reg)] || num_not_at_initial_offset)) \
567 { \
568 rtx mem = make_memloc (reg, REGNO (reg)); \
569 if (! strict_memory_address_p (GET_MODE (mem), XEXP (mem, 0))) \
570 { \
571 /* Note that we're doing address in address - cf. ADDR_TYPE */\
572 find_reloads_address (GET_MODE (mem), &mem, XEXP (mem, 0), \
573 &XEXP (mem, 0), (OPNUM), \
574 ADDR_TYPE (TYPE), (IND), insn); \
575 } \
576 push_reload (mem, NULL, &XEXP (X, 0), NULL, \
577 GENERAL_REGS, Pmode, VOIDmode, 0, 0, \
578 OPNUM, TYPE); \
579 push_reload (X, NULL, &X, NULL, \
580 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), VOIDmode, \
581 0, 0, OPNUM, TYPE); \
582 goto WIN; \
583 } \
584 } \
585}
c24851de 586
e3223ea2
DC		 587#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
588 do { \
589 if (ip2k_mode_dependent_address (ADDR)) goto LABEL; \
590 } while (0)
591
e3223ea2 592#define LEGITIMATE_CONSTANT_P(X) 1
e3223ea2 593
e3223ea2 594#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 7
e3223ea2
DC		 595
596#define MEMORY_MOVE_COST(MODE,CLASS,IN) 6
e3223ea2
DC		 597
598#define SLOW_BYTE_ACCESS 0
e3223ea2
DC		 599
600#define NO_FUNCTION_CSE
e3223ea2 601#define NO_RECURSIVE_FUNCTION_CSE
e3223ea2
DC		 602
603#define TEXT_SECTION_ASM_OP ".text"
e3223ea2 604#define DATA_SECTION_ASM_OP ".data"
e3223ea2 605
e3223ea2 606#define JUMP_TABLES_IN_TEXT_SECTION 1
e3223ea2
DC		 607
608#define ASM_COMMENT_START " ; "
e3223ea2
DC		 609
610#define ASM_APP_ON "/* #APP */\n"
e3223ea2
DC		 611
612#define ASM_APP_OFF "/* #NOAPP */\n"
e3223ea2 613
e3223ea2
DC		 614#define ASM_OUTPUT_DOUBLE(STREAM, VALUE) \
615 fprintf ((STREAM), ".double %.20e\n", (VALUE))
616#define ASM_OUTPUT_FLOAT(STREAM, VALUE) \
617 asm_output_float ((STREAM), (VALUE))
618
e3223ea2
DC		 619#define ASM_OUTPUT_INT(FILE, VALUE) \
620 ( fprintf ((FILE), "\t.long "), \
621 output_addr_const ((FILE), (VALUE)), \
622 fputs ("\n", (FILE)))
623
e3223ea2
DC		 624#define ASM_OUTPUT_SHORT(FILE,VALUE) \
625 asm_output_short ((FILE), (VALUE))
626#define ASM_OUTPUT_CHAR(FILE,VALUE) \
627 asm_output_char ((FILE), (VALUE))
628
e3223ea2
DC		 629#define ASM_OUTPUT_BYTE(FILE,VALUE) \
630 asm_output_byte ((FILE), (VALUE))
e3223ea2
DC		 631
632#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) \
633 ((C) == '\n' || ((C) == '$'))
e3223ea2 634
e3223ea2
DC		 635#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
636do { \
637 fputs ("\t.comm ", (STREAM)); \
638 assemble_name ((STREAM), (NAME)); \
58e15542 639 fprintf ((STREAM), ",%d\n", (int)(SIZE)); \
e3223ea2 640} while (0)
e3223ea2
DC		 641
642#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
643do { \
644 fputs ("\t.lcomm ", (STREAM)); \
645 assemble_name ((STREAM), (NAME)); \
58e15542 646 fprintf ((STREAM), ",%d\n", (int)(SIZE)); \
e3223ea2 647} while (0)
e3223ea2 648
e3223ea2
DC		 649#undef WEAK_ASM_OP
650#define WEAK_ASM_OP ".weak"
651
652#undef ASM_DECLARE_FUNCTION_SIZE
653#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
654 do { \
655 if (!flag_inhibit_size_directive) \
99086d59 656 ASM_OUTPUT_MEASURED_SIZE (FILE, FNAME); \
e3223ea2 657 } while (0)
e3223ea2 658
e3223ea2
DC		 659#define ESCAPES \
660"\1\1\1\1\1\1\1\1btn\1fr\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
661\0\0\"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\
662\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\\\0\0\0\
663\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\1\
664\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
665\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
666\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\
667\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1\1"
668/* A table of bytes codes used by the ASM_OUTPUT_ASCII and
669 ASM_OUTPUT_LIMITED_STRING macros. Each byte in the table
670 corresponds to a particular byte value [0..255]. For any
671 given byte value, if the value in the corresponding table
672 position is zero, the given character can be output directly.
673 If the table value is 1, the byte must be output as a \ooo
674 octal escape. If the tables value is anything else, then the
675 byte value should be output as a \ followed by the value
676 in the table. Note that we can use standard UN*X escape
677 sequences for many control characters, but we don't use
678 \a to represent BEL because some svr4 assemblers (e.g. on
679 the i386) don't know about that. Also, we don't use \v
680 since some versions of gas, such as 2.2 did not accept it. */
681
506a61b1
KG		 682/* Globalizing directive for a label. */
683#define GLOBAL_ASM_OP ".global\t"
e3223ea2 684
e3223ea2
DC		 685#define REGISTER_NAMES { \
686 "$00","$01","$02","$03","iph","ipl","sph","spl", \
687 "pch","pcl","wreg","status","dph","dpl","$0e","mulh", \
688 "$10","$11","$12","$13","$14","$15","$16","$17", \
689 "$18","$19","$1a","$1b","$1c","$1d","$1e","$1f", \
690 "$20","$21","$22","$23","$24","$25","$26","$27", \
691 "$28","$29","$2a","$2b","$2c","$2d","$2e","$2f", \
692 "$30","$31","$32","$33","$34","$35","$36","$37", \
693 "$38","$39","$3a","$3b","$3c","$3d","$3e","$3f", \
694 "$40","$41","$42","$43","$44","$45","$46","$47", \
695 "$48","$49","$4a","$4b","$4c","$4d","$4e","$4f", \
696 "$50","$51","$52","$53","$54","$55","$56","$57", \
697 "$58","$59","$5a","$5b","$5c","$5d","$5e","$5f", \
698 "$60","$61","$62","$63","$64","$65","$66","$67", \
699 "$68","$69","$6a","$6b","$6c","$6d","$6e","$6f", \
700 "$70","$71","$72","$73","$74","$75","$76","$77", \
701 "$78","$79","$7a","$7b","$7c","$7d","callh","calll", \
702 "$80","$81","$82","$83","$84","$85","$86","$87", \
703 "$88","$89","$8a","$8b","$8c","$8d","$8e","$8f", \
704 "$90","$91","$92","$93","$94","$95","$96","$97", \
705 "$98","$99","$9a","$9b","$9c","$9d","$9e","$9f", \
706 "$a0","$a1","$a2","$a3","$a4","$a5","$a6","$a7", \
707 "$a8","$a9","$aa","$ab","$ac","$ad","$ae","$af", \
708 "$b0","$b1","$b2","$b3","$b4","$b5","$b6","$b7", \
709 "$b8","$b9","$ba","$bb","$bc","$bd","$be","$bf", \
710 "$c0","$c1","$c2","$c3","$c4","$c5","$c6","$c7", \
711 "$c8","$c9","$ca","$cb","$cc","$cd","$ce","$cf", \
712 "$d0","$d1","$d2","$d3","$d4","$d5","$d6","$d7", \
713 "$d8","$d9","$da","$db","$dc","$dd","$de","$df", \
714 "$e0","$e1","$e2","$e3","$e4","$e5","$e6","$e7", \
715 "$e8","$e9","$ea","$eb","$ec","$ed","$ee","$ef", \
716 "$f0","$f1","$f2","$f3","$f4","$f5","$f6","$f7", \
717 "$f8","$f9","$fa","$fb","$fc","$fd","$fe","$ff", \
718 "vfph","vfpl","vaph","vapl"}
719
e3223ea2
DC		 720#define PRINT_OPERAND(STREAM, X, CODE) \
721 print_operand ((STREAM), (X), (CODE))
e3223ea2
DC		 722
723#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
724 ((CODE) == '<' || (CODE) == '>')
725
e3223ea2 726#define PRINT_OPERAND_ADDRESS(STREAM, X) print_operand_address(STREAM, X)
e3223ea2
DC		 727
728/* Since register names don't have a prefix, we must preface all
729 user identifiers with the '_' to prevent confusion. */
730
731#undef USER_LABEL_PREFIX
732#define USER_LABEL_PREFIX "_"
733#define LOCAL_LABEL_PREFIX ".L"
e3223ea2
DC		 734
735#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
736 asm_fprintf ((STREAM), "\tpage\t%L%d\n\tjmp\t%L%d\n", (VALUE), (VALUE))
737
738/* elfos.h presumes that we will want switch/case dispatch tables aligned.
739 This is not so for the ip2k. */
740#undef ASM_OUTPUT_CASE_LABEL
741
742#undef ASM_OUTPUT_ADDR_VEC_ELT
743#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
744 asm_fprintf ((STREAM), "\tpage\t%L%d\n\tjmp\t%L%d\n", (VALUE), (VALUE))
745
e3223ea2
DC		 746#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
747 fprintf ((STREAM), "\t.align %d\n", (POWER))
e3223ea2
DC		 748
749/* Since instructions are 16 bit word addresses, we should lie and claim that
750 the dispatch vectors are in QImode. Otherwise the offset into the jump
751 table will be scaled by the MODE_SIZE. */
752
753#define CASE_VECTOR_MODE QImode
e3223ea2
DC		 754
755#undef WORD_REGISTER_OPERATIONS
e3223ea2 756
e3223ea2 757#define MOVE_MAX 1
e3223ea2
DC		 758
759#define MOVE_RATIO 3
760/* MOVE_RATIO is the number of move instructions that is better than a
761 block move. Make this small on the IP2k, since the code size grows very
762 large with each move. */
763
764#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
e3223ea2
DC		 765
766#define Pmode HImode
e3223ea2
DC		 767
768#define FUNCTION_MODE HImode
e3223ea2 769
e3223ea2 770#define DOLLARS_IN_IDENTIFIERS 0
e3223ea2 771
e3223ea2
DC		 772extern int ip2k_reorg_in_progress;
773/* Flag if we're in the middle of IP2k-specific reorganization. */
774
775extern int ip2k_reorg_completed;
776/* Flag if we've completed our IP2k-specific reorganization. If we have
777 then we allow quite a few more tricks than before. */
778
779extern int ip2k_reorg_split_dimode;
780extern int ip2k_reorg_split_simode;
781extern int ip2k_reorg_split_qimode;
782extern int ip2k_reorg_split_himode;
783/* Flags for various split operations that we run in sequence. */
784
785extern int ip2k_reorg_merge_qimode;
786/* Flag to indicate that it's safe to merge QImode operands. */
787
e3223ea2
DC		 788#define TRAMPOLINE_TEMPLATE(FILE) abort ()
789
e3223ea2
DC		 790#define TRAMPOLINE_SIZE 4
791
e3223ea2
DC		 792#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
793{ \
794 emit_move_insn (gen_rtx_MEM (HImode, plus_constant ((TRAMP), 2)), \
795 CXT); \
796 emit_move_insn (gen_rtx_MEM (HImode, plus_constant ((TRAMP), 6)), \
797 FNADDR); \
798}
799/* Store in cc_status the expressions
800 that the condition codes will describe
801 after execution of an instruction whose pattern is EXP.
802 Do not alter them if the instruction would not alter the cc's. */
803
c8bf1a1a 804#define NOTICE_UPDATE_CC(EXP, INSN) (void)(0)
e3223ea2
DC		 805
806/* Output assembler code to FILE to increment profiler label # LABELNO
807 for profiling a function entry. */
808
809#define FUNCTION_PROFILER(FILE, LABELNO) \
810 fprintf ((FILE), "/* profiler %d */", (LABELNO))
811
812#define TARGET_MEM_FUNCTIONS
e3223ea2
DC		 813
814#undef ENDFILE_SPEC
815#undef LINK_SPEC
816#undef STARTFILE_SPEC
817
e3223ea2
DC		 818#if defined(__STDC__) || defined(ALMOST_STDC)
819#define AS2(a,b,c) #a "\t" #b "," #c
820#define AS1(a,b) #a "\t" #b
821#else
822#define AS1(a,b) "a b"
823#define AS2(a,b,c) "a b,c"
824#endif
825#define OUT_AS1(a,b) output_asm_insn (AS1 (a,b), operands)
826#define OUT_AS2(a,b,c) output_asm_insn (AS2 (a,b,c), operands)
827#define CR_TAB "\n\t"
828
e3223ea2
DC		 829#define PREDICATE_CODES \
830 {"ip2k_ip_operand", {MEM}}, \
831 {"ip2k_short_operand", {MEM}}, \
832 {"ip2k_gen_operand", {MEM, REG, SUBREG}}, \
833 {"ip2k_nonptr_operand", {REG, SUBREG}}, \
834 {"ip2k_ptr_operand", {REG, SUBREG}}, \
835 {"ip2k_split_dest_operand", {REG, SUBREG, MEM}}, \
836 {"ip2k_sp_operand", {REG}}, \
837 {"ip2k_nonsp_reg_operand", {REG, SUBREG}}, \
838 {"ip2k_symbol_ref_operand", {SYMBOL_REF}}, \
839 {"ip2k_binary_operator", {PLUS, MINUS, MULT, DIV, \
840 UDIV, MOD, UMOD, AND, IOR, \
841 XOR, COMPARE, ASHIFT, \
842 ASHIFTRT, LSHIFTRT}}, \
843 {"ip2k_unary_operator", {NEG, NOT, SIGN_EXTEND, \
844 ZERO_EXTEND}}, \
845 {"ip2k_unsigned_comparison_operator", {LTU, GTU, NE, \
846 EQ, LEU, GEU}},\
847 {"ip2k_signed_comparison_operator", {LT, GT, LE, GE}},
848
23532de9 849#define DWARF2_DEBUGGING_INFO 1
e3223ea2
DC		 850
851#define DWARF2_ASM_LINE_DEBUG_INFO 1
852
853#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
854
ff482c8d 855/* Miscellaneous macros to describe machine specifics. */
e3223ea2 856
e3223ea2
DC		 857#define IS_PSEUDO_P(R) (REGNO (R) >= FIRST_PSEUDO_REGISTER)
858
859/* Default calculations would cause DWARF address sizes to be 2 bytes,
860 but the Harvard architecture of the IP2k and the word-addressed 64k
861 of instruction memory causes us to want a 32-bit "address" field. */
862#undef DWARF2_ADDR_SIZE
863#define DWARF2_ADDR_SIZE 4
864
Mirror of https://gcc.gnu.org/git/gcc.git