]>
Commit | Line | Data |
---|---|---|
62ec3b53 | 1 | /* Definitions of target machine for GNU compiler. LoongArch version. |
83ffe9cd | 2 | Copyright (C) 2021-2023 Free Software Foundation, Inc. |
62ec3b53 | 3 | Contributed by Loongson Ltd. |
4 | Based on MIPS and RISC-V target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | /* LoongArch external variables defined in loongarch.cc. */ | |
23 | ||
24 | #include "config/loongarch/loongarch-opts.h" | |
25 | ||
26 | /* Macros to silence warnings about numbers being signed in traditional | |
27 | C and unsigned in ISO C when compiled on 32-bit hosts. */ | |
28 | ||
29 | #define BITMASK_HIGH (((unsigned long) 1) << 31) /* 0x80000000 */ | |
30 | ||
31 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
32 | ||
33 | /* Target CPU builtins. */ | |
34 | #define TARGET_CPU_CPP_BUILTINS() loongarch_cpu_cpp_builtins (pfile) | |
35 | ||
36 | /* Default target_flags if no switches are specified. */ | |
37 | ||
38 | #ifdef IN_LIBGCC2 | |
39 | #undef TARGET_64BIT | |
40 | /* Make this compile time constant for libgcc2. */ | |
41 | #ifdef __loongarch64 | |
42 | #define TARGET_64BIT 1 | |
43 | #else | |
44 | #define TARGET_64BIT 0 | |
45 | #endif | |
46 | #endif /* IN_LIBGCC2 */ | |
47 | ||
48 | #define TARGET_LIBGCC_SDATA_SECTION ".sdata" | |
49 | ||
50 | /* Driver native functions for SPEC processing in the GCC driver. */ | |
51 | #include "loongarch-driver.h" | |
52 | ||
53 | /* This definition replaces the formerly used 'm' constraint with a | |
54 | different constraint letter in order to avoid changing semantics of | |
55 | the 'm' constraint when accepting new address formats in | |
56 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
57 | must not be used in insn definitions or inline assemblies. */ | |
58 | #define TARGET_MEM_CONSTRAINT 'w' | |
59 | ||
60 | /* Tell collect what flags to pass to nm. */ | |
61 | #ifndef NM_FLAGS | |
62 | #define NM_FLAGS "-Bn" | |
63 | #endif | |
64 | ||
65 | /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be | |
66 | overridden by subtargets. */ | |
67 | ||
68 | #ifndef SUBTARGET_ASM_SPEC | |
69 | #define SUBTARGET_ASM_SPEC "" | |
70 | #endif | |
71 | ||
72 | #undef ASM_SPEC | |
73 | #define ASM_SPEC "%{mabi=*} %{subtarget_asm_spec}" | |
74 | ||
75 | /* Extra switches sometimes passed to the linker. */ | |
76 | ||
77 | #ifndef LINK_SPEC | |
78 | #define LINK_SPEC "" | |
79 | #endif /* LINK_SPEC defined */ | |
80 | ||
81 | /* Specs for the compiler proper. */ | |
82 | ||
83 | /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ | |
84 | ||
85 | #undef CC1_SPEC | |
86 | #define CC1_SPEC "\ | |
87 | %{G*} \ | |
88 | %(subtarget_cc1_spec)" | |
89 | ||
90 | /* Preprocessor specs. */ | |
91 | ||
92 | /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be | |
93 | overridden by subtargets. */ | |
94 | #ifndef SUBTARGET_CPP_SPEC | |
95 | #define SUBTARGET_CPP_SPEC "" | |
96 | #endif | |
97 | ||
98 | #define CPP_SPEC "%(subtarget_cpp_spec)" | |
99 | ||
100 | /* This macro defines names of additional specifications to put in the specs | |
101 | that can be used in various specifications like CC1_SPEC. Its definition | |
102 | is an initializer with a subgrouping for each command option. | |
103 | ||
104 | Each subgrouping contains a string constant, that defines the | |
105 | specification name, and a string constant that used by the GCC driver | |
106 | program. | |
107 | ||
108 | Do not define this macro if it does not need to do anything. */ | |
109 | ||
110 | #define EXTRA_SPECS \ | |
111 | {"subtarget_cc1_spec", SUBTARGET_CC1_SPEC}, \ | |
112 | {"subtarget_cpp_spec", SUBTARGET_CPP_SPEC}, \ | |
113 | {"subtarget_asm_spec", SUBTARGET_ASM_SPEC}, | |
114 | ||
115 | /* Registers may have a prefix which can be ignored when matching | |
116 | user asm and register definitions. */ | |
117 | #ifndef REGISTER_PREFIX | |
118 | #define REGISTER_PREFIX "$" | |
119 | #endif | |
120 | ||
121 | /* Local compiler-generated symbols must have a prefix that the assembler | |
122 | understands. */ | |
123 | ||
124 | #define LOCAL_LABEL_PREFIX "." | |
125 | ||
126 | /* By default on the loongarch, external symbols do not have an underscore | |
127 | prepended. */ | |
128 | ||
129 | #define USER_LABEL_PREFIX "" | |
130 | ||
131 | #ifndef PREFERRED_DEBUGGING_TYPE | |
132 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
133 | #endif | |
134 | ||
135 | /* The size of DWARF addresses should be the same as the size of symbols | |
136 | in the target file format. */ | |
137 | #define DWARF2_ADDR_SIZE (TARGET_64BIT ? 8 : 4) | |
138 | ||
139 | /* By default, turn on GDB extensions. */ | |
140 | #define DEFAULT_GDB_EXTENSIONS 1 | |
141 | ||
142 | /* By default, produce dwarf version 2 format debugging output in response | |
143 | to the ā-gā option. */ | |
144 | #define DWARF2_DEBUGGING_INFO 1 | |
145 | ||
146 | /* The mapping from gcc register number to DWARF 2 CFA column number. */ | |
147 | #define DWARF_FRAME_REGNUM(REGNO) loongarch_dwarf_regno[REGNO] | |
148 | ||
149 | /* The DWARF 2 CFA column which tracks the return address. */ | |
150 | #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM | |
151 | ||
152 | /* Before the prologue, RA lives in r1. */ | |
153 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) | |
154 | ||
155 | /* Describe how we implement __builtin_eh_return. */ | |
156 | #define EH_RETURN_DATA_REGNO(N) \ | |
157 | ((N) < (4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
158 | ||
159 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_ARG_FIRST + 4) | |
160 | ||
161 | #define EH_USES(N) loongarch_eh_uses (N) | |
162 | ||
163 | /* Offsets recorded in opcodes are a multiple of this alignment factor. | |
164 | The default for this in 64-bit mode is 8, which causes problems with | |
165 | SFmode register saves. */ | |
166 | #define DWARF_CIE_DATA_ALIGNMENT -4 | |
167 | ||
168 | /* Target machine storage layout. */ | |
169 | ||
170 | #define BITS_BIG_ENDIAN 0 | |
171 | #define BYTES_BIG_ENDIAN 0 | |
172 | #define WORDS_BIG_ENDIAN 0 | |
173 | ||
174 | #define MAX_BITS_PER_WORD 64 | |
175 | ||
176 | /* Width of a word, in units (bytes). */ | |
177 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
178 | #ifndef IN_LIBGCC2 | |
179 | #define MIN_UNITS_PER_WORD 4 | |
180 | #endif | |
181 | ||
182 | /* For LARCH, width of a floating point register. */ | |
183 | #define UNITS_PER_FPREG (TARGET_DOUBLE_FLOAT ? 8 : 4) | |
184 | ||
185 | /* The largest size of value that can be held in floating-point | |
186 | registers and moved with a single instruction. */ | |
187 | #define UNITS_PER_HWFPVALUE \ | |
188 | (TARGET_SOFT_FLOAT ? 0 : UNITS_PER_FPREG) | |
189 | ||
190 | /* The largest size of value that can be held in floating-point | |
191 | registers. */ | |
192 | #define UNITS_PER_FPVALUE \ | |
193 | (TARGET_SOFT_FLOAT ? 0 \ | |
194 | : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ | |
195 | : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) | |
196 | ||
197 | /* The number of bytes in a double. */ | |
198 | #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) | |
199 | ||
200 | /* Set the sizes of the core types. */ | |
201 | #define SHORT_TYPE_SIZE 16 | |
202 | #define INT_TYPE_SIZE 32 | |
203 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
204 | #define LONG_LONG_TYPE_SIZE 64 | |
205 | ||
206 | #define FLOAT_TYPE_SIZE 32 | |
207 | #define DOUBLE_TYPE_SIZE 64 | |
208 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_64BIT ? 128 : 64) | |
209 | ||
210 | /* Define the sizes of fixed-point types. */ | |
211 | #define SHORT_FRACT_TYPE_SIZE 8 | |
212 | #define FRACT_TYPE_SIZE 16 | |
213 | #define LONG_FRACT_TYPE_SIZE 32 | |
214 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
215 | ||
216 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
217 | #define ACCUM_TYPE_SIZE 32 | |
218 | #define LONG_ACCUM_TYPE_SIZE 64 | |
219 | #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) | |
220 | ||
221 | /* long double is not a fixed mode, but the idea is that, if we | |
222 | support long double, we also want a 128-bit integer type. */ | |
223 | #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE | |
224 | ||
225 | /* Width in bits of a pointer. */ | |
226 | #ifndef POINTER_SIZE | |
227 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
228 | #endif | |
229 | ||
230 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
231 | #define PARM_BOUNDARY BITS_PER_WORD | |
232 | ||
233 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
234 | #define FUNCTION_BOUNDARY 32 | |
235 | ||
236 | /* Alignment of field after `int : 0' in a structure. */ | |
237 | #define EMPTY_FIELD_BOUNDARY 32 | |
238 | ||
239 | /* Number of bits which any structure or union's size must be a multiple of. | |
240 | Each structure or union's size is rounded up to a multiple of this. */ | |
241 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
242 | ||
243 | /* There is no point aligning anything to a rounder boundary than | |
244 | LONG_DOUBLE_TYPE_SIZE. */ | |
245 | #define BIGGEST_ALIGNMENT (LONG_DOUBLE_TYPE_SIZE) | |
246 | ||
247 | /* All accesses must be aligned. */ | |
248 | #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGN) | |
249 | ||
250 | /* Define this if you wish to imitate the way many other C compilers | |
251 | handle alignment of bitfields and the structures that contain | |
252 | them. | |
253 | ||
254 | The behavior is that the type written for a bit-field (`int', | |
255 | `short', or other integer type) imposes an alignment for the | |
256 | entire structure, as if the structure really did contain an | |
257 | ordinary field of that type. In addition, the bit-field is placed | |
258 | within the structure so that it would fit within such a field, | |
259 | not crossing a boundary for it. | |
260 | ||
261 | Thus, on most machines, a bit-field whose type is written as `int' | |
262 | would not cross a four-byte boundary, and would force four-byte | |
263 | alignment for the whole structure. (The alignment used may not | |
264 | be four bytes; it is controlled by the other alignment | |
265 | parameters.) | |
266 | ||
267 | If the macro is defined, its definition should be a C expression; | |
268 | a nonzero value for the expression enables this behavior. */ | |
269 | ||
270 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
271 | ||
272 | /* If defined, a C expression to compute the alignment for a static | |
273 | variable. TYPE is the data type, and ALIGN is the alignment that | |
274 | the object would ordinarily have. The value of this macro is used | |
275 | instead of that alignment to align the object. | |
276 | ||
277 | If this macro is not defined, then ALIGN is used. | |
278 | ||
279 | One use of this macro is to increase alignment of medium-size | |
280 | data to make it all fit in fewer cache lines. Another is to | |
281 | cause character arrays to be word-aligned so that `strcpy' calls | |
282 | that copy constants to character arrays can be done inline. */ | |
283 | ||
284 | #undef DATA_ALIGNMENT | |
285 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
286 | ((((ALIGN) < BITS_PER_WORD) \ | |
287 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
288 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
289 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
290 | ||
291 | /* We need this for the same reason as DATA_ALIGNMENT, namely to cause | |
292 | character arrays to be word-aligned so that `strcpy' calls that copy | |
293 | constants to character arrays can be done inline, and 'strcmp' can be | |
294 | optimised to use word loads. */ | |
295 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) | |
296 | ||
297 | /* Define if operations between registers always perform the operation | |
298 | on the full register even if a narrower mode is specified. */ | |
299 | #define WORD_REGISTER_OPERATIONS 1 | |
300 | ||
301 | /* When in 64-bit mode, move insns will sign extend SImode and FCCmode | |
302 | moves. All other references are zero extended. */ | |
303 | #define LOAD_EXTEND_OP(MODE) \ | |
304 | (TARGET_64BIT && ((MODE) == SImode || (MODE) == FCCmode) ? SIGN_EXTEND \ | |
305 | : ZERO_EXTEND) | |
306 | ||
307 | /* Define this macro if it is advisable to hold scalars in registers | |
308 | in a wider mode than that declared by the program. In such cases, | |
309 | the value is constrained to be within the bounds of the declared | |
310 | type, but kept valid in the wider mode. The signedness of the | |
311 | extension may differ from that of the type. */ | |
312 | ||
313 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
314 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
315 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ | |
316 | { \ | |
317 | if ((MODE) == SImode) \ | |
318 | (UNSIGNEDP) = 0; \ | |
319 | (MODE) = Pmode; \ | |
320 | } | |
321 | ||
322 | /* Pmode is always the same as ptr_mode, but not always the same as word_mode. | |
323 | Extensions of pointers to word_mode must be signed. */ | |
324 | #define POINTERS_EXTEND_UNSIGNED false | |
325 | ||
326 | /* Define if loading short immediate values into registers sign extends. */ | |
327 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 | |
328 | ||
329 | /* The clz.{w/d} instructions have the natural values at 0. */ | |
330 | ||
331 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
332 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) | |
333 | ||
334 | /* Standard register usage. */ | |
335 | ||
336 | /* Number of hardware registers. We have: | |
337 | ||
338 | - 32 integer registers | |
339 | - 32 floating point registers | |
340 | - 8 condition code registers | |
341 | - 2 fake registers: | |
342 | - ARG_POINTER_REGNUM | |
343 | - FRAME_POINTER_REGNUM | |
344 | */ | |
345 | ||
346 | #define FIRST_PSEUDO_REGISTER 74 | |
347 | ||
348 | /* zero, tp, sp and x are fixed. */ | |
349 | #define FIXED_REGISTERS \ | |
350 | { /* General registers. */ \ | |
351 | 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
352 | 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
353 | /* Floating-point registers. */ \ | |
354 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
355 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
356 | /* Others. */ \ | |
357 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1} | |
358 | ||
359 | /* The call RTLs themselves clobber ra. */ | |
360 | #define CALL_USED_REGISTERS \ | |
361 | { /* General registers. */ \ | |
362 | 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
363 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
364 | /* Floating-point registers. */ \ | |
365 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
366 | 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
367 | /* Others. */ \ | |
368 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} | |
369 | ||
370 | /* Internal macros to classify a register number as to whether it's a | |
371 | general purpose register, a floating point register, or a status | |
372 | register. */ | |
373 | ||
374 | #define GP_REG_FIRST 0 | |
375 | #define GP_REG_LAST 31 | |
376 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
377 | ||
378 | #define FP_REG_FIRST 32 | |
379 | #define FP_REG_LAST 63 | |
380 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
381 | ||
382 | /* The DWARF 2 CFA column which tracks the return address from a | |
383 | signal handler context. This means that to maintain backwards | |
384 | compatibility, no hard register can be assigned this column if it | |
385 | would need to be handled by the DWARF unwinder. */ | |
386 | #define DWARF_ALT_FRAME_RETURN_COLUMN 72 | |
387 | ||
388 | #define FCC_REG_FIRST 64 | |
389 | #define FCC_REG_LAST 71 | |
390 | #define FCC_REG_NUM (FCC_REG_LAST - FCC_REG_FIRST + 1) | |
391 | ||
392 | #define GP_REG_P(REGNO) \ | |
393 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
394 | #define FP_REG_P(REGNO) \ | |
395 | ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
396 | #define FCC_REG_P(REGNO) \ | |
397 | ((unsigned int) ((int) (REGNO) - FCC_REG_FIRST) < FCC_REG_NUM) | |
398 | ||
399 | #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) | |
400 | ||
401 | /* Select a register mode required for caller save of hard regno REGNO. */ | |
402 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
403 | loongarch_hard_regno_caller_save_mode (REGNO, NREGS, MODE) | |
404 | ||
405 | /* Register to use for pushing function arguments. */ | |
406 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 3) | |
407 | ||
408 | /* These two registers don't really exist: they get eliminated to either | |
409 | the stack or hard frame pointer. */ | |
410 | #define ARG_POINTER_REGNUM 72 | |
411 | #define FRAME_POINTER_REGNUM 73 | |
412 | ||
413 | #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 22) | |
414 | ||
415 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 | |
416 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
417 | ||
418 | /* Register in which static-chain is passed to a function. */ | |
419 | #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 20) /* $t8 */ | |
420 | ||
421 | #define GP_TEMP_FIRST (GP_REG_FIRST + 12) | |
422 | #define LARCH_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1) | |
423 | #define LARCH_PROLOGUE_TEMP2_REGNUM (GP_TEMP_FIRST) | |
424 | #define LARCH_PROLOGUE_TEMP3_REGNUM (GP_TEMP_FIRST + 2) | |
425 | #define LARCH_EPILOGUE_TEMP_REGNUM (GP_TEMP_FIRST) | |
426 | ||
427 | #define CALLEE_SAVED_REG_NUMBER(REGNO) \ | |
428 | ((REGNO) >= 22 && (REGNO) <= 31 ? (REGNO) - 22 : -1) | |
429 | ||
430 | #define LARCH_PROLOGUE_TEMP(MODE) \ | |
431 | gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP_REGNUM) | |
432 | #define LARCH_PROLOGUE_TEMP2(MODE) \ | |
433 | gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP2_REGNUM) | |
434 | #define LARCH_PROLOGUE_TEMP3(MODE) \ | |
435 | gen_rtx_REG (MODE, LARCH_PROLOGUE_TEMP3_REGNUM) | |
436 | #define LARCH_EPILOGUE_TEMP(MODE) \ | |
437 | gen_rtx_REG (MODE, LARCH_EPILOGUE_TEMP_REGNUM) | |
438 | ||
439 | /* Define this macro if it is as good or better to call a constant | |
440 | function address than to call an address kept in a register. */ | |
441 | #define NO_FUNCTION_CSE 1 | |
442 | ||
443 | #define THREAD_POINTER_REGNUM (GP_REG_FIRST + 2) | |
444 | ||
445 | /* Define the classes of registers for register constraints in the | |
446 | machine description. Also define ranges of constants. | |
447 | ||
448 | One of the classes must always be named ALL_REGS and include all hard regs. | |
449 | If there is more than one class, another class must be named NO_REGS | |
450 | and contain no registers. | |
451 | ||
452 | The name GENERAL_REGS must be the name of a class (or an alias for | |
453 | another name such as ALL_REGS). This is the class of registers | |
454 | that is allowed by "r" in a register constraint. | |
455 | Also, registers outside this class are allocated only when | |
456 | instructions express preferences for them. | |
457 | ||
458 | The classes must be numbered in nondecreasing order; that is, | |
459 | a larger-numbered class must never be contained completely | |
460 | in a smaller-numbered class. | |
461 | ||
462 | For any two classes, it is very desirable that there be another | |
463 | class that represents their union. */ | |
464 | ||
465 | enum reg_class | |
466 | { | |
467 | NO_REGS, /* no registers in set */ | |
468 | SIBCALL_REGS, /* registers used by indirect sibcalls */ | |
469 | JIRL_REGS, /* registers used by indirect calls */ | |
470 | CSR_REGS, /* integer registers except for $r0 and $r1 for lcsr. */ | |
471 | GR_REGS, /* integer registers */ | |
472 | FP_REGS, /* floating point registers */ | |
473 | FCC_REGS, /* status registers (fp status) */ | |
474 | FRAME_REGS, /* arg pointer and frame pointer */ | |
475 | ALL_REGS, /* all registers */ | |
476 | LIM_REG_CLASSES /* max value + 1 */ | |
477 | }; | |
478 | ||
479 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
480 | ||
481 | #define GENERAL_REGS GR_REGS | |
482 | ||
483 | /* An initializer containing the names of the register classes as C | |
484 | string constants. These names are used in writing some of the | |
485 | debugging dumps. */ | |
486 | ||
487 | #define REG_CLASS_NAMES \ | |
488 | { \ | |
489 | "NO_REGS", \ | |
490 | "SIBCALL_REGS", \ | |
491 | "JIRL_REGS", \ | |
492 | "CSR_REGS", \ | |
493 | "GR_REGS", \ | |
494 | "FP_REGS", \ | |
495 | "FCC_REGS", \ | |
496 | "FRAME_REGS", \ | |
497 | "ALL_REGS" \ | |
498 | } | |
499 | ||
500 | /* An initializer containing the contents of the register classes, | |
501 | as integers which are bit masks. The Nth integer specifies the | |
502 | contents of class N. The way the integer MASK is interpreted is | |
503 | that register R is in the class if `MASK & (1 << R)' is 1. | |
504 | ||
505 | When the machine has more than 32 registers, an integer does not | |
506 | suffice. Then the integers are replaced by sub-initializers, | |
507 | braced groupings containing several integers. Each | |
508 | sub-initializer must be suitable as an initializer for the type | |
509 | `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
510 | ||
511 | #define REG_CLASS_CONTENTS \ | |
512 | { \ | |
513 | { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
020b7d98 | 514 | { 0x001fd000, 0x00000000, 0x00000000 }, /* SIBCALL_REGS */ \ |
62ec3b53 | 515 | { 0xff9ffff0, 0x00000000, 0x00000000 }, /* JIRL_REGS */ \ |
516 | { 0xfffffffc, 0x00000000, 0x00000000 }, /* CSR_REGS */ \ | |
517 | { 0xffffffff, 0x00000000, 0x00000000 }, /* GR_REGS */ \ | |
518 | { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ | |
519 | { 0x00000000, 0x00000000, 0x000000ff }, /* FCC_REGS */ \ | |
520 | { 0x00000000, 0x00000000, 0x00000300 }, /* FRAME_REGS */ \ | |
521 | { 0xffffffff, 0xffffffff, 0x000003ff } /* ALL_REGS */ \ | |
522 | } | |
523 | ||
524 | /* A C expression whose value is a register class containing hard | |
525 | register REGNO. In general there is more that one such class; | |
526 | choose a class which is "minimal", meaning that no smaller class | |
527 | also contains the register. */ | |
528 | ||
529 | #define REGNO_REG_CLASS(REGNO) loongarch_regno_to_class[(REGNO)] | |
530 | ||
531 | /* A macro whose definition is the name of the class to which a | |
532 | valid base register must belong. A base register is one used in | |
533 | an address which is the register value plus a displacement. */ | |
534 | ||
535 | #define BASE_REG_CLASS (GR_REGS) | |
536 | ||
537 | /* A macro whose definition is the name of the class to which a | |
538 | valid index register must belong. An index register is one used | |
539 | in an address where its value is either multiplied by a scale | |
540 | factor or added to another register (as well as added to a | |
541 | displacement). */ | |
542 | ||
543 | #define INDEX_REG_CLASS GR_REGS | |
544 | ||
545 | /* We generally want to put call-clobbered registers ahead of | |
546 | call-saved ones. (IRA expects this.) */ | |
547 | ||
548 | #define REG_ALLOC_ORDER \ | |
549 | { /* Call-clobbered GPRs. */ \ | |
550 | 12, 13, 14, 15, 16, 17, 18, 19, 20, 4, 5, 6, 7, 8, 9, 10, 11, 1, \ | |
551 | /* Call-saved GPRs. */ \ | |
552 | 23, 24, 25, 26, 27, 28, 29, 30, 31, \ | |
553 | /* GPRs that can never be exposed to the register allocator. */ \ | |
554 | 0, 2, 3, 21, 22, \ | |
555 | /* Call-clobbered FPRs. */ \ | |
556 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ | |
557 | 48, 49, 50, 51,52, 53, 54, 55, \ | |
558 | 56, 57, 58, 59, 60, 61, 62, 63, \ | |
559 | /* None of the remaining classes have defined call-saved \ | |
560 | registers. */ \ | |
561 | 64, 65, 66, 67, 68, 69, 70, 71, 72, 73} | |
562 | ||
563 | #define IMM_BITS 12 | |
b169b67d CX |
564 | #define IMM_REACH (HOST_WIDE_INT_1 << IMM_BITS) |
565 | #define HWIT_1U HOST_WIDE_INT_1U | |
62ec3b53 | 566 | |
567 | /* True if VALUE is an unsigned 6-bit number. */ | |
568 | ||
569 | #define UIMM6_OPERAND(VALUE) (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) | |
570 | ||
571 | /* True if VALUE is a signed 10-bit number. */ | |
572 | ||
573 | #define IMM10_OPERAND(VALUE) ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) | |
574 | ||
575 | /* True if VALUE is a signed 12-bit number. */ | |
576 | ||
577 | #define IMM12_OPERAND(VALUE) \ | |
578 | ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH / 2 < IMM_REACH) | |
579 | ||
580 | /* True if VALUE is a signed 16-bit number. */ | |
581 | ||
582 | #define IMM16_OPERAND(VALUE) \ | |
583 | ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) | |
584 | ||
585 | /* True if VALUE is an unsigned 12-bit number. */ | |
586 | ||
587 | #define IMM12_OPERAND_UNSIGNED(VALUE) \ | |
588 | (((VALUE) & ~(unsigned HOST_WIDE_INT) (IMM_REACH - 1)) == 0) | |
589 | ||
590 | /* True if VALUE can be loaded into a register using LU12I. */ | |
591 | ||
592 | #define LU12I_OPERAND(VALUE) \ | |
b169b67d CX |
593 | (((VALUE) | ((HWIT_1U << 31) - IMM_REACH)) == ((HWIT_1U << 31) - IMM_REACH) \ |
594 | || ((VALUE) | ((HWIT_1U << 31) - IMM_REACH)) + IMM_REACH == 0) | |
62ec3b53 | 595 | |
596 | /* True if VALUE can be loaded into a register using LU32I. */ | |
597 | ||
598 | #define LU32I_OPERAND(VALUE) \ | |
b169b67d CX |
599 | (((VALUE) | (((HWIT_1U << 19) - 1) << 32)) == (((HWIT_1U << 19) - 1) << 32) \ |
600 | || ((VALUE) | (((HWIT_1U << 19) - 1) << 32)) + (HWIT_1U << 32) == 0) | |
62ec3b53 | 601 | |
602 | /* True if VALUE can be loaded into a register using LU52I. */ | |
603 | ||
b169b67d CX |
604 | #define HWIT_UC_0xFFF HOST_WIDE_INT_UC(0xfff) |
605 | #define LU52I_OPERAND(VALUE) \ | |
606 | (((VALUE) | (HWIT_UC_0xFFF << 52)) == (HWIT_UC_0xFFF << 52)) | |
62ec3b53 | 607 | |
608 | /* Return a value X with the low 12 bits clear, and such that | |
609 | VALUE - X is a signed 12-bit value. */ | |
610 | ||
611 | #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH / 2)) & ~(IMM_REACH - 1)) | |
612 | ||
613 | #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE)) | |
614 | ||
615 | #define IMM12_INT(X) IMM12_OPERAND (INTVAL (X)) | |
616 | #define IMM12_INT_UNSIGNED(X) IMM12_OPERAND_UNSIGNED (INTVAL (X)) | |
617 | #define LU12I_INT(X) LU12I_OPERAND (INTVAL (X)) | |
618 | #define LU32I_INT(X) LU32I_OPERAND (INTVAL (X)) | |
619 | #define LU52I_INT(X) LU52I_OPERAND (INTVAL (X)) | |
d5e401fb | 620 | #define LARCH_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) |
62ec3b53 | 621 | #define LARCH_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255)) |
622 | #define LARCH_16BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -32768, 32767)) | |
623 | #define LARCH_SHIFT_2_OFFSET_P(OFFSET) (((OFFSET) & 0x3) == 0) | |
624 | ||
625 | /* Return the maximum number of consecutive registers | |
626 | needed to represent mode MODE in a register of class CLASS. */ | |
627 | ||
628 | #define CLASS_MAX_NREGS(CLASS, MODE) loongarch_class_max_nregs (CLASS, MODE) | |
629 | ||
630 | /* Stack layout; function entry, exit and calling. */ | |
631 | ||
632 | #define STACK_GROWS_DOWNWARD 1 | |
633 | ||
634 | #define FRAME_GROWS_DOWNWARD 1 | |
635 | ||
636 | #define RETURN_ADDR_RTX loongarch_return_addr | |
637 | ||
638 | /* Similarly, don't use the least-significant bit to tell pointers to | |
639 | code from vtable index. */ | |
640 | ||
641 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
642 | ||
643 | #define ELIMINABLE_REGS \ | |
644 | { \ | |
645 | {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
646 | {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
647 | {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
648 | {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
649 | } | |
650 | ||
651 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
652 | (OFFSET) = loongarch_initial_elimination_offset ((FROM), (TO)) | |
653 | ||
654 | /* Allocate stack space for arguments at the beginning of each function. */ | |
655 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
656 | ||
657 | /* The argument pointer always points to the first argument. */ | |
658 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
659 | ||
660 | #define REG_PARM_STACK_SPACE(FNDECL) 0 | |
661 | ||
662 | /* Define this if it is the responsibility of the caller to | |
663 | allocate the area reserved for arguments passed in registers. | |
664 | If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect | |
665 | of this macro is to determine whether the space is included in | |
666 | `crtl->outgoing_args_size'. */ | |
667 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
668 | ||
669 | #define STACK_BOUNDARY (TARGET_ABI_LP64 ? 128 : 64) | |
670 | ||
f57ff189 LC |
671 | /* This value controls how many pages we manually unroll the loop for when |
672 | generating stack clash probes. */ | |
673 | #define STACK_CLASH_MAX_UNROLL_PAGES 4 | |
674 | ||
62ec3b53 | 675 | /* Symbolic macros for the registers used to return integer and floating |
676 | point values. */ | |
677 | ||
678 | #define GP_RETURN (GP_REG_FIRST + 4) | |
679 | #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) | |
680 | ||
681 | #define MAX_ARGS_IN_REGISTERS 8 | |
682 | ||
683 | /* Symbolic macros for the first/last argument registers. */ | |
684 | ||
685 | #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
686 | #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
687 | #define FP_ARG_FIRST (FP_REG_FIRST + 0) | |
688 | #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) | |
689 | ||
690 | /* 1 if N is a possible register number for function argument passing. | |
691 | We have no FP argument registers when soft-float. */ | |
692 | ||
693 | /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI. */ | |
694 | #define FUNCTION_ARG_REGNO_P(N) \ | |
695 | (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST) \ | |
696 | || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST))) | |
697 | ||
698 | typedef struct { | |
699 | /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */ | |
700 | unsigned int num_gprs; | |
701 | ||
702 | /* Number of floating-point registers used so far, likewise. */ | |
703 | unsigned int num_fprs; | |
704 | ||
705 | } CUMULATIVE_ARGS; | |
706 | ||
707 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
708 | for a call to a function whose data type is FNTYPE. | |
709 | For a library call, FNTYPE is 0. */ | |
710 | ||
711 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ | |
712 | memset (&(CUM), 0, sizeof (CUM)) | |
713 | ||
714 | #define EPILOGUE_USES(REGNO) loongarch_epilogue_uses (REGNO) | |
715 | ||
716 | /* Treat LOC as a byte offset from the stack pointer and round it up | |
717 | to the next fully-aligned offset. */ | |
718 | #define LARCH_STACK_ALIGN(LOC) \ | |
719 | (TARGET_ABI_LP64 ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8)) | |
720 | ||
721 | #define MCOUNT_NAME "_mcount" | |
722 | ||
723 | /* Emit rtl for profiling. Output assembler code to FILE | |
724 | to call "_mcount" for profiling a function entry. */ | |
725 | #define PROFILE_HOOK(LABEL) \ | |
726 | { \ | |
727 | rtx fun, ra; \ | |
728 | ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); \ | |
729 | fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ | |
730 | emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \ | |
731 | } | |
732 | ||
733 | /* All the work done in PROFILE_HOOK, but still required. */ | |
734 | #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) | |
735 | ||
736 | #define NO_PROFILE_COUNTERS 1 | |
737 | ||
738 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
739 | the stack pointer does not matter. The value is tested only in | |
740 | functions that have frame pointers. | |
741 | No definition is equivalent to always zero. */ | |
742 | ||
743 | #define EXIT_IGNORE_STACK 1 | |
744 | ||
745 | /* Trampolines are a block of code followed by two pointers. */ | |
746 | ||
747 | #define TRAMPOLINE_CODE_SIZE 16 | |
748 | #define TRAMPOLINE_SIZE \ | |
749 | ((Pmode == SImode) ? TRAMPOLINE_CODE_SIZE \ | |
750 | : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2)) | |
751 | #define TRAMPOLINE_ALIGNMENT POINTER_SIZE | |
752 | ||
753 | /* loongarch_trampoline_init calls this library function to flush | |
754 | program and data caches. */ | |
755 | ||
756 | #ifndef CACHE_FLUSH_FUNC | |
757 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
758 | #endif | |
759 | ||
760 | /* Addressing modes, and classification of registers for them. */ | |
761 | ||
762 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
763 | loongarch_regno_mode_ok_for_base_p (REGNO, VOIDmode, 1) | |
764 | ||
765 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
766 | loongarch_regno_mode_ok_for_base_p (REGNO, MODE, 1) | |
767 | ||
768 | /* Maximum number of registers that can appear in a valid memory address. */ | |
769 | ||
770 | #define MAX_REGS_PER_ADDRESS 2 | |
771 | ||
772 | /* Check for constness inline but use loongarch_legitimate_address_p | |
773 | to check whether a constant really is an address. */ | |
774 | ||
775 | #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && memory_address_p (SImode, X)) | |
776 | ||
777 | /* This handles the magic '..CURRENT_FUNCTION' symbol, which means | |
778 | 'the start of the function that this code is output in'. */ | |
779 | ||
780 | #define ASM_OUTPUT_LABELREF(FILE, NAME) \ | |
781 | do \ | |
782 | { \ | |
783 | if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
784 | asm_fprintf ((FILE), "%U%s", \ | |
785 | XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \ | |
786 | else \ | |
787 | asm_fprintf ((FILE), "%U%s", (NAME)); \ | |
788 | } \ | |
789 | while (0) | |
790 | ||
791 | #define CASE_VECTOR_MODE Pmode | |
792 | ||
793 | #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) Pmode | |
794 | ||
795 | /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
796 | #ifndef DEFAULT_SIGNED_CHAR | |
797 | #define DEFAULT_SIGNED_CHAR 1 | |
798 | #endif | |
799 | ||
800 | /* The SPARC port says: | |
801 | The maximum number of bytes that a single instruction | |
802 | can move quickly between memory and registers or between | |
803 | two memory locations. */ | |
804 | #define MOVE_MAX UNITS_PER_WORD | |
805 | #define MAX_MOVE_MAX 8 | |
806 | ||
807 | /* The SPARC port says: | |
808 | Nonzero if access to memory by bytes is slow and undesirable. | |
809 | For RISC chips, it means that access to memory by bytes is no | |
810 | better than access by words when possible, so grab a whole word | |
811 | and maybe make use of that. */ | |
812 | #define SLOW_BYTE_ACCESS 1 | |
813 | ||
814 | /* Standard LoongArch integer shifts truncate the shift amount to the | |
815 | width of the shifted operand. */ | |
816 | #define SHIFT_COUNT_TRUNCATED 1 | |
817 | ||
818 | /* Specify the machine mode that pointers have. | |
819 | After generation of rtl, the compiler makes no further distinction | |
820 | between pointers and any other objects of this machine mode. */ | |
821 | ||
822 | #ifndef Pmode | |
823 | #define Pmode (TARGET_64BIT ? DImode : SImode) | |
824 | #endif | |
825 | ||
826 | /* Give call MEMs SImode since it is the "most permissive" mode | |
827 | for both 32-bit and 64-bit targets. */ | |
828 | ||
829 | #define FUNCTION_MODE SImode | |
830 | ||
831 | /* We allocate $fcc registers by hand and can't cope with moves of | |
832 | CCmode registers to and from pseudos (or memory). */ | |
833 | #define AVOID_CCMODE_COPIES | |
834 | ||
835 | /* A C expression for the cost of a branch instruction. A value of | |
836 | 1 is the default; other values are interpreted relative to that. */ | |
837 | ||
838 | #define BRANCH_COST(speed_p, predictable_p) loongarch_branch_cost | |
839 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
840 | ||
841 | /* Return the asm template for a conditional branch instruction. | |
842 | OPCODE is the opcode's mnemonic and OPERANDS is the asm template for | |
843 | its operands. */ | |
844 | #define LARCH_BRANCH(OPCODE, OPERANDS) OPCODE "\t" OPERANDS | |
845 | ||
846 | /* Control the assembler format that we output. */ | |
847 | ||
848 | /* Output to assembler file text saying following lines | |
849 | may contain character constants, extra white space, comments, etc. */ | |
850 | ||
851 | #ifndef ASM_APP_ON | |
852 | #define ASM_APP_ON " #APP\n" | |
853 | #endif | |
854 | ||
855 | /* Output to assembler file text saying following lines | |
856 | no longer contain unusual constructs. */ | |
857 | ||
858 | #ifndef ASM_APP_OFF | |
859 | #define ASM_APP_OFF " #NO_APP\n" | |
860 | #endif | |
861 | ||
862 | #define REGISTER_NAMES \ | |
863 | { "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \ | |
864 | "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$r15", \ | |
865 | "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \ | |
866 | "$r24", "$r25", "$r26", "$r27", "$r28", "$r29", "$r30", "$r31", \ | |
867 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ | |
868 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
869 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ | |
870 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ | |
871 | "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4","$fcc5","$fcc6","$fcc7", \ | |
872 | "$arg", "$frame"} | |
873 | ||
874 | /* This macro defines additional names for hard registers. */ | |
875 | ||
876 | #define ADDITIONAL_REGISTER_NAMES \ | |
877 | { \ | |
878 | { "zero", 0 + GP_REG_FIRST }, \ | |
879 | { "ra", 1 + GP_REG_FIRST }, \ | |
880 | { "tp", 2 + GP_REG_FIRST }, \ | |
881 | { "sp", 3 + GP_REG_FIRST }, \ | |
882 | { "a0", 4 + GP_REG_FIRST }, \ | |
883 | { "a1", 5 + GP_REG_FIRST }, \ | |
884 | { "a2", 6 + GP_REG_FIRST }, \ | |
885 | { "a3", 7 + GP_REG_FIRST }, \ | |
886 | { "a4", 8 + GP_REG_FIRST }, \ | |
887 | { "a5", 9 + GP_REG_FIRST }, \ | |
888 | { "a6", 10 + GP_REG_FIRST }, \ | |
889 | { "a7", 11 + GP_REG_FIRST }, \ | |
890 | { "t0", 12 + GP_REG_FIRST }, \ | |
891 | { "t1", 13 + GP_REG_FIRST }, \ | |
892 | { "t2", 14 + GP_REG_FIRST }, \ | |
893 | { "t3", 15 + GP_REG_FIRST }, \ | |
894 | { "t4", 16 + GP_REG_FIRST }, \ | |
895 | { "t5", 17 + GP_REG_FIRST }, \ | |
896 | { "t6", 18 + GP_REG_FIRST }, \ | |
897 | { "t7", 19 + GP_REG_FIRST }, \ | |
898 | { "t8", 20 + GP_REG_FIRST }, \ | |
899 | { "x", 21 + GP_REG_FIRST }, \ | |
900 | { "fp", 22 + GP_REG_FIRST }, \ | |
901 | { "s0", 23 + GP_REG_FIRST }, \ | |
902 | { "s1", 24 + GP_REG_FIRST }, \ | |
903 | { "s2", 25 + GP_REG_FIRST }, \ | |
904 | { "s3", 26 + GP_REG_FIRST }, \ | |
905 | { "s4", 27 + GP_REG_FIRST }, \ | |
906 | { "s5", 28 + GP_REG_FIRST }, \ | |
907 | { "s6", 29 + GP_REG_FIRST }, \ | |
908 | { "s7", 30 + GP_REG_FIRST }, \ | |
909 | { "s8", 31 + GP_REG_FIRST }, \ | |
910 | { "v0", 4 + GP_REG_FIRST }, \ | |
911 | { "v1", 5 + GP_REG_FIRST } \ | |
912 | } | |
913 | ||
914 | /* Globalizing directive for a label. */ | |
915 | #define GLOBAL_ASM_OP "\t.globl\t" | |
916 | ||
917 | /* This says how to output an external. It would be possible not to | |
918 | output anything and let undefined symbol become external. However | |
919 | the assembler uses length information on externals to allocate in | |
920 | data/sdata bss/sbss, thereby saving exec time. */ | |
921 | ||
922 | #undef ASM_OUTPUT_EXTERNAL | |
923 | #define ASM_OUTPUT_EXTERNAL(STREAM, DECL, NAME) \ | |
924 | loongarch_output_external (STREAM, DECL, NAME) | |
925 | ||
926 | /* This is how to store into the string LABEL | |
927 | the symbol_ref name of an internal numbered label where | |
928 | PREFIX is the class of label and NUM is the number within the class. | |
929 | This is suitable for output with `assemble_name'. */ | |
930 | ||
931 | #undef ASM_GENERATE_INTERNAL_LABEL | |
932 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ | |
933 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long) (NUM)) | |
934 | ||
935 | /* Print debug labels as "foo = ." rather than "foo:" because they should | |
936 | represent a byte pointer rather than an ISA-encoded address. This is | |
937 | particularly important for code like: | |
938 | ||
939 | $LFBxxx = . | |
940 | .cfi_startproc | |
941 | ... | |
942 | .section .gcc_except_table,... | |
943 | ... | |
944 | .uleb128 foo-$LFBxxx | |
945 | ||
946 | The .uleb128 requies $LFBxxx to match the FDE start address, which is | |
947 | likewise a byte pointer rather than an ISA-encoded address. | |
948 | ||
949 | At the time of writing, this hook is not used for the function end | |
950 | label: | |
951 | ||
952 | $LFExxx: | |
953 | .end foo | |
954 | ||
955 | */ | |
956 | ||
957 | #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ | |
958 | fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) | |
959 | ||
960 | /* This is how to output an element of a case-vector that is absolute. */ | |
961 | ||
962 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
963 | fprintf (STREAM, "\t%s\t%sL%d\n", ptr_mode == DImode ? ".dword" : ".word", \ | |
964 | LOCAL_LABEL_PREFIX, VALUE) | |
965 | ||
966 | /* This is how to output an element of a case-vector. */ | |
967 | ||
968 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ | |
969 | do \ | |
970 | { \ | |
971 | fprintf (STREAM, "\t%s\t%sL%d-%sL%d\n", \ | |
972 | ptr_mode == DImode ? ".dword" : ".word", LOCAL_LABEL_PREFIX, \ | |
973 | VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
974 | } \ | |
975 | while (0) | |
976 | ||
977 | #define JUMP_TABLES_IN_TEXT_SECTION 0 | |
978 | ||
979 | /* This is how to output an assembler line | |
980 | that says to advance the location counter | |
981 | to a multiple of 2**LOG bytes. */ | |
982 | ||
983 | #define ASM_OUTPUT_ALIGN(STREAM, LOG) fprintf (STREAM, "\t.align\t%d\n", (LOG)) | |
984 | ||
985 | /* "nop" instruction 54525952 (andi $r0,$r0,0) is | |
986 | used for padding. */ | |
987 | #define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, LOG) \ | |
988 | fprintf (STREAM, "\t.align\t%d,54525952,4\n", (LOG)) | |
989 | ||
990 | /* This is how to output an assembler line to advance the location | |
991 | counter by SIZE bytes. */ | |
992 | ||
993 | #undef ASM_OUTPUT_SKIP | |
994 | #define ASM_OUTPUT_SKIP(STREAM, SIZE) \ | |
995 | fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", (SIZE)) | |
996 | ||
997 | /* This is how to output a string. */ | |
998 | #undef ASM_OUTPUT_ASCII | |
999 | #define ASM_OUTPUT_ASCII loongarch_output_ascii | |
1000 | ||
1001 | /* Define the strings to put out for each section in the object file. */ | |
1002 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
1003 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
1004 | ||
1005 | #undef READONLY_DATA_SECTION_ASM_OP | |
1006 | #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata" /* read-only data */ | |
1007 | ||
1008 | #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ | |
1009 | do \ | |
1010 | { \ | |
1011 | fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,%s,0\n", \ | |
1012 | TARGET_64BIT ? "addi.d" : "addi.w", \ | |
1013 | reg_names[STACK_POINTER_REGNUM], \ | |
1014 | reg_names[STACK_POINTER_REGNUM], \ | |
1015 | TARGET_64BIT ? "st.d" : "st.w", reg_names[REGNO], \ | |
1016 | reg_names[STACK_POINTER_REGNUM]); \ | |
1017 | } \ | |
1018 | while (0) | |
1019 | ||
1020 | #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ | |
1021 | do \ | |
1022 | { \ | |
1023 | fprintf (STREAM, "\t%s\t%s,%s,0\n\t%s\t%s,%s,8\n", \ | |
1024 | TARGET_64BIT ? "ld.d" : "ld.w", reg_names[REGNO], \ | |
1025 | reg_names[STACK_POINTER_REGNUM], \ | |
1026 | TARGET_64BIT ? "addi.d" : "addi.w", \ | |
1027 | reg_names[STACK_POINTER_REGNUM], \ | |
1028 | reg_names[STACK_POINTER_REGNUM]); \ | |
1029 | } \ | |
1030 | while (0) | |
1031 | ||
1032 | /* How to start an assembler comment. | |
1033 | The leading space is important (the loongarch native assembler requires it). | |
1034 | */ | |
1035 | #ifndef ASM_COMMENT_START | |
1036 | #define ASM_COMMENT_START " #" | |
1037 | #endif | |
1038 | ||
1039 | #undef SIZE_TYPE | |
1040 | #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") | |
1041 | ||
1042 | #undef PTRDIFF_TYPE | |
1043 | #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") | |
1044 | ||
1045 | /* The maximum number of bytes that can be copied by one iteration of | |
1046 | a cpymemsi loop; see loongarch_block_move_loop. */ | |
1047 | #define LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4) | |
1048 | ||
1049 | /* The maximum number of bytes that can be copied by a straight-line | |
1050 | implementation of cpymemsi; see loongarch_block_move_straight. We want | |
1051 | to make sure that any loop-based implementation will iterate at | |
1052 | least twice. */ | |
1053 | #define LARCH_MAX_MOVE_BYTES_STRAIGHT (LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) | |
1054 | ||
1055 | /* The base cost of a memcpy call, for MOVE_RATIO and friends. These | |
1056 | values were determined experimentally by benchmarking with CSiBE. | |
1057 | */ | |
1058 | #define LARCH_CALL_RATIO 8 | |
1059 | ||
1060 | /* Any loop-based implementation of cpymemsi will have at least | |
1061 | LARCH_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory | |
1062 | moves, so allow individual copies of fewer elements. | |
1063 | ||
1064 | When cpymemsi is not available, use a value approximating | |
1065 | the length of a memcpy call sequence, so that move_by_pieces | |
1066 | will generate inline code if it is shorter than a function call. | |
1067 | Since move_by_pieces_ninsns counts memory-to-memory moves, but | |
1068 | we'll have to generate a load/store pair for each, halve the | |
1069 | value of LARCH_CALL_RATIO to take that into account. */ | |
1070 | ||
1071 | #define MOVE_RATIO(speed) \ | |
1072 | (HAVE_cpymemsi \ | |
1073 | ? LARCH_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD \ | |
1074 | : CLEAR_RATIO (speed) / 2) | |
1075 | ||
1076 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate | |
1077 | of the length of a memset call, but use the default otherwise. */ | |
1078 | ||
1079 | #define CLEAR_RATIO(speed) ((speed) ? 15 : LARCH_CALL_RATIO) | |
1080 | ||
1081 | /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
1082 | optimizing for size adjust the ratio to account for the overhead of | |
1083 | loading the constant and replicating it across the word. */ | |
1084 | ||
1085 | #define SET_RATIO(speed) ((speed) ? 15 : LARCH_CALL_RATIO - 2) | |
1086 | ||
1087 | #ifndef USED_FOR_TARGET | |
1088 | extern const enum reg_class loongarch_regno_to_class[]; | |
1089 | extern int loongarch_dwarf_regno[]; | |
1090 | ||
1091 | /* Information about a function's frame layout. */ | |
1092 | struct GTY (()) loongarch_frame_info | |
1093 | { | |
1094 | /* The size of the frame in bytes. */ | |
1095 | HOST_WIDE_INT total_size; | |
1096 | ||
1097 | /* Bit X is set if the function saves or restores GPR X. */ | |
1098 | unsigned int mask; | |
1099 | ||
1100 | /* Likewise FPR X. */ | |
1101 | unsigned int fmask; | |
1102 | ||
1103 | /* How much the GPR save/restore routines adjust sp (or 0 if unused). */ | |
1104 | unsigned save_libcall_adjustment; | |
1105 | ||
1106 | /* Offsets of fixed-point and floating-point save areas from frame | |
1107 | bottom. */ | |
1108 | HOST_WIDE_INT gp_sp_offset; | |
1109 | HOST_WIDE_INT fp_sp_offset; | |
1110 | ||
1111 | /* Offset of virtual frame pointer from stack pointer/frame bottom. */ | |
1112 | HOST_WIDE_INT frame_pointer_offset; | |
1113 | ||
1114 | /* Offset of hard frame pointer from stack pointer/frame bottom. */ | |
1115 | HOST_WIDE_INT hard_frame_pointer_offset; | |
1116 | ||
1117 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ | |
1118 | HOST_WIDE_INT arg_pointer_offset; | |
1119 | }; | |
1120 | ||
1121 | struct GTY (()) machine_function | |
1122 | { | |
1123 | /* The next floating-point condition-code register to allocate | |
1124 | for 8CC targets, relative to FCC_REG_FIRST. */ | |
1125 | unsigned int next_fcc; | |
1126 | ||
1127 | /* The number of extra stack bytes taken up by register varargs. | |
1128 | This area is allocated by the callee at the very top of the frame. */ | |
1129 | int varargs_size; | |
1130 | ||
1131 | /* The current frame information, calculated by loongarch_compute_frame_info. | |
1132 | */ | |
1133 | struct loongarch_frame_info frame; | |
1134 | }; | |
1135 | #endif | |
1136 | ||
201e8d9f LC |
1137 | #ifdef HAVE_AS_EH_FRAME_PCREL_ENCODING_SUPPORT |
1138 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
1139 | (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) | |
1140 | #else | |
62ec3b53 | 1141 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ |
1142 | (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) | |
201e8d9f | 1143 | #endif |
62ec3b53 | 1144 | |
1145 | /* Do emit .note.GNU-stack by default. */ | |
1146 | #ifndef NEED_INDICATE_EXEC_STACK | |
1147 | #define NEED_INDICATE_EXEC_STACK 1 | |
1148 | #endif | |
1149 | ||
1150 | /* The `Q' extension is not yet supported. */ | |
1151 | /* TODO: according to march. */ | |
1152 | #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4) | |
1153 | ||
1154 | /* The largest type that can be passed in floating-point registers. */ | |
1155 | /* TODO: according to mabi. */ | |
1156 | #define UNITS_PER_FP_ARG \ | |
1157 | (TARGET_HARD_FLOAT ? (TARGET_DOUBLE_FLOAT ? 8 : 4) : 0) | |
1158 | ||
1159 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN) |