[thirdparty/gcc.git] / gcc / config / nds32 / constraints.md

;; Constraint definitions of Andes NDS32 cpu for GNU compiler
;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
;; Contributed by Andes Technology Corporation.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.
;;
;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;; Check 16.8.7 Defining Machine-Specific Constraints for detail.

;; NO contrains can be prefixed with: E F V X g i m n o p r s
;; Machine-dependent integer: I J K L M N O P
;; Machine-dependent floating: G H


(define_register_constraint "w" "(TARGET_ISA_V3 || TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
  "LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")

(define_register_constraint "l" "LOW_REGS"
  "LOW register class $r0 ~ $r7")

(define_register_constraint "d" "MIDDLE_REGS"
  "MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")

(define_register_constraint "h" "HIGH_REGS"
  "HIGH register class $r12 ~ $r14, $r20 ~ $r31")


(define_register_constraint "t" "R15_TA_REG"
  "Temporary Assist register $ta (i.e. $r15)")

(define_register_constraint "e" "R8_REG"
  "Function Entry register $r8)")

(define_register_constraint "k" "STACK_REG"
  "Stack register $sp")

(define_register_constraint "v" "R5_REG"
  "Register $r5")

(define_register_constraint "x" "FRAME_POINTER_REG"
  "Frame pointer register $fp")

(define_register_constraint "f"
  "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) ? FP_REGS : NO_REGS"
 "The Floating point registers $fs0 ~ $fs31")

(define_constraint "Iv00"
  "Constant value 0"
  (and (match_code "const_int")
       (match_test "ival == 0")))

(define_constraint "Iv01"
  "Constant value 1"
  (and (match_code "const_int")
       (match_test "ival == 1")))

(define_constraint "Iv02"
  "Constant value 2"
  (and (match_code "const_int")
       (match_test "ival == 2")))

(define_constraint "Iv04"
  "Constant value 4"
  (and (match_code "const_int")
       (match_test "ival == 4")))

(define_constraint "Iv08"
  "Constant value 8"
  (and (match_code "const_int")
       (match_test "ival == 8")))

(define_constraint "Iu01"
  "Unsigned immediate 1-bit value"
  (and (match_code "const_int")
       (match_test "ival == 1 || ival == 0")))

(define_constraint "Iu02"
  "Unsigned immediate 2-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 2) && ival >= 0")))

(define_constraint "Iu03"
  "Unsigned immediate 3-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 3) && ival >= 0")))

(define_constraint "In03"
  "Negative immediate 3-bit value in the range of -7 to 0"
  (and (match_code "const_int")
       (match_test "IN_RANGE (ival, -7, 0)")))

(define_constraint "Iu04"
  "Unsigned immediate 4-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 4) && ival >= 0")))

(define_constraint "Is05"
  "Signed immediate 5-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 4) && ival >= -(1 << 4)")))

(define_constraint "Cs05"
  "Signed immediate 5-bit value"
  (and (match_code "const_double")
       (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 4), (1 << 4))")))

(define_constraint "Iu05"
  "Unsigned immediate 5-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 5) && ival >= 0")))

(define_constraint "In05"
  "Negative immediate 5-bit value in the range of -31 to 0"
  (and (match_code "const_int")
       (match_test "IN_RANGE (ival, -31, 0)")))

(define_constraint "Iu06"
  "Unsigned immediate 6-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 6) && ival >= 0")))

;; Ip05 is special and dedicated for v3 movpi45 instruction.
;; movpi45 has imm5u field but the range is 16 ~ 47.
(define_constraint "Ip05"
  "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
  (and (match_code "const_int")
       (match_test "ival < ((1 << 5) + 16)
		    && ival >= (0 + 16)
		    && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))

(define_constraint "IU06"
  "Unsigned immediate 6-bit value constraint for addri36.sp instruction"
  (and (match_code "const_int")
       (match_test "ival < (1 << 8)
		    && ival >= 0
		    && (ival % 4 == 0)
		    && (TARGET_ISA_V3 || TARGET_ISA_V3M)")))

(define_constraint "Iu08"
  "Unsigned immediate 8-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 8) && ival >= 0")))

(define_constraint "Iu09"
  "Unsigned immediate 9-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 9) && ival >= 0")))


(define_constraint "Is08"
  "Signed immediate 8-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 7) && ival >= -(1 << 7)")))

(define_constraint "Is10"
  "Signed immediate 10-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 9) && ival >= -(1 << 9)")))

(define_constraint "Is11"
  "Signed immediate 11-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 10) && ival >= -(1 << 10)")))

(define_constraint "Is14"
  "Signed immediate 14-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 13) && ival >= -(1 << 13)")))

(define_constraint "Is15"
  "Signed immediate 15-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 14) && ival >= -(1 << 14)")))

(define_constraint "Iu15"
  "Unsigned immediate 15-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 15) && ival >= 0")))


;; Ic15 is special and dedicated for performance extension
;; 'bclr' (single-bit-clear) instruction.
;; It is used in andsi3 pattern and recognized for the immediate
;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
;; (If the immediate value IS in the range of imm15u,
;;  we can directly use 'andi' instruction.)
(define_constraint "Ic15"
  "A constant which is not in the range of imm15u but ok for bclr instruction"
  (and (match_code "const_int")
       (match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))

;; Ie15 is special and dedicated for performance extension
;; 'bset' (single-bit-set) instruction.
;; It is used in iorsi3 pattern and recognized for the immediate
;; which is NOT in the range of imm15u but OK for 'bset' instruction.
;; (If the immediate value IS in the range of imm15u,
;;  we can directly use 'ori' instruction.)
(define_constraint "Ie15"
  "A constant which is not in the range of imm15u but ok for bset instruction"
  (and (match_code "const_int")
       (match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))

;; It15 is special and dedicated for performance extension
;; 'btgl' (single-bit-toggle) instruction.
;; It is used in xorsi3 pattern and recognized for the immediate
;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
;; (If the immediate value IS in the range of imm15u,
;;  we can directly use 'xori' instruction.)
(define_constraint "It15"
  "A constant which is not in the range of imm15u but ok for btgl instruction"
  (and (match_code "const_int")
       (match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))


;; Ii15 is special and dedicated for v3 isa
;; 'bitci' (bit-clear-immediate) instruction.
;; It is used in andsi3 pattern and recognized for the immediate whose
;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
;  with 'bitci $r0,$r0,3'.
(define_constraint "Ii15"
  "A constant whose compliment value is in the range of imm15u
   and ok for bitci instruction"
  (and (match_code "const_int")
       (match_test "nds32_can_use_bitci_p (ival)")))


(define_constraint "Is16"
  "Signed immediate 16-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 15) && ival >= -(1 << 15)")))

(define_constraint "Is17"
  "Signed immediate 17-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 16) && ival >= -(1 << 16)")))


(define_constraint "Is19"
  "Signed immediate 19-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 18) && ival >= -(1 << 18)")))


(define_constraint "Is20"
  "Signed immediate 20-bit value"
  (and (match_code "const_int")
       (match_test "ival < (1 << 19) && ival >= -(1 << 19)")))

(define_constraint "Cs20"
  "Signed immediate 20-bit value"
  (and (match_code "const_double")
       (match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 19), (1 << 19))")))

(define_constraint "Ihig"
  "The immediate value that can be simply set high 20-bit"
  (and (match_code "const_int")
       (match_test "(ival != 0) && ((ival & 0xfff) == 0)")))

(define_constraint "Chig"
  "The immediate value that can be simply set high 20-bit"
  (and (match_code "high")
       (match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))

(define_constraint "Izeb"
  "The immediate value 0xff"
  (and (match_code "const_int")
       (match_test "(ival == 0xff)")))

(define_constraint "Izeh"
  "The immediate value 0xffff"
  (and (match_code "const_int")
       (match_test "(ival == 0xffff)")))

(define_constraint "Ixls"
  "The immediate value 0x01"
  (and (match_code "const_int")
       (match_test "TARGET_EXT_PERF && (ival == 0x1)")))

(define_constraint "Ix11"
  "The immediate value 0x7ff"
  (and (match_code "const_int")
       (match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))

(define_constraint "Ibms"
  "The immediate value with power of 2"
  (and (match_code "const_int")
       (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
		    && (IN_RANGE (exact_log2 (ival), 0, 7))")))

(define_constraint "Ifex"
  "The immediate value with power of 2 minus 1"
  (and (match_code "const_int")
       (match_test "(TARGET_ISA_V3 || TARGET_ISA_V3M)
		    && (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))

(define_constraint "CVp5"
  "Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
  (and (match_code "const_vector")
       (match_test "nds32_valid_CVp5_p (op)")))

(define_constraint "CVs5"
  "Signed immediate 5-bit value"
  (and (match_code "const_vector")
       (match_test "nds32_valid_CVs5_p (op)")))

(define_constraint "CVs2"
  "Signed immediate 20-bit value"
  (and (match_code "const_vector")
       (match_test "nds32_valid_CVs2_p (op)")))

(define_constraint "CVhi"
  "The immediate value that can be simply set high 20-bit"
  (and (match_code "const_vector")
       (match_test "nds32_valid_CVhi_p (op)")))

(define_memory_constraint "U33"
  "Memory constraint for 333 format"
  (and (match_code "mem")
       (match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
		    || nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
		    || nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))

(define_memory_constraint "U45"
  "Memory constraint for 45 format"
  (and (match_code "mem")
       (match_test "(nds32_mem_format (op) == ADDRESS_REG)
		    && ((GET_MODE (op) == SImode)
		       || (GET_MODE (op) == SFmode))")))

(define_memory_constraint "Ufe"
  "Memory constraint for fe format"
  (and (match_code "mem")
       (match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
		    && (GET_MODE (op) == SImode
			|| GET_MODE (op) == SFmode)")))

(define_memory_constraint "U37"
  "Memory constraint for 37 format"
  (and (match_code "mem")
       (match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
		    || nds32_mem_format (op) == ADDRESS_FP_IMM7U)
		    && (GET_MODE (op) == SImode
			|| GET_MODE (op) == SFmode)")))

(define_memory_constraint "Umw"
  "Memory constraint for lwm/smw"
  (and (match_code "mem")
       (match_test "nds32_valid_smw_lwm_base_p (op)")))

(define_memory_constraint "Da"
  "Memory constraint for non-offset loads/stores"
  (and (match_code "mem")
       (match_test "REG_P (XEXP (op, 0))
		    || (GET_CODE (XEXP (op, 0)) == POST_INC)")))

(define_memory_constraint "Q"
  "Memory constraint for no symbol_ref and const"
  (and (match_code "mem")
       (match_test "(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)
		     && nds32_float_mem_operand_p (op)")))

(define_constraint "S"
  "@internal
   A constant call address."
  (match_operand 0 "nds32_symbolic_operand"))

;; ------------------------------------------------------------------------
Commit	Line	Data
9304f876	1	;; Constraint definitions of Andes NDS32 cpu for GNU compiler
a945c346	2	;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
9304f876 CJW	3	;; Contributed by Andes Technology Corporation.
	4	;;
	5	;; This file is part of GCC.
	6	;;
	7	;; GCC is free software; you can redistribute it and/or modify it
	8	;; under the terms of the GNU General Public License as published
	9	;; by the Free Software Foundation; either version 3, or (at your
	10	;; option) any later version.
	11	;;
	12	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	13	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	14	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	15	;; License for more details.
	16	;;
	17	;; You should have received a copy of the GNU General Public License
	18	;; along with GCC; see the file COPYING3. If not see
	19	;; <http://www.gnu.org/licenses/>.
	20
	21	;; Check 16.8.7 Defining Machine-Specific Constraints for detail.
	22
	23	;; NO contrains can be prefixed with: E F V X g i m n o p r s
	24	;; Machine-dependent integer: I J K L M N O P
	25	;; Machine-dependent floating: G H
	26
	27
	28	(define_register_constraint "w" "(TARGET_ISA_V3 \|\| TARGET_ISA_V3M) ? LOW_REGS : NO_REGS"
	29	"LOW register class $r0 ~ $r7 constraint for V3/V3M ISA")
	30
	31	(define_register_constraint "l" "LOW_REGS"
	32	"LOW register class $r0 ~ $r7")
	33
	34	(define_register_constraint "d" "MIDDLE_REGS"
	35	"MIDDLE register class $r0 ~ $r11, $r16 ~ $r19")
	36
	37	(define_register_constraint "h" "HIGH_REGS"
	38	"HIGH register class $r12 ~ $r14, $r20 ~ $r31")
	39
	40
	41	(define_register_constraint "t" "R15_TA_REG"
	42	"Temporary Assist register $ta (i.e. $r15)")
	43
36f28760 CJW	44	(define_register_constraint "e" "R8_REG"
	45	"Function Entry register $r8)")
	46
9304f876 CJW	47	(define_register_constraint "k" "STACK_REG"
	48	"Stack register $sp")
	49
36f28760 CJW	50	(define_register_constraint "v" "R5_REG"
	51	"Register $r5")
	52
	53	(define_register_constraint "x" "FRAME_POINTER_REG"
	54	"Frame pointer register $fp")
	55
e2286268 MC	56	(define_register_constraint "f"
	57	"(TARGET_FPU_SINGLE \|\| TARGET_FPU_DOUBLE) ? FP_REGS : NO_REGS"
	58	"The Floating point registers $fs0 ~ $fs31")
	59
36f28760 CJW	60	(define_constraint "Iv00"
	61	"Constant value 0"
	62	(and (match_code "const_int")
	63	(match_test "ival == 0")))
	64
	65	(define_constraint "Iv01"
	66	"Constant value 1"
	67	(and (match_code "const_int")
	68	(match_test "ival == 1")))
	69
	70	(define_constraint "Iv02"
	71	"Constant value 2"
	72	(and (match_code "const_int")
	73	(match_test "ival == 2")))
	74
	75	(define_constraint "Iv04"
	76	"Constant value 4"
	77	(and (match_code "const_int")
	78	(match_test "ival == 4")))
	79
	80	(define_constraint "Iv08"
	81	"Constant value 8"
	82	(and (match_code "const_int")
	83	(match_test "ival == 8")))
	84
	85	(define_constraint "Iu01"
	86	"Unsigned immediate 1-bit value"
	87	(and (match_code "const_int")
	88	(match_test "ival == 1 \|\| ival == 0")))
	89
	90	(define_constraint "Iu02"
	91	"Unsigned immediate 2-bit value"
	92	(and (match_code "const_int")
	93	(match_test "ival < (1 << 2) && ival >= 0")))
9304f876 CJW	94
	95	(define_constraint "Iu03"
	96	"Unsigned immediate 3-bit value"
	97	(and (match_code "const_int")
	98	(match_test "ival < (1 << 3) && ival >= 0")))
	99
	100	(define_constraint "In03"
	101	"Negative immediate 3-bit value in the range of -7 to 0"
	102	(and (match_code "const_int")
	103	(match_test "IN_RANGE (ival, -7, 0)")))
	104
	105	(define_constraint "Iu04"
	106	"Unsigned immediate 4-bit value"
	107	(and (match_code "const_int")
	108	(match_test "ival < (1 << 4) && ival >= 0")))
	109
	110	(define_constraint "Is05"
	111	"Signed immediate 5-bit value"
	112	(and (match_code "const_int")
	113	(match_test "ival < (1 << 4) && ival >= -(1 << 4)")))
	114
e2286268 MC	115	(define_constraint "Cs05"
	116	"Signed immediate 5-bit value"
	117	(and (match_code "const_double")
	118	(match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 4), (1 << 4))")))
	119
9304f876 CJW	120	(define_constraint "Iu05"
	121	"Unsigned immediate 5-bit value"
	122	(and (match_code "const_int")
	123	(match_test "ival < (1 << 5) && ival >= 0")))
	124
	125	(define_constraint "In05"
	126	"Negative immediate 5-bit value in the range of -31 to 0"
	127	(and (match_code "const_int")
	128	(match_test "IN_RANGE (ival, -31, 0)")))
	129
7c32ef41 MC	130	(define_constraint "Iu06"
	131	"Unsigned immediate 6-bit value"
	132	(and (match_code "const_int")
	133	(match_test "ival < (1 << 6) && ival >= 0")))
	134
9304f876 CJW	135	;; Ip05 is special and dedicated for v3 movpi45 instruction.
	136	;; movpi45 has imm5u field but the range is 16 ~ 47.
	137	(define_constraint "Ip05"
	138	"Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
	139	(and (match_code "const_int")
	140	(match_test "ival < ((1 << 5) + 16)
	141	&& ival >= (0 + 16)
	142	&& (TARGET_ISA_V3 \|\| TARGET_ISA_V3M)")))
	143
7c32ef41	144	(define_constraint "IU06"
9304f876 CJW	145	"Unsigned immediate 6-bit value constraint for addri36.sp instruction"
9304f876 CJW	146	(and (match_code "const_int")
7c32ef41	147	(match_test "ival < (1 << 8)
9304f876 CJW	148	&& ival >= 0
	149	&& (ival % 4 == 0)
	150	&& (TARGET_ISA_V3 \|\| TARGET_ISA_V3M)")))
	151
	152	(define_constraint "Iu08"
	153	"Unsigned immediate 8-bit value"
	154	(and (match_code "const_int")
	155	(match_test "ival < (1 << 8) && ival >= 0")))
	156
	157	(define_constraint "Iu09"
	158	"Unsigned immediate 9-bit value"
	159	(and (match_code "const_int")
	160	(match_test "ival < (1 << 9) && ival >= 0")))
	161
	162
36f28760 CJW	163	(define_constraint "Is08"
	164	"Signed immediate 8-bit value"
	165	(and (match_code "const_int")
	166	(match_test "ival < (1 << 7) && ival >= -(1 << 7)")))
	167
9304f876 CJW	168	(define_constraint "Is10"
	169	"Signed immediate 10-bit value"
	170	(and (match_code "const_int")
	171	(match_test "ival < (1 << 9) && ival >= -(1 << 9)")))
	172
	173	(define_constraint "Is11"
	174	"Signed immediate 11-bit value"
	175	(and (match_code "const_int")
	176	(match_test "ival < (1 << 10) && ival >= -(1 << 10)")))
	177
36f28760 CJW	178	(define_constraint "Is14"
	179	"Signed immediate 14-bit value"
	180	(and (match_code "const_int")
	181	(match_test "ival < (1 << 13) && ival >= -(1 << 13)")))
9304f876 CJW	182
	183	(define_constraint "Is15"
	184	"Signed immediate 15-bit value"
	185	(and (match_code "const_int")
	186	(match_test "ival < (1 << 14) && ival >= -(1 << 14)")))
	187
	188	(define_constraint "Iu15"
	189	"Unsigned immediate 15-bit value"
	190	(and (match_code "const_int")
	191	(match_test "ival < (1 << 15) && ival >= 0")))
	192
	193
	194	;; Ic15 is special and dedicated for performance extension
	195	;; 'bclr' (single-bit-clear) instruction.
	196	;; It is used in andsi3 pattern and recognized for the immediate
	197	;; which is NOT in the range of imm15u but OK for 'bclr' instruction.
	198	;; (If the immediate value IS in the range of imm15u,
	199	;; we can directly use 'andi' instruction.)
	200	(define_constraint "Ic15"
	201	"A constant which is not in the range of imm15u but ok for bclr instruction"
	202	(and (match_code "const_int")
	203	(match_test "(ival & 0xffff8000) && nds32_can_use_bclr_p (ival)")))
	204
	205	;; Ie15 is special and dedicated for performance extension
	206	;; 'bset' (single-bit-set) instruction.
	207	;; It is used in iorsi3 pattern and recognized for the immediate
	208	;; which is NOT in the range of imm15u but OK for 'bset' instruction.
	209	;; (If the immediate value IS in the range of imm15u,
	210	;; we can directly use 'ori' instruction.)
	211	(define_constraint "Ie15"
	212	"A constant which is not in the range of imm15u but ok for bset instruction"
	213	(and (match_code "const_int")
	214	(match_test "(ival & 0xffff8000) && nds32_can_use_bset_p (ival)")))
	215
	216	;; It15 is special and dedicated for performance extension
	217	;; 'btgl' (single-bit-toggle) instruction.
	218	;; It is used in xorsi3 pattern and recognized for the immediate
	219	;; which is NOT in the range of imm15u but OK for 'btgl' instruction.
	220	;; (If the immediate value IS in the range of imm15u,
	221	;; we can directly use 'xori' instruction.)
	222	(define_constraint "It15"
	223	"A constant which is not in the range of imm15u but ok for btgl instruction"
	224	(and (match_code "const_int")
	225	(match_test "(ival & 0xffff8000) && nds32_can_use_btgl_p (ival)")))
	226
	227
	228	;; Ii15 is special and dedicated for v3 isa
	229	;; 'bitci' (bit-clear-immediate) instruction.
	230	;; It is used in andsi3 pattern and recognized for the immediate whose
	231	;; (~ival) value is in the range of imm15u and OK for 'bitci' instruction.
	232	;; For example, 'andi $r0,$r0,0xfffffffc' can be presented
	233	; with 'bitci $r0,$r0,3'.
	234	(define_constraint "Ii15"
	235	"A constant whose compliment value is in the range of imm15u
	236	and ok for bitci instruction"
	237	(and (match_code "const_int")
	238	(match_test "nds32_can_use_bitci_p (ival)")))
	239
	240
	241	(define_constraint "Is16"
	242	"Signed immediate 16-bit value"
	243	(and (match_code "const_int")
	244	(match_test "ival < (1 << 15) && ival >= -(1 << 15)")))
	245
246	(define_constraint "Is17"
247	"Signed immediate 17-bit value"
248	(and (match_code "const_int")
249	(match_test "ival < (1 << 16) && ival >= -(1 << 16)")))
250
251
252	(define_constraint "Is19"
253	"Signed immediate 19-bit value"
254	(and (match_code "const_int")
255	(match_test "ival < (1 << 18) && ival >= -(1 << 18)")))
256
257
258	(define_constraint "Is20"
259	"Signed immediate 20-bit value"
260	(and (match_code "const_int")
261	(match_test "ival < (1 << 19) && ival >= -(1 << 19)")))
262
e2286268 MC	263	(define_constraint "Cs20"
	264	"Signed immediate 20-bit value"
	265	(and (match_code "const_double")
	266	(match_test "nds32_const_double_range_ok_p (op, SFmode, -(1 << 19), (1 << 19))")))
9304f876 CJW	267
	268	(define_constraint "Ihig"
	269	"The immediate value that can be simply set high 20-bit"
	270	(and (match_code "const_int")
	271	(match_test "(ival != 0) && ((ival & 0xfff) == 0)")))
	272
e2286268 MC	273	(define_constraint "Chig"
	274	"The immediate value that can be simply set high 20-bit"
	275	(and (match_code "high")
	276	(match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))
	277
9304f876 CJW	278	(define_constraint "Izeb"
	279	"The immediate value 0xff"
	280	(and (match_code "const_int")
	281	(match_test "(ival == 0xff)")))
	282
	283	(define_constraint "Izeh"
	284	"The immediate value 0xffff"
	285	(and (match_code "const_int")
	286	(match_test "(ival == 0xffff)")))
	287
	288	(define_constraint "Ixls"
	289	"The immediate value 0x01"
	290	(and (match_code "const_int")
aa4b851c	291	(match_test "TARGET_EXT_PERF && (ival == 0x1)")))
9304f876 CJW	292
	293	(define_constraint "Ix11"
	294	"The immediate value 0x7ff"
	295	(and (match_code "const_int")
aa4b851c	296	(match_test "TARGET_EXT_PERF && (ival == 0x7ff)")))
9304f876 CJW	297
	298	(define_constraint "Ibms"
	299	"The immediate value with power of 2"
	300	(and (match_code "const_int")
	301	(match_test "(TARGET_ISA_V3 \|\| TARGET_ISA_V3M)
	302	&& (IN_RANGE (exact_log2 (ival), 0, 7))")))
	303
	304	(define_constraint "Ifex"
	305	"The immediate value with power of 2 minus 1"
	306	(and (match_code "const_int")
	307	(match_test "(TARGET_ISA_V3 \|\| TARGET_ISA_V3M)
	308	&& (IN_RANGE (exact_log2 (ival + 1), 1, 8))")))
	309
7c32ef41 MC	310	(define_constraint "CVp5"
	311	"Unsigned immediate 5-bit value for movpi45 instruction with range 16-47"
	312	(and (match_code "const_vector")
	313	(match_test "nds32_valid_CVp5_p (op)")))
	314
	315	(define_constraint "CVs5"
	316	"Signed immediate 5-bit value"
	317	(and (match_code "const_vector")
	318	(match_test "nds32_valid_CVs5_p (op)")))
	319
	320	(define_constraint "CVs2"
	321	"Signed immediate 20-bit value"
	322	(and (match_code "const_vector")
	323	(match_test "nds32_valid_CVs2_p (op)")))
	324
	325	(define_constraint "CVhi"
	326	"The immediate value that can be simply set high 20-bit"
	327	(and (match_code "const_vector")
	328	(match_test "nds32_valid_CVhi_p (op)")))
9304f876 CJW	329
	330	(define_memory_constraint "U33"
	331	"Memory constraint for 333 format"
	332	(and (match_code "mem")
67e1eb3d SC	333	(match_test "nds32_mem_format (op) == ADDRESS_POST_INC_LO_REG_IMM3U
	334	\|\| nds32_mem_format (op) == ADDRESS_POST_MODIFY_LO_REG_IMM3U
	335	\|\| nds32_mem_format (op) == ADDRESS_LO_REG_IMM3U")))
9304f876 CJW	336
	337	(define_memory_constraint "U45"
	338	"Memory constraint for 45 format"
	339	(and (match_code "mem")
	340	(match_test "(nds32_mem_format (op) == ADDRESS_REG)
e2286268 MC	341	&& ((GET_MODE (op) == SImode)
e2286268 MC	342	\|\| (GET_MODE (op) == SFmode))")))
9304f876	343
8656bbcf SC	344	(define_memory_constraint "Ufe"
	345	"Memory constraint for fe format"
	346	(and (match_code "mem")
	347	(match_test "nds32_mem_format (op) == ADDRESS_R8_IMM7U
e2286268 MC	348	&& (GET_MODE (op) == SImode
e2286268 MC	349	\|\| GET_MODE (op) == SFmode)")))
8656bbcf	350
9304f876 CJW	351	(define_memory_constraint "U37"
	352	"Memory constraint for 37 format"
	353	(and (match_code "mem")
	354	(match_test "(nds32_mem_format (op) == ADDRESS_SP_IMM7U
	355	\|\| nds32_mem_format (op) == ADDRESS_FP_IMM7U)
e2286268 MC	356	&& (GET_MODE (op) == SImode
e2286268 MC	357	\|\| GET_MODE (op) == SFmode)")))
e576ddb5 KC	358
	359	(define_memory_constraint "Umw"
	360	"Memory constraint for lwm/smw"
	361	(and (match_code "mem")
	362	(match_test "nds32_valid_smw_lwm_base_p (op)")))
	363
e2286268 MC	364	(define_memory_constraint "Da"
	365	"Memory constraint for non-offset loads/stores"
	366	(and (match_code "mem")
	367	(match_test "REG_P (XEXP (op, 0))
	368	\|\| (GET_CODE (XEXP (op, 0)) == POST_INC)")))
	369
	370	(define_memory_constraint "Q"
	371	"Memory constraint for no symbol_ref and const"
	372	(and (match_code "mem")
	373	(match_test "(TARGET_FPU_SINGLE \|\| TARGET_FPU_DOUBLE)
	374	&& nds32_float_mem_operand_p (op)")))
	375
7af10dfe CJW	376	(define_constraint "S"
	377	"@internal
	378	A constant call address."
	379	(match_operand 0 "nds32_symbolic_operand"))
	380
9304f876	381	;; ------------------------------------------------------------------------