projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 03f33657 | 1 | /* Machine mode switch for RISC-V 'V' Extension for GNU compiler. |
| a945c346 | 2 | Copyright (C) 2022-2024 Free Software Foundation, Inc. |
| 03f33657 JZZ |
3 | Contributed by Ju-Zhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd. |
| 4 | ||
| 5 | This file is part of GCC. | |
| 6 | ||
| 7 | GCC is free software; you can redistribute it and/or modify | |
| 8 | it under the terms of the GNU General Public License as published by | |
| 9 | the Free Software Foundation; either version 3, or (at your option) | |
| 10 | any later version. | |
| 11 | ||
| 12 | GCC is distributed in the hope that it will be useful, | |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | GNU General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU General Public License | |
| 18 | along with GCC; see the file COPYING3. If not see | |
| 19 | <http://www.gnu.org/licenses/>. */ | |
| 20 | ||
| 21 | /* This file is enable or disable the RVV modes according '-march'. */ | |
| 22 | ||
| 23 | /* According to rvv-intrinsic and RISC-V 'V' Extension ISA document: | |
| 24 | https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md. | |
| 25 | https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc. | |
| 26 | ||
| 27 | Data Types | |
| 28 | Encode SEW and LMUL into data types. | |
| 29 | We enforce the constraint LMUL ≥ SEW/ELEN in the implementation. | |
| 30 | There are the following data types for MIN_VLEN > 32. | |
| 31 | ||
| 32 | Note: N/A means the corresponding vector type is disabled. | |
| 33 | ||
| 879c52c9 JZ |
34 | Encode SEW and LMUL into data types. |
| 35 | We enforce the constraint LMUL ≥ SEW/ELEN in the implementation. | |
| 36 | There are the following data types for ELEN = 64. | |
| 37 | ||
| 38 | |Modes|LMUL=1 |LMUL=2 |LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8| | |
| 39 | |DI |RVVM1DI|RVVM2DI|RVVM4DI|RVVM8DI|N/A |N/A |N/A | | |
| 40 | |SI |RVVM1SI|RVVM2SI|RVVM4SI|RVVM8SI|RVVMF2SI|N/A |N/A | | |
| 41 | |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|RVVMF4HI|N/A | | |
| 42 | |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|RVVMF8QI| | |
| 43 | |DF |RVVM1DF|RVVM2DF|RVVM4DF|RVVM8DF|N/A |N/A |N/A | | |
| 44 | |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|RVVMF2SF|N/A |N/A | | |
| 45 | |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|RVVMF4HF|N/A | | |
| 46 | ||
| 47 | There are the following data types for ELEN = 32. | |
| 48 | ||
| 49 | |Modes|LMUL=1 |LMUL=2 |LMUL=4 |LMUL=8 |LMUL=1/2|LMUL=1/4|LMUL=1/8| | |
| 50 | |SI |RVVM1SI|RVVM2SI|RVVM4SI|RVVM8SI|N/A |N/A |N/A | | |
| 51 | |HI |RVVM1HI|RVVM2HI|RVVM4HI|RVVM8HI|RVVMF2HI|N/A |N/A | | |
| 52 | |QI |RVVM1QI|RVVM2QI|RVVM4QI|RVVM8QI|RVVMF2QI|RVVMF4QI|N/A | | |
| 53 | |SF |RVVM1SF|RVVM2SF|RVVM4SF|RVVM8SF|N/A |N/A |N/A | | |
| 54 | |HF |RVVM1HF|RVVM2HF|RVVM4HF|RVVM8HF|RVVMF2HF|N/A |N/A | | |
| 55 | ||
| 56 | Encode the ratio of SEW/LMUL into the mask types. | |
| 57 | There are the following mask types. | |
| 58 | ||
| 59 | n = SEW/LMUL | |
| 60 | ||
| 61 | |Modes| n = 1 | n = 2 | n = 4 | n = 8 | n = 16 | n = 32 | n = 64 | | |
| 62 | |BI |RVVM1BI|RVVMF2BI|RVVMF4BI|RVVMF8BI|RVVMF16BI|RVVMF32BI|RVVMF64BI| */ | |
| 03f33657 JZZ |
63 | |
| 64 | /* Return 'REQUIREMENT' for machine_mode 'MODE'. | |
| 879c52c9 | 65 | For example: 'MODE' = RVVMF64BImode needs TARGET_MIN_VLEN > 32. */ |
| 03f33657 | 66 | #ifndef ENTRY |
| 879c52c9 | 67 | #define ENTRY(MODE, REQUIREMENT, VLMUL, RATIO) |
| 03f33657 | 68 | #endif |
| 879c52c9 JZ |
69 | |
| 70 | /* Disable modes if TARGET_MIN_VLEN == 32. */ | |
| 71 | ENTRY (RVVMF64BI, TARGET_MIN_VLEN > 32, LMUL_F8, 64) | |
| 72 | ENTRY (RVVMF32BI, true, LMUL_F4, 32) | |
| 73 | ENTRY (RVVMF16BI, true, LMUL_F2, 16) | |
| 74 | ENTRY (RVVMF8BI, true, LMUL_1, 8) | |
| 75 | ENTRY (RVVMF4BI, true, LMUL_2, 4) | |
| 76 | ENTRY (RVVMF2BI, true, LMUL_4, 2) | |
| 77 | ENTRY (RVVM1BI, true, LMUL_8, 1) | |
| 78 | ||
| 79 | /* Disable modes if TARGET_MIN_VLEN == 32. */ | |
| 80 | ENTRY (RVVM8QI, true, LMUL_8, 1) | |
| 81 | ENTRY (RVVM4QI, true, LMUL_4, 2) | |
| 82 | ENTRY (RVVM2QI, true, LMUL_2, 4) | |
| 83 | ENTRY (RVVM1QI, true, LMUL_1, 8) | |
| 84 | ENTRY (RVVMF2QI, true, LMUL_F2, 16) | |
| 85 | ENTRY (RVVMF4QI, true, LMUL_F4, 32) | |
| 86 | ENTRY (RVVMF8QI, TARGET_MIN_VLEN > 32, LMUL_F8, 64) | |
| 87 | ||
| 88 | /* Disable modes if TARGET_MIN_VLEN == 32. */ | |
| 89 | ENTRY (RVVM8HI, true, LMUL_8, 2) | |
| 90 | ENTRY (RVVM4HI, true, LMUL_4, 4) | |
| 91 | ENTRY (RVVM2HI, true, LMUL_2, 8) | |
| 92 | ENTRY (RVVM1HI, true, LMUL_1, 16) | |
| 93 | ENTRY (RVVMF2HI, true, LMUL_F2, 32) | |
| 94 | ENTRY (RVVMF4HI, TARGET_MIN_VLEN > 32, LMUL_F4, 64) | |
| 95 | ||
| 96 | /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_16. */ | |
| 97 | ENTRY (RVVM8HF, TARGET_VECTOR_ELEN_FP_16, LMUL_8, 2) | |
| 98 | ENTRY (RVVM4HF, TARGET_VECTOR_ELEN_FP_16, LMUL_4, 4) | |
| 99 | ENTRY (RVVM2HF, TARGET_VECTOR_ELEN_FP_16, LMUL_2, 8) | |
| 100 | ENTRY (RVVM1HF, TARGET_VECTOR_ELEN_FP_16, LMUL_1, 16) | |
| 101 | ENTRY (RVVMF2HF, TARGET_VECTOR_ELEN_FP_16, LMUL_F2, 32) | |
| 102 | ENTRY (RVVMF4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, LMUL_F4, 64) | |
| 103 | ||
| 104 | /* Disable modes if TARGET_MIN_VLEN == 32. */ | |
| 105 | ENTRY (RVVM8SI, true, LMUL_8, 4) | |
| 106 | ENTRY (RVVM4SI, true, LMUL_4, 8) | |
| 107 | ENTRY (RVVM2SI, true, LMUL_2, 16) | |
| 108 | ENTRY (RVVM1SI, true, LMUL_1, 32) | |
| 109 | ENTRY (RVVMF2SI, TARGET_MIN_VLEN > 32, LMUL_F2, 64) | |
| 110 | ||
| 111 | /* Disable modes if TARGET_MIN_VLEN == 32 or !TARGET_VECTOR_ELEN_FP_32. */ | |
| 112 | ENTRY (RVVM8SF, TARGET_VECTOR_ELEN_FP_32, LMUL_8, 4) | |
| 113 | ENTRY (RVVM4SF, TARGET_VECTOR_ELEN_FP_32, LMUL_4, 8) | |
| 114 | ENTRY (RVVM2SF, TARGET_VECTOR_ELEN_FP_32, LMUL_2, 16) | |
| 115 | ENTRY (RVVM1SF, TARGET_VECTOR_ELEN_FP_32, LMUL_1, 32) | |
| 116 | ENTRY (RVVMF2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, LMUL_F2, 64) | |
| 117 | ||
| 118 | /* Disable modes if !TARGET_VECTOR_ELEN_64. */ | |
| 119 | ENTRY (RVVM8DI, TARGET_VECTOR_ELEN_64, LMUL_8, 8) | |
| 120 | ENTRY (RVVM4DI, TARGET_VECTOR_ELEN_64, LMUL_4, 16) | |
| 121 | ENTRY (RVVM2DI, TARGET_VECTOR_ELEN_64, LMUL_2, 32) | |
| 122 | ENTRY (RVVM1DI, TARGET_VECTOR_ELEN_64, LMUL_1, 64) | |
| 123 | ||
| 124 | /* Disable modes if !TARGET_VECTOR_ELEN_FP_64. */ | |
| 125 | ENTRY (RVVM8DF, TARGET_VECTOR_ELEN_FP_64, LMUL_8, 8) | |
| 126 | ENTRY (RVVM4DF, TARGET_VECTOR_ELEN_FP_64, LMUL_4, 16) | |
| 127 | ENTRY (RVVM2DF, TARGET_VECTOR_ELEN_FP_64, LMUL_2, 32) | |
| 128 | ENTRY (RVVM1DF, TARGET_VECTOR_ELEN_FP_64, LMUL_1, 64) | |
| 129 | ||
| 130 | /* Tuple modes for segment loads/stores according to NF. | |
| 131 | ||
| 132 | Tuple modes format: RVV<LMUL>x<NF><BASEMODE> | |
| 133 | ||
| 134 | When LMUL is MF8/MF4/MF2/M1, NF can be 2 ~ 8. | |
| 135 | When LMUL is M2, NF can be 2 ~ 4. | |
| 136 | When LMUL is M4, NF can be 4. */ | |
| 137 | ||
| 12847288 | 138 | #ifndef TUPLE_ENTRY |
| 879c52c9 | 139 | #define TUPLE_ENTRY(MODE, REQUIREMENT, SUBPART_MODE, NF, VLMUL, RATIO) |
| 12847288 | 140 | #endif |
| 03f33657 | 141 | |
| 879c52c9 JZ |
142 | TUPLE_ENTRY (RVVM1x8QI, true, RVVM1QI, 8, LMUL_1, 8) |
| 143 | TUPLE_ENTRY (RVVMF2x8QI, true, RVVMF2QI, 8, LMUL_F2, 16) | |
| 144 | TUPLE_ENTRY (RVVMF4x8QI, true, RVVMF4QI, 8, LMUL_F4, 32) | |
| 145 | TUPLE_ENTRY (RVVMF8x8QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 8, LMUL_F8, 64) | |
| 146 | TUPLE_ENTRY (RVVM1x7QI, true, RVVM1QI, 7, LMUL_1, 8) | |
| 147 | TUPLE_ENTRY (RVVMF2x7QI, true, RVVMF2QI, 7, LMUL_F2, 16) | |
| 148 | TUPLE_ENTRY (RVVMF4x7QI, true, RVVMF4QI, 7, LMUL_F4, 32) | |
| 149 | TUPLE_ENTRY (RVVMF8x7QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 7, LMUL_F8, 64) | |
| 150 | TUPLE_ENTRY (RVVM1x6QI, true, RVVM1QI, 6, LMUL_1, 8) | |
| 151 | TUPLE_ENTRY (RVVMF2x6QI, true, RVVMF2QI, 6, LMUL_F2, 16) | |
| 152 | TUPLE_ENTRY (RVVMF4x6QI, true, RVVMF4QI, 6, LMUL_F4, 32) | |
| 153 | TUPLE_ENTRY (RVVMF8x6QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 6, LMUL_F8, 64) | |
| 154 | TUPLE_ENTRY (RVVM1x5QI, true, RVVM1QI, 5, LMUL_1, 8) | |
| 155 | TUPLE_ENTRY (RVVMF2x5QI, true, RVVMF2QI, 5, LMUL_F2, 16) | |
| 156 | TUPLE_ENTRY (RVVMF4x5QI, true, RVVMF4QI, 5, LMUL_F4, 32) | |
| 157 | TUPLE_ENTRY (RVVMF8x5QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 5, LMUL_F8, 64) | |
| 158 | TUPLE_ENTRY (RVVM2x4QI, true, RVVM2QI, 4, LMUL_2, 4) | |
| 159 | TUPLE_ENTRY (RVVM1x4QI, true, RVVM1QI, 4, LMUL_1, 8) | |
| 160 | TUPLE_ENTRY (RVVMF2x4QI, true, RVVMF2QI, 4, LMUL_F2, 16) | |
| 161 | TUPLE_ENTRY (RVVMF4x4QI, true, RVVMF4QI, 4, LMUL_F4, 32) | |
| 162 | TUPLE_ENTRY (RVVMF8x4QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 4, LMUL_F8, 64) | |
| 163 | TUPLE_ENTRY (RVVM2x3QI, true, RVVM2QI, 3, LMUL_2, 4) | |
| 164 | TUPLE_ENTRY (RVVM1x3QI, true, RVVM1QI, 3, LMUL_1, 8) | |
| 165 | TUPLE_ENTRY (RVVMF2x3QI, true, RVVMF2QI, 3, LMUL_F2, 16) | |
| 166 | TUPLE_ENTRY (RVVMF4x3QI, true, RVVMF4QI, 3, LMUL_F4, 32) | |
| 167 | TUPLE_ENTRY (RVVMF8x3QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 3, LMUL_F8, 64) | |
| 168 | TUPLE_ENTRY (RVVM4x2QI, true, RVVM4QI, 2, LMUL_4, 2) | |
| 169 | TUPLE_ENTRY (RVVM2x2QI, true, RVVM2QI, 2, LMUL_2, 4) | |
| 170 | TUPLE_ENTRY (RVVM1x2QI, true, RVVM1QI, 2, LMUL_1, 8) | |
| 171 | TUPLE_ENTRY (RVVMF2x2QI, true, RVVMF2QI, 2, LMUL_F2, 16) | |
| 172 | TUPLE_ENTRY (RVVMF4x2QI, true, RVVMF4QI, 2, LMUL_F4, 32) | |
| 173 | TUPLE_ENTRY (RVVMF8x2QI, TARGET_MIN_VLEN > 32, RVVMF8QI, 2, LMUL_F8, 64) | |
| 174 | ||
| 175 | TUPLE_ENTRY (RVVM1x8HI, true, RVVM1HI, 8, LMUL_1, 16) | |
| 176 | TUPLE_ENTRY (RVVMF2x8HI, true, RVVMF2HI, 8, LMUL_F2, 32) | |
| 177 | TUPLE_ENTRY (RVVMF4x8HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 8, LMUL_F4, 64) | |
| 178 | TUPLE_ENTRY (RVVM1x7HI, true, RVVM1HI, 7, LMUL_1, 16) | |
| 179 | TUPLE_ENTRY (RVVMF2x7HI, true, RVVMF2HI, 7, LMUL_F2, 32) | |
| 180 | TUPLE_ENTRY (RVVMF4x7HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 7, LMUL_F4, 64) | |
| 181 | TUPLE_ENTRY (RVVM1x6HI, true, RVVM1HI, 6, LMUL_1, 16) | |
| 182 | TUPLE_ENTRY (RVVMF2x6HI, true, RVVMF2HI, 6, LMUL_F2, 32) | |
| 183 | TUPLE_ENTRY (RVVMF4x6HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 6, LMUL_F4, 64) | |
| 184 | TUPLE_ENTRY (RVVM1x5HI, true, RVVM1HI, 5, LMUL_1, 16) | |
| 185 | TUPLE_ENTRY (RVVMF2x5HI, true, RVVMF2HI, 5, LMUL_F2, 32) | |
| 186 | TUPLE_ENTRY (RVVMF4x5HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 5, LMUL_F4, 64) | |
| 187 | TUPLE_ENTRY (RVVM2x4HI, true, RVVM2HI, 4, LMUL_2, 8) | |
| 188 | TUPLE_ENTRY (RVVM1x4HI, true, RVVM1HI, 4, LMUL_1, 16) | |
| 189 | TUPLE_ENTRY (RVVMF2x4HI, true, RVVMF2HI, 4, LMUL_F2, 32) | |
| 190 | TUPLE_ENTRY (RVVMF4x4HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 4, LMUL_F4, 64) | |
| 191 | TUPLE_ENTRY (RVVM2x3HI, true, RVVM2HI, 3, LMUL_2, 8) | |
| 192 | TUPLE_ENTRY (RVVM1x3HI, true, RVVM1HI, 3, LMUL_1, 16) | |
| 193 | TUPLE_ENTRY (RVVMF2x3HI, true, RVVMF2HI, 3, LMUL_F2, 32) | |
| 194 | TUPLE_ENTRY (RVVMF4x3HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 3, LMUL_F4, 64) | |
| 195 | TUPLE_ENTRY (RVVM4x2HI, true, RVVM4HI, 2, LMUL_4, 4) | |
| 196 | TUPLE_ENTRY (RVVM2x2HI, true, RVVM2HI, 2, LMUL_2, 8) | |
| 197 | TUPLE_ENTRY (RVVM1x2HI, true, RVVM1HI, 2, LMUL_1, 16) | |
| 198 | TUPLE_ENTRY (RVVMF2x2HI, true, RVVMF2HI, 2, LMUL_F2, 32) | |
| 199 | TUPLE_ENTRY (RVVMF4x2HI, TARGET_MIN_VLEN > 32, RVVMF4HI, 2, LMUL_F4, 64) | |
| 200 | ||
| 201 | TUPLE_ENTRY (RVVM1x8HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 8, LMUL_1, 16) | |
| 202 | TUPLE_ENTRY (RVVMF2x8HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 8, LMUL_F2, 32) | |
| 203 | TUPLE_ENTRY (RVVMF4x8HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 8, LMUL_F4, 64) | |
| 204 | TUPLE_ENTRY (RVVM1x7HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 7, LMUL_1, 16) | |
| 205 | TUPLE_ENTRY (RVVMF2x7HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 7, LMUL_F2, 32) | |
| 206 | TUPLE_ENTRY (RVVMF4x7HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 7, LMUL_F4, 64) | |
| 207 | TUPLE_ENTRY (RVVM1x6HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 6, LMUL_1, 16) | |
| 208 | TUPLE_ENTRY (RVVMF2x6HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 6, LMUL_F2, 32) | |
| 209 | TUPLE_ENTRY (RVVMF4x6HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 6, LMUL_F4, 64) | |
| 210 | TUPLE_ENTRY (RVVM1x5HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 5, LMUL_1, 16) | |
| 211 | TUPLE_ENTRY (RVVMF2x5HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 5, LMUL_F2, 32) | |
| 212 | TUPLE_ENTRY (RVVMF4x5HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 5, LMUL_F4, 64) | |
| 213 | TUPLE_ENTRY (RVVM2x4HF, TARGET_VECTOR_ELEN_FP_16, RVVM2HF, 4, LMUL_2, 8) | |
| 214 | TUPLE_ENTRY (RVVM1x4HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 4, LMUL_1, 16) | |
| 215 | TUPLE_ENTRY (RVVMF2x4HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 4, LMUL_F2, 32) | |
| 216 | TUPLE_ENTRY (RVVMF4x4HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 4, LMUL_F4, 64) | |
| 217 | TUPLE_ENTRY (RVVM2x3HF, TARGET_VECTOR_ELEN_FP_16, RVVM2HF, 3, LMUL_2, 8) | |
| 218 | TUPLE_ENTRY (RVVM1x3HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 3, LMUL_1, 16) | |
| 219 | TUPLE_ENTRY (RVVMF2x3HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 3, LMUL_F2, 32) | |
| 220 | TUPLE_ENTRY (RVVMF4x3HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 3, LMUL_F4, 64) | |
| 221 | TUPLE_ENTRY (RVVM4x2HF, TARGET_VECTOR_ELEN_FP_16, RVVM4HF, 2, LMUL_4, 4) | |
| 222 | TUPLE_ENTRY (RVVM2x2HF, TARGET_VECTOR_ELEN_FP_16, RVVM2HF, 2, LMUL_2, 8) | |
| 223 | TUPLE_ENTRY (RVVM1x2HF, TARGET_VECTOR_ELEN_FP_16, RVVM1HF, 2, LMUL_1, 16) | |
| 224 | TUPLE_ENTRY (RVVMF2x2HF, TARGET_VECTOR_ELEN_FP_16, RVVMF2HF, 2, LMUL_F2, 32) | |
| 225 | TUPLE_ENTRY (RVVMF4x2HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, RVVMF4HF, 2, LMUL_F4, 64) | |
| 226 | ||
| 227 | TUPLE_ENTRY (RVVM1x8SI, true, RVVM1SI, 8, LMUL_1, 16) | |
| 228 | TUPLE_ENTRY (RVVMF2x8SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 8, LMUL_F2, 32) | |
| 229 | TUPLE_ENTRY (RVVM1x7SI, true, RVVM1SI, 7, LMUL_1, 16) | |
| 230 | TUPLE_ENTRY (RVVMF2x7SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 7, LMUL_F2, 32) | |
| 231 | TUPLE_ENTRY (RVVM1x6SI, true, RVVM1SI, 6, LMUL_1, 16) | |
| 232 | TUPLE_ENTRY (RVVMF2x6SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 6, LMUL_F2, 32) | |
| 233 | TUPLE_ENTRY (RVVM1x5SI, true, RVVM1SI, 5, LMUL_1, 16) | |
| 234 | TUPLE_ENTRY (RVVMF2x5SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 5, LMUL_F2, 32) | |
| 235 | TUPLE_ENTRY (RVVM2x4SI, true, RVVM2SI, 4, LMUL_2, 8) | |
| 236 | TUPLE_ENTRY (RVVM1x4SI, true, RVVM1SI, 4, LMUL_1, 16) | |
| 237 | TUPLE_ENTRY (RVVMF2x4SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 4, LMUL_F2, 32) | |
| 238 | TUPLE_ENTRY (RVVM2x3SI, true, RVVM2SI, 3, LMUL_2, 8) | |
| 239 | TUPLE_ENTRY (RVVM1x3SI, true, RVVM1SI, 3, LMUL_1, 16) | |
| 240 | TUPLE_ENTRY (RVVMF2x3SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 3, LMUL_F2, 32) | |
| 241 | TUPLE_ENTRY (RVVM4x2SI, true, RVVM4SI, 2, LMUL_4, 4) | |
| 242 | TUPLE_ENTRY (RVVM2x2SI, true, RVVM2SI, 2, LMUL_2, 8) | |
| 243 | TUPLE_ENTRY (RVVM1x2SI, true, RVVM1SI, 2, LMUL_1, 16) | |
| 244 | TUPLE_ENTRY (RVVMF2x2SI, TARGET_MIN_VLEN > 32, RVVMF2SI, 2, LMUL_F2, 32) | |
| 245 | ||
| 246 | TUPLE_ENTRY (RVVM1x8SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 8, LMUL_1, 16) | |
| 247 | TUPLE_ENTRY (RVVMF2x8SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 8, LMUL_F2, 32) | |
| 248 | TUPLE_ENTRY (RVVM1x7SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 7, LMUL_1, 16) | |
| 249 | TUPLE_ENTRY (RVVMF2x7SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 7, LMUL_F2, 32) | |
| 250 | TUPLE_ENTRY (RVVM1x6SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 6, LMUL_1, 16) | |
| 251 | TUPLE_ENTRY (RVVMF2x6SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 6, LMUL_F2, 32) | |
| 252 | TUPLE_ENTRY (RVVM1x5SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 5, LMUL_1, 16) | |
| 253 | TUPLE_ENTRY (RVVMF2x5SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 5, LMUL_F2, 32) | |
| 254 | TUPLE_ENTRY (RVVM2x4SF, TARGET_VECTOR_ELEN_FP_32, RVVM2SF, 4, LMUL_2, 8) | |
| 255 | TUPLE_ENTRY (RVVM1x4SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 4, LMUL_1, 16) | |
| 256 | TUPLE_ENTRY (RVVMF2x4SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 4, LMUL_F2, 32) | |
| 257 | TUPLE_ENTRY (RVVM2x3SF, TARGET_VECTOR_ELEN_FP_32, RVVM2SF, 3, LMUL_2, 8) | |
| 258 | TUPLE_ENTRY (RVVM1x3SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 3, LMUL_1, 16) | |
| 259 | TUPLE_ENTRY (RVVMF2x3SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 3, LMUL_F2, 32) | |
| 260 | TUPLE_ENTRY (RVVM4x2SF, TARGET_VECTOR_ELEN_FP_32, RVVM4SF, 2, LMUL_4, 4) | |
| 261 | TUPLE_ENTRY (RVVM2x2SF, TARGET_VECTOR_ELEN_FP_32, RVVM2SF, 2, LMUL_2, 8) | |
| 262 | TUPLE_ENTRY (RVVM1x2SF, TARGET_VECTOR_ELEN_FP_32, RVVM1SF, 2, LMUL_1, 16) | |
| 263 | TUPLE_ENTRY (RVVMF2x2SF, TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32, RVVMF2SF, 2, LMUL_F2, 32) | |
| 264 | ||
| 265 | TUPLE_ENTRY (RVVM1x8DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 8, LMUL_1, 16) | |
| 266 | TUPLE_ENTRY (RVVM1x7DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 7, LMUL_1, 16) | |
| 267 | TUPLE_ENTRY (RVVM1x6DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 6, LMUL_1, 16) | |
| 268 | TUPLE_ENTRY (RVVM1x5DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 5, LMUL_1, 16) | |
| 269 | TUPLE_ENTRY (RVVM2x4DI, TARGET_VECTOR_ELEN_64, RVVM2DI, 4, LMUL_2, 8) | |
| 270 | TUPLE_ENTRY (RVVM1x4DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 4, LMUL_1, 16) | |
| 271 | TUPLE_ENTRY (RVVM2x3DI, TARGET_VECTOR_ELEN_64, RVVM2DI, 3, LMUL_2, 8) | |
| 272 | TUPLE_ENTRY (RVVM1x3DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 3, LMUL_1, 16) | |
| 273 | TUPLE_ENTRY (RVVM4x2DI, TARGET_VECTOR_ELEN_64, RVVM4DI, 2, LMUL_4, 4) | |
| 274 | TUPLE_ENTRY (RVVM2x2DI, TARGET_VECTOR_ELEN_64, RVVM2DI, 2, LMUL_2, 8) | |
| 275 | TUPLE_ENTRY (RVVM1x2DI, TARGET_VECTOR_ELEN_64, RVVM1DI, 2, LMUL_1, 16) | |
| 276 | ||
| 277 | TUPLE_ENTRY (RVVM1x8DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 8, LMUL_1, 16) | |
| 278 | TUPLE_ENTRY (RVVM1x7DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 7, LMUL_1, 16) | |
| 279 | TUPLE_ENTRY (RVVM1x6DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 6, LMUL_1, 16) | |
| 280 | TUPLE_ENTRY (RVVM1x5DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 5, LMUL_1, 16) | |
| 281 | TUPLE_ENTRY (RVVM2x4DF, TARGET_VECTOR_ELEN_FP_64, RVVM2DF, 4, LMUL_2, 8) | |
| 282 | TUPLE_ENTRY (RVVM1x4DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 4, LMUL_1, 16) | |
| 283 | TUPLE_ENTRY (RVVM2x3DF, TARGET_VECTOR_ELEN_FP_64, RVVM2DF, 3, LMUL_2, 8) | |
| 284 | TUPLE_ENTRY (RVVM1x3DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 3, LMUL_1, 16) | |
| 285 | TUPLE_ENTRY (RVVM4x2DF, TARGET_VECTOR_ELEN_FP_64, RVVM4DF, 2, LMUL_4, 4) | |
| 286 | TUPLE_ENTRY (RVVM2x2DF, TARGET_VECTOR_ELEN_FP_64, RVVM2DF, 2, LMUL_2, 8) | |
| 287 | TUPLE_ENTRY (RVVM1x2DF, TARGET_VECTOR_ELEN_FP_64, RVVM1DF, 2, LMUL_1, 16) | |
| 12847288 | 288 | |
| 33b153ff JZ |
289 | #ifndef VLS_ENTRY |
| 290 | #define VLS_ENTRY(MODE, REQUIREMENT) | |
| 291 | #endif | |
| 292 | ||
| 293 | /* This following VLS modes should satisfy the constraint: | |
| 294 | GET_MODE_BITSIZE (MODE) <= TARGET_MIN_VLEN * 8. */ | |
| 66c26e5c PL |
295 | VLS_ENTRY (V1BI, riscv_vector::vls_mode_valid_p (V1BImode)) |
| 296 | VLS_ENTRY (V2BI, riscv_vector::vls_mode_valid_p (V2BImode)) | |
| 297 | VLS_ENTRY (V4BI, riscv_vector::vls_mode_valid_p (V4BImode)) | |
| 298 | VLS_ENTRY (V8BI, riscv_vector::vls_mode_valid_p (V8BImode)) | |
| 299 | VLS_ENTRY (V16BI, riscv_vector::vls_mode_valid_p (V16BImode)) | |
| 300 | VLS_ENTRY (V32BI, riscv_vector::vls_mode_valid_p (V32BImode)) | |
| 301 | VLS_ENTRY (V64BI, riscv_vector::vls_mode_valid_p (V64BImode) && TARGET_MIN_VLEN >= 64) | |
| 302 | VLS_ENTRY (V128BI, riscv_vector::vls_mode_valid_p (V128BImode) && TARGET_MIN_VLEN >= 128) | |
| 303 | VLS_ENTRY (V256BI, riscv_vector::vls_mode_valid_p (V256BImode) && TARGET_MIN_VLEN >= 256) | |
| 304 | VLS_ENTRY (V512BI, riscv_vector::vls_mode_valid_p (V512BImode) && TARGET_MIN_VLEN >= 512) | |
| 305 | VLS_ENTRY (V1024BI, riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN >= 1024) | |
| 306 | VLS_ENTRY (V2048BI, riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048) | |
| 307 | VLS_ENTRY (V4096BI, riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096) | |
| 308 | ||
| 309 | VLS_ENTRY (V1QI, riscv_vector::vls_mode_valid_p (V1QImode)) | |
| 310 | VLS_ENTRY (V2QI, riscv_vector::vls_mode_valid_p (V2QImode)) | |
| 311 | VLS_ENTRY (V4QI, riscv_vector::vls_mode_valid_p (V4QImode)) | |
| 312 | VLS_ENTRY (V8QI, riscv_vector::vls_mode_valid_p (V8QImode)) | |
| 313 | VLS_ENTRY (V16QI, riscv_vector::vls_mode_valid_p (V16QImode)) | |
| 314 | VLS_ENTRY (V32QI, riscv_vector::vls_mode_valid_p (V32QImode)) | |
| 315 | VLS_ENTRY (V64QI, riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64) | |
| 316 | VLS_ENTRY (V128QI, riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128) | |
| 317 | VLS_ENTRY (V256QI, riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256) | |
| 318 | VLS_ENTRY (V512QI, riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512) | |
| 319 | VLS_ENTRY (V1024QI, riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024) | |
| 320 | VLS_ENTRY (V2048QI, riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048) | |
| 321 | VLS_ENTRY (V4096QI, riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096) | |
| 322 | VLS_ENTRY (V1HI, riscv_vector::vls_mode_valid_p (V1HImode)) | |
| 323 | VLS_ENTRY (V2HI, riscv_vector::vls_mode_valid_p (V2HImode)) | |
| 324 | VLS_ENTRY (V4HI, riscv_vector::vls_mode_valid_p (V4HImode)) | |
| 325 | VLS_ENTRY (V8HI, riscv_vector::vls_mode_valid_p (V8HImode)) | |
| 326 | VLS_ENTRY (V16HI, riscv_vector::vls_mode_valid_p (V16HImode)) | |
| 327 | VLS_ENTRY (V32HI, riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64) | |
| 328 | VLS_ENTRY (V64HI, riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128) | |
| 329 | VLS_ENTRY (V128HI, riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256) | |
| 330 | VLS_ENTRY (V256HI, riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512) | |
| 331 | VLS_ENTRY (V512HI, riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024) | |
| 332 | VLS_ENTRY (V1024HI, riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048) | |
| 333 | VLS_ENTRY (V2048HI, riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096) | |
| 334 | VLS_ENTRY (V1SI, riscv_vector::vls_mode_valid_p (V1SImode)) | |
| 335 | VLS_ENTRY (V2SI, riscv_vector::vls_mode_valid_p (V2SImode)) | |
| 336 | VLS_ENTRY (V4SI, riscv_vector::vls_mode_valid_p (V4SImode)) | |
| 337 | VLS_ENTRY (V8SI, riscv_vector::vls_mode_valid_p (V8SImode)) | |
| 338 | VLS_ENTRY (V16SI, riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64) | |
| 339 | VLS_ENTRY (V32SI, riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128) | |
| 340 | VLS_ENTRY (V64SI, riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256) | |
| 341 | VLS_ENTRY (V128SI, riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512) | |
| 342 | VLS_ENTRY (V256SI, riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024) | |
| 343 | VLS_ENTRY (V512SI, riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048) | |
| 344 | VLS_ENTRY (V1024SI, riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096) | |
| 345 | VLS_ENTRY (V1DI, riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64) | |
| 346 | VLS_ENTRY (V2DI, riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64) | |
| 347 | VLS_ENTRY (V4DI, riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64) | |
| 348 | VLS_ENTRY (V8DI, riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64) | |
| 349 | VLS_ENTRY (V16DI, riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128) | |
| 350 | VLS_ENTRY (V32DI, riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256) | |
| 351 | VLS_ENTRY (V64DI, riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512) | |
| 352 | VLS_ENTRY (V128DI, riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024) | |
| 353 | VLS_ENTRY (V256DI, riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048) | |
| 354 | VLS_ENTRY (V512DI, riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096) | |
| 355 | ||
| 356 | VLS_ENTRY (V1HF, riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_VECTOR_ELEN_FP_16) | |
| 357 | VLS_ENTRY (V2HF, riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_VECTOR_ELEN_FP_16) | |
| 358 | VLS_ENTRY (V4HF, riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_VECTOR_ELEN_FP_16) | |
| 359 | VLS_ENTRY (V8HF, riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_VECTOR_ELEN_FP_16) | |
| 360 | VLS_ENTRY (V16HF, riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_VECTOR_ELEN_FP_16) | |
| 361 | VLS_ENTRY (V32HF, riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64) | |
| 362 | VLS_ENTRY (V64HF, riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128) | |
| 363 | VLS_ENTRY (V128HF, riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256) | |
| 364 | VLS_ENTRY (V256HF, riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512) | |
| 365 | VLS_ENTRY (V512HF, riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024) | |
| 366 | VLS_ENTRY (V1024HF, riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048) | |
| 367 | VLS_ENTRY (V2048HF, riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096) | |
| 368 | VLS_ENTRY (V1SF, riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32) | |
| 369 | VLS_ENTRY (V2SF, riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32) | |
| 370 | VLS_ENTRY (V4SF, riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32) | |
| 371 | VLS_ENTRY (V8SF, riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32) | |
| 372 | VLS_ENTRY (V16SF, riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64) | |
| 373 | VLS_ENTRY (V32SF, riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128) | |
| 374 | VLS_ENTRY (V64SF, riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256) | |
| 375 | VLS_ENTRY (V128SF, riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512) | |
| 376 | VLS_ENTRY (V256SF, riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024) | |
| 377 | VLS_ENTRY (V512SF, riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048) | |
| 378 | VLS_ENTRY (V1024SF, riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096) | |
| 379 | VLS_ENTRY (V1DF, riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64) | |
| 380 | VLS_ENTRY (V2DF, riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64) | |
| 381 | VLS_ENTRY (V4DF, riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64) | |
| 382 | VLS_ENTRY (V8DF, riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64) | |
| 383 | VLS_ENTRY (V16DF, riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128) | |
| 384 | VLS_ENTRY (V32DF, riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256) | |
| 385 | VLS_ENTRY (V64DF, riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512) | |
| 386 | VLS_ENTRY (V128DF, riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024) | |
| 387 | VLS_ENTRY (V256DF, riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048) | |
| 388 | VLS_ENTRY (V512DF, riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096) | |
| 33b153ff JZ |
389 | |
| 390 | #undef VLS_ENTRY | |
| 12847288 | 391 | #undef TUPLE_ENTRY |
| 879c52c9 | 392 | #undef ENTRY |