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52609473 | 1 | ;; Scheduling description for z990 (cpu 2084). |
d652f226 | 2 | ;; Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2010 |
66647d44 | 3 | ;; Free Software Foundation, Inc. |
52609473 HP |
4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
5 | ;; Ulrich Weigand (uweigand@de.ibm.com). | |
58add37a UW |
6 | |
7 | ;; This file is part of GCC. | |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
18 | ||
52609473 | 19 | ;; You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
52609473 HP |
22 | |
23 | (define_automaton "x_ipu") | |
24 | ||
25 | (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu") | |
26 | (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu") | |
27 | (define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu") | |
28 | (define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu") | |
29 | (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu") | |
30 | (define_cpu_unit "x_store_tok" "x_ipu") | |
31 | (define_cpu_unit "x_ms,x_mt" "x_ipu") | |
32 | ||
33 | (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)") | |
34 | ||
35 | (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)") | |
36 | ||
37 | (absence_set "x_e1_r" "x_e1_s,x_e1_t") | |
38 | (absence_set "x_e1_s" "x_e1_t") | |
39 | ||
40 | ;; Try to avoid int <-> fp transitions. | |
41 | ||
42 | (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4") | |
43 | (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6") | |
44 | (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)") | |
45 | (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)") | |
46 | (define_reservation "x-wr-fp" "x_wr_fp,x-f") | |
47 | (define_reservation "x-mem" "x_ms|x_mt") | |
48 | ||
49 | (absence_set "x_wr_fp" | |
50 | "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t") | |
51 | ||
52 | (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t" | |
53 | "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp") | |
54 | ||
55 | ;; Don't have any load type insn in same group as store | |
56 | ||
57 | (absence_set "x_ms,x_mt" "x_store_tok") | |
58 | ||
59 | ||
60 | ;; | |
61 | ;; Simple insns | |
62 | ;; | |
63 | ||
29a74354 | 64 | (define_insn_reservation "x_int" 1 |
ec24698e | 65 | (and (eq_attr "cpu" "z990,z9_109") |
29a74354 UW |
66 | (and (eq_attr "type" "integer") |
67 | (eq_attr "atype" "reg"))) | |
68 | "x-e1-st,x-wr-st") | |
69 | ||
70 | (define_insn_reservation "x_agen" 1 | |
ec24698e | 71 | (and (eq_attr "cpu" "z990,z9_109") |
29a74354 UW |
72 | (and (eq_attr "type" "integer") |
73 | (eq_attr "atype" "agen"))) | |
74 | "x-e1-st,x-wr-st") | |
75 | ||
52609473 | 76 | (define_insn_reservation "x_lr" 1 |
ec24698e | 77 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 78 | (eq_attr "type" "lr")) |
f4aa3848 | 79 | "x-e1-st,x-wr-st") |
52609473 | 80 | |
f4aa3848 | 81 | (define_insn_reservation "x_la" 1 |
ec24698e | 82 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 83 | (eq_attr "type" "la")) |
f4aa3848 | 84 | "x-e1-st,x-wr-st") |
52609473 | 85 | |
f4aa3848 | 86 | (define_insn_reservation "x_larl" 1 |
ec24698e | 87 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 88 | (eq_attr "type" "larl")) |
f4aa3848 | 89 | "x-e1-st,x-wr-st") |
52609473 | 90 | |
f4aa3848 | 91 | (define_insn_reservation "x_load" 1 |
ec24698e | 92 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 93 | (eq_attr "type" "load")) |
f4aa3848 | 94 | "x-e1-st+x-mem,x-wr-st") |
52609473 | 95 | |
f4aa3848 | 96 | (define_insn_reservation "x_store" 1 |
ec24698e | 97 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 98 | (eq_attr "type" "store")) |
f4aa3848 | 99 | "x-e1-st+x_store_tok,x-wr-st") |
52609473 | 100 | |
f4aa3848 | 101 | (define_insn_reservation "x_branch" 1 |
ec24698e | 102 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 103 | (eq_attr "type" "branch")) |
f4aa3848 | 104 | "x_e1_r,x_wr_r") |
52609473 | 105 | |
f4aa3848 | 106 | (define_insn_reservation "x_call" 5 |
ec24698e | 107 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 108 | (eq_attr "type" "jsr")) |
ed0e512a | 109 | "x-e1-np*5,x-wr-np") |
f4aa3848 | 110 | |
ed0e512a | 111 | (define_insn_reservation "x_mul_hi" 2 |
ec24698e | 112 | (and (eq_attr "cpu" "z990,z9_109") |
ed0e512a AK |
113 | (eq_attr "type" "imulhi")) |
114 | "x-e1-np*2,x-wr-np") | |
115 | ||
116 | (define_insn_reservation "x_mul_sidi" 4 | |
ec24698e | 117 | (and (eq_attr "cpu" "z990,z9_109") |
ed0e512a AK |
118 | (eq_attr "type" "imulsi,imuldi")) |
119 | "x-e1-np*4,x-wr-np") | |
120 | ||
121 | (define_insn_reservation "x_div" 10 | |
ec24698e | 122 | (and (eq_attr "cpu" "z990,z9_109") |
ed0e512a AK |
123 | (eq_attr "type" "idiv")) |
124 | "x-e1-np*10,x-wr-np") | |
52609473 | 125 | |
f4aa3848 | 126 | (define_insn_reservation "x_sem" 17 |
ec24698e | 127 | (and (eq_attr "cpu" "z990,z9_109") |
e0374221 | 128 | (eq_attr "type" "sem")) |
f4aa3848 | 129 | "x-e1-np+x-mem,x-e1-np*16,x-wr-st") |
e0374221 | 130 | |
52609473 HP |
131 | ;; |
132 | ;; Multicycle insns | |
133 | ;; | |
134 | ||
f4aa3848 | 135 | (define_insn_reservation "x_cs" 1 |
ec24698e | 136 | (and (eq_attr "cpu" "z990,z9_109") |
29a74354 | 137 | (eq_attr "type" "cs")) |
f4aa3848 | 138 | "x-e1-np,x-wr-np") |
52609473 | 139 | |
f4aa3848 | 140 | (define_insn_reservation "x_vs" 1 |
ec24698e | 141 | (and (eq_attr "cpu" "z990,z9_109") |
29a74354 | 142 | (eq_attr "type" "vs")) |
f4aa3848 | 143 | "x-e1-np*10,x-wr-np") |
29a74354 | 144 | |
f4aa3848 | 145 | (define_insn_reservation "x_stm" 1 |
ec24698e | 146 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 147 | (eq_attr "type" "stm")) |
f4aa3848 | 148 | "(x-e1-np+x_store_tok)*10,x-wr-np") |
52609473 | 149 | |
f4aa3848 | 150 | (define_insn_reservation "x_lm" 1 |
ec24698e | 151 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 152 | (eq_attr "type" "lm")) |
f4aa3848 | 153 | "x-e1-np*10,x-wr-np") |
52609473 | 154 | |
f4aa3848 | 155 | (define_insn_reservation "x_other" 1 |
ec24698e | 156 | (and (eq_attr "cpu" "z990,z9_109") |
29a74354 | 157 | (eq_attr "type" "other")) |
f4aa3848 | 158 | "x-e1-np,x-wr-np") |
52609473 | 159 | |
52609473 HP |
160 | ;; |
161 | ;; Floating point insns | |
162 | ;; | |
163 | ||
f4aa3848 | 164 | (define_insn_reservation "x_fsimptf" 7 |
f61a2c7d | 165 | (and (eq_attr "cpu" "z990,z9_109") |
2cdece44 | 166 | (eq_attr "type" "fsimptf,fhex")) |
f4aa3848 | 167 | "x_e1_t*2,x-wr-fp") |
f61a2c7d | 168 | |
f4aa3848 | 169 | (define_insn_reservation "x_fsimpdf" 6 |
ec24698e | 170 | (and (eq_attr "cpu" "z990,z9_109") |
65b1d8ea | 171 | (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex")) |
f4aa3848 | 172 | "x_e1_t,x-wr-fp") |
52609473 | 173 | |
f4aa3848 | 174 | (define_insn_reservation "x_fsimpsf" 6 |
ec24698e | 175 | (and (eq_attr "cpu" "z990,z9_109") |
65b1d8ea | 176 | (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex")) |
f4aa3848 | 177 | "x_e1_t,x-wr-fp") |
52609473 | 178 | |
f61a2c7d AK |
179 | |
180 | (define_insn_reservation "x_fmultf" 33 | |
181 | (and (eq_attr "cpu" "z990,z9_109") | |
182 | (eq_attr "type" "fmultf")) | |
f4aa3848 | 183 | "x_e1_t*27,x-wr-fp") |
f61a2c7d AK |
184 | |
185 | ||
186 | (define_insn_reservation "x_fdivtf" 82 | |
187 | (and (eq_attr "cpu" "z990,z9_109") | |
188 | (eq_attr "type" "fdivtf,fsqrttf")) | |
f4aa3848 | 189 | "x_e1_t*76,x-wr-fp") |
f61a2c7d | 190 | |
cfdb984b | 191 | (define_insn_reservation "x_fdivdf" 36 |
ec24698e | 192 | (and (eq_attr "cpu" "z990,z9_109") |
cfdb984b | 193 | (eq_attr "type" "fdivdf,fsqrtdf")) |
f4aa3848 | 194 | "x_e1_t*30,x-wr-fp") |
52609473 | 195 | |
f4aa3848 | 196 | (define_insn_reservation "x_fdivsf" 36 |
ec24698e | 197 | (and (eq_attr "cpu" "z990,z9_109") |
cfdb984b | 198 | (eq_attr "type" "fdivsf,fsqrtsf")) |
f4aa3848 | 199 | "x_e1_t*30,x-wr-fp") |
52609473 | 200 | |
f61a2c7d | 201 | |
f4aa3848 | 202 | (define_insn_reservation "x_floadtf" 6 |
f61a2c7d AK |
203 | (and (eq_attr "cpu" "z990,z9_109") |
204 | (eq_attr "type" "floadtf")) | |
f4aa3848 | 205 | "x_e1_t,x-wr-fp") |
f61a2c7d | 206 | |
f4aa3848 | 207 | (define_insn_reservation "x_floaddf" 6 |
ec24698e | 208 | (and (eq_attr "cpu" "z990,z9_109") |
cfdb984b | 209 | (eq_attr "type" "floaddf")) |
f4aa3848 | 210 | "x_e1_t,x-wr-fp") |
52609473 | 211 | |
f4aa3848 | 212 | (define_insn_reservation "x_floadsf" 6 |
ec24698e | 213 | (and (eq_attr "cpu" "z990,z9_109") |
cfdb984b | 214 | (eq_attr "type" "floadsf")) |
f4aa3848 | 215 | "x_e1_t,x-wr-fp") |
52609473 | 216 | |
f61a2c7d | 217 | |
f4aa3848 | 218 | (define_insn_reservation "x_fstoredf" 1 |
ec24698e | 219 | (and (eq_attr "cpu" "z990,z9_109") |
cfdb984b | 220 | (eq_attr "type" "fstoredf")) |
f4aa3848 | 221 | "x_e1_t,x-wr-fp") |
52609473 | 222 | |
f4aa3848 | 223 | (define_insn_reservation "x_fstoresf" 1 |
ec24698e | 224 | (and (eq_attr "cpu" "z990,z9_109") |
cfdb984b | 225 | (eq_attr "type" "fstoresf")) |
f4aa3848 | 226 | "x_e1_t,x-wr-fp") |
52609473 | 227 | |
f61a2c7d AK |
228 | |
229 | (define_insn_reservation "x_ftrunctf" 16 | |
230 | (and (eq_attr "cpu" "z990,z9_109") | |
231 | (eq_attr "type" "ftrunctf")) | |
f4aa3848 | 232 | "x_e1_t*10,x-wr-fp") |
f61a2c7d AK |
233 | |
234 | (define_insn_reservation "x_ftruncdf" 11 | |
235 | (and (eq_attr "cpu" "z990,z9_109") | |
236 | (eq_attr "type" "ftruncdf")) | |
f4aa3848 | 237 | "x_e1_t*5,x-wr-fp") |
f61a2c7d AK |
238 | |
239 | ||
f4aa3848 | 240 | (define_insn_reservation "x_ftoi" 1 |
ec24698e | 241 | (and (eq_attr "cpu" "z990,z9_109") |
52609473 | 242 | (eq_attr "type" "ftoi")) |
f4aa3848 | 243 | "x_e1_t*3,x-wr-fp") |
52609473 | 244 | |
f4aa3848 | 245 | (define_insn_reservation "x_itof" 7 |
ec24698e | 246 | (and (eq_attr "cpu" "z990,z9_109") |
9381e3f1 | 247 | (eq_attr "type" "itoftf,itofdf,itofsf")) |
f4aa3848 | 248 | "x_e1_t*3,x-wr-fp") |
52609473 | 249 | |
cfdb984b | 250 | (define_bypass 1 "x_fsimpdf" "x_fstoredf") |
52609473 | 251 | |
cfdb984b | 252 | (define_bypass 1 "x_fsimpsf" "x_fstoresf") |
52609473 | 253 | |
cfdb984b | 254 | (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf") |
f4aa3848 | 255 | |
cfdb984b | 256 | (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf") |
52609473 | 257 | |
52609473 | 258 | ;; |
f4aa3848 | 259 | ;; s390_agen_dep_p returns 1, if a register is set in the |
fae778eb | 260 | ;; first insn and used in the dependent insn to form a address. |
52609473 HP |
261 | ;; |
262 | ||
263 | ;; | |
fae778eb | 264 | ;; If an instruction uses a register to address memory, it needs |
52609473 | 265 | ;; to be set 5 cycles in advance. |
f4aa3848 | 266 | ;; |
52609473 | 267 | |
f4aa3848 | 268 | (define_bypass 5 "x_int,x_agen,x_lr" |
29a74354 | 269 | "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
52609473 HP |
270 | "s390_agen_dep_p") |
271 | ||
f4aa3848 | 272 | (define_bypass 9 "x_int,x_agen,x_lr" |
f61a2c7d | 273 | "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
cfdb984b | 274 | x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" |
52609473 HP |
275 | "s390_agen_dep_p") |
276 | ;; | |
f4aa3848 AK |
277 | ;; A load type instruction uses a bypass to feed the result back |
278 | ;; to the address generation pipeline stage. | |
52609473 HP |
279 | ;; |
280 | ||
f4aa3848 | 281 | (define_bypass 4 "x_load" |
29a74354 | 282 | "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
52609473 HP |
283 | "s390_agen_dep_p") |
284 | ||
285 | (define_bypass 5 "x_load" | |
f61a2c7d | 286 | "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
cfdb984b | 287 | x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" |
52609473 HP |
288 | "s390_agen_dep_p") |
289 | ||
290 | ;; | |
f4aa3848 AK |
291 | ;; A load address type instruction uses a bypass to feed the |
292 | ;; result back to the address generation pipeline stage. | |
52609473 HP |
293 | ;; |
294 | ||
f4aa3848 | 295 | (define_bypass 3 "x_larl,x_la" |
29a74354 | 296 | "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
52609473 HP |
297 | "s390_agen_dep_p") |
298 | ||
299 | (define_bypass 5 "x_larl, x_la" | |
f61a2c7d | 300 | "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
cfdb984b | 301 | x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" |
52609473 HP |
302 | "s390_agen_dep_p") |
303 | ||
304 | ;; | |
305 | ;; Operand forwarding | |
306 | ;; | |
307 | ||
308 | (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr") | |
309 | ||
310 |