projects / thirdparty / gcc.git / blame
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|---|---|---|
| 4d8af13f | 1 | /* Definitions of target machine for GCC, for Sun SPARC. |
| 7adcbafe | 2 | Copyright (C) 2002-2022 Free Software Foundation, Inc. |
| a5381466 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
| ff7e7ee0 | 4 | 64-bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
| a5381466 ZW |
5 | at Cygnus Support. |
| 6 | ||
| 4d8af13f | 7 | This file is part of GCC. |
| a5381466 | 8 | |
| 4d8af13f | 9 | GCC is free software; you can redistribute it and/or modify |
| a5381466 | 10 | it under the terms of the GNU General Public License as published by |
| 2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
| a5381466 ZW |
12 | any later version. |
| 13 | ||
| 4d8af13f | 14 | GCC is distributed in the hope that it will be useful, |
| a5381466 ZW |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | GNU General Public License for more details. | |
| 18 | ||
| 19 | You should have received a copy of the GNU General Public License | |
| 2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
| 21 | <http://www.gnu.org/licenses/>. */ | |
| a5381466 | 22 | |
| 94134f42 ZW |
23 | /* 128-bit floating point */ |
| 24 | FLOAT_MODE (TF, 16, ieee_quad_format); | |
| 25 | ||
| a1a7d094 EB |
26 | /* We need a 32-byte mode to return structures in the 64-bit ABI. */ |
| 27 | INT_MODE (OI, 32); | |
| 28 | ||
| a5381466 ZW |
29 | /* Add any extra modes needed to represent the condition code. |
| 30 | ||
| ff7e7ee0 EB |
31 | We have a CCNZ mode which is used for implicit comparisons with zero when |
| 32 | arithmetic instructions set the condition code. Only the N and Z flags | |
| 33 | are valid in this mode, which means that only the =,!= and <,>= operators | |
| 34 | can be used in conjunction with it. | |
| 35 | ||
| 36 | We also have a CCCmode which is used by the arithmetic instructions when | |
| 37 | they explicitly set the C flag (unsigned overflow). Only the unsigned | |
| 38 | <,>= operators can be used in conjunction with it. | |
| a5381466 | 39 | |
| 85729229 EB |
40 | We also have a CCVmode which is used by the arithmetic instructions when |
| 41 | they explicitly set the V flag (signed overflow). Only the =,!= operators | |
| 42 | can be used in conjunction with it. | |
| 43 | ||
| a5381466 ZW |
44 | We also have two modes to indicate that the relevant condition code is |
| 45 | in the floating-point condition code register. One for comparisons which | |
| 46 | will generate an exception if the result is unordered (CCFPEmode) and | |
| 47 | one for comparisons which will never trap (CCFPmode). | |
| 48 | ||
| ff7e7ee0 | 49 | CC modes are used for the 32-bit ICC, CCX modes for the 64-bit XCC. */ |
| a5381466 | 50 | |
| 94134f42 | 51 | CC_MODE (CCX); |
| ff7e7ee0 EB |
52 | CC_MODE (CCNZ); |
| 53 | CC_MODE (CCXNZ); | |
| 54 | CC_MODE (CCC); | |
| 55 | CC_MODE (CCXC); | |
| 85729229 EB |
56 | CC_MODE (CCV); |
| 57 | CC_MODE (CCXV); | |
| 94134f42 ZW |
58 | CC_MODE (CCFP); |
| 59 | CC_MODE (CCFPE); | |
| c75d6010 JM |
60 | |
| 61 | /* Vector modes. */ | |
| 856f4c6a EB |
62 | VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ |
| 63 | VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */ | |
| 64 | VECTOR_MODES (INT, 4); /* V4QI V2HI */ | |
| 65 | VECTOR_MODE (INT, DI, 1); /* V1DI */ | |
| 66 | VECTOR_MODE (INT, SI, 1); /* V1SI */ |