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1bb87f28 | 1 | /* Definitions of target machine for GNU compiler, for Sun SPARC. |
4592bdcb | 2 | Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999 |
3a7b4385 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 |
66647d44 | 4 | Free Software Foundation, Inc. |
1bb87f28 | 5 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
3e2cc1d1 | 6 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
7a6cf439 | 7 | at Cygnus Support. |
1bb87f28 | 8 | |
7ec022b2 | 9 | This file is part of GCC. |
1bb87f28 | 10 | |
7ec022b2 | 11 | GCC is free software; you can redistribute it and/or modify |
1bb87f28 | 12 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 13 | the Free Software Foundation; either version 3, or (at your option) |
1bb87f28 JW |
14 | any later version. |
15 | ||
7ec022b2 | 16 | GCC is distributed in the hope that it will be useful, |
1bb87f28 JW |
17 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | GNU General Public License for more details. | |
20 | ||
21 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
22 | along with GCC; see the file COPYING3. If not see |
23 | <http://www.gnu.org/licenses/>. */ | |
1bb87f28 | 24 | |
1910440e RS |
25 | #include "config/vxworks-dummy.h" |
26 | ||
1bb87f28 | 27 | /* Note that some other tm.h files include this one and then override |
a0a301fc DE |
28 | whatever definitions are necessary. */ |
29 | ||
18df6de9 DM |
30 | /* Define the specific costs for a given cpu */ |
31 | ||
32 | struct processor_costs { | |
33 | /* Integer load */ | |
34 | const int int_load; | |
35 | ||
36 | /* Integer signed load */ | |
37 | const int int_sload; | |
38 | ||
39 | /* Integer zeroed load */ | |
40 | const int int_zload; | |
41 | ||
42 | /* Float load */ | |
43 | const int float_load; | |
44 | ||
45 | /* fmov, fneg, fabs */ | |
46 | const int float_move; | |
47 | ||
48 | /* fadd, fsub */ | |
49 | const int float_plusminus; | |
50 | ||
51 | /* fcmp */ | |
52 | const int float_cmp; | |
53 | ||
54 | /* fmov, fmovr */ | |
55 | const int float_cmove; | |
56 | ||
57 | /* fmul */ | |
58 | const int float_mul; | |
59 | ||
60 | /* fdivs */ | |
61 | const int float_div_sf; | |
62 | ||
63 | /* fdivd */ | |
64 | const int float_div_df; | |
65 | ||
66 | /* fsqrts */ | |
67 | const int float_sqrt_sf; | |
68 | ||
69 | /* fsqrtd */ | |
70 | const int float_sqrt_df; | |
71 | ||
72 | /* umul/smul */ | |
73 | const int int_mul; | |
74 | ||
75 | /* mulX */ | |
76 | const int int_mulX; | |
77 | ||
78 | /* integer multiply cost for each bit set past the most | |
79 | significant 3, so the formula for multiply cost becomes: | |
80 | ||
81 | if (rs1 < 0) | |
82 | highest_bit = highest_clear_bit(rs1); | |
83 | else | |
84 | highest_bit = highest_set_bit(rs1); | |
85 | if (highest_bit < 3) | |
86 | highest_bit = 3; | |
87 | cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); | |
88 | ||
89 | A value of zero indicates that the multiply costs is fixed, | |
90 | and not variable. */ | |
91 | const int int_mul_bit_factor; | |
92 | ||
93 | /* udiv/sdiv */ | |
94 | const int int_div; | |
95 | ||
96 | /* divX */ | |
97 | const int int_divX; | |
98 | ||
99 | /* movcc, movr */ | |
100 | const int int_cmove; | |
101 | ||
102 | /* penalty for shifts, due to scheduling rules etc. */ | |
103 | const int shift_penalty; | |
104 | }; | |
105 | ||
106 | extern const struct processor_costs *sparc_costs; | |
107 | ||
8d12174d | 108 | #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () |
9b8466f4 | 109 | |
a0a301fc DE |
110 | /* Specify this in a cover file to provide bi-architecture (32/64) support. */ |
111 | /* #define SPARC_BI_ARCH */ | |
112 | ||
113 | /* Macro used later in this file to determine default architecture. */ | |
114 | #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) | |
7a6cf439 | 115 | |
a0a301fc DE |
116 | /* TARGET_ARCH{32,64} are the main macros to decide which of the two |
117 | architectures to compile for. We allow targets to choose compile time or | |
118 | runtime selection. */ | |
959eb758 | 119 | #ifdef IN_LIBGCC2 |
afdac905 | 120 | #if defined(__sparcv9) || defined(__arch64__) |
959eb758 DM |
121 | #define TARGET_ARCH32 0 |
122 | #else | |
123 | #define TARGET_ARCH32 1 | |
afdac905 | 124 | #endif /* sparc64 */ |
959eb758 | 125 | #else |
53f4a9f6 | 126 | #ifdef SPARC_BI_ARCH |
a0a301fc DE |
127 | #define TARGET_ARCH32 (! TARGET_64BIT) |
128 | #else | |
129 | #define TARGET_ARCH32 (DEFAULT_ARCH32_P) | |
959eb758 | 130 | #endif /* SPARC_BI_ARCH */ |
53f4a9f6 | 131 | #endif /* IN_LIBGCC2 */ |
a0a301fc DE |
132 | #define TARGET_ARCH64 (! TARGET_ARCH32) |
133 | ||
ed38d6fe EB |
134 | /* Code model selection in 64-bit environment. |
135 | ||
136 | The machine mode used for addresses is 32-bit wide: | |
137 | ||
138 | TARGET_CM_32: 32-bit address space. | |
139 | It is the code model used when generating 32-bit code. | |
140 | ||
141 | The machine mode used for addresses is 64-bit wide: | |
142 | ||
143 | TARGET_CM_MEDLOW: 32-bit address space. | |
144 | The executable must be in the low 32 bits of memory. | |
145 | This avoids generating %uhi and %ulo terms. Programs | |
146 | can be statically or dynamically linked. | |
147 | ||
148 | TARGET_CM_MEDMID: 44-bit address space. | |
149 | The executable must be in the low 44 bits of memory, | |
150 | and the %[hml]44 terms are used. The text and data | |
151 | segments have a maximum size of 2GB (31-bit span). | |
152 | The maximum offset from any instruction to the label | |
153 | _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
154 | ||
155 | TARGET_CM_MEDANY: 64-bit address space. | |
156 | The text and data segments have a maximum size of 2GB | |
157 | (31-bit span) and may be located anywhere in memory. | |
158 | The maximum offset from any instruction to the label | |
159 | _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
160 | ||
161 | TARGET_CM_EMBMEDANY: 64-bit address space. | |
162 | The text and data segments have a maximum size of 2GB | |
163 | (31-bit span) and may be located anywhere in memory. | |
164 | The global register %g4 contains the start address of | |
165 | the data segment. Programs are statically linked and | |
166 | PIC is not supported. | |
167 | ||
168 | Different code models are not supported in 32-bit environment. */ | |
a0a301fc DE |
169 | |
170 | enum cmodel { | |
171 | CM_32, | |
172 | CM_MEDLOW, | |
173 | CM_MEDMID, | |
174 | CM_MEDANY, | |
175 | CM_EMBMEDANY | |
176 | }; | |
177 | ||
a0a301fc DE |
178 | /* One of CM_FOO. */ |
179 | extern enum cmodel sparc_cmodel; | |
180 | ||
181 | /* V9 code model selection. */ | |
182 | #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) | |
183 | #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) | |
184 | #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) | |
185 | #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) | |
186 | ||
a330e73b | 187 | #define SPARC_DEFAULT_CMODEL CM_32 |
6f64bf5f | 188 | |
548a6c4f EB |
189 | /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO) |
190 | which requires the following macro to be true if enabled. Prior to V9, | |
191 | there are no instructions to even talk about memory synchronization. | |
192 | Note that the UltraSPARC III processors don't implement RMO, unlike the | |
3e64c239 DM |
193 | UltraSPARC II processors. Niagara, Niagara-2, and Niagara-3 do not |
194 | implement RMO either. | |
548a6c4f EB |
195 | |
196 | Default to false; for example, Solaris never enables RMO, only ever uses | |
197 | total memory ordering (TMO). */ | |
198 | #define SPARC_RELAXED_ORDERING false | |
199 | ||
5e77eb53 EB |
200 | /* Do not use the .note.GNU-stack convention by default. */ |
201 | #define NEED_INDICATE_EXEC_STACK 0 | |
202 | ||
a0a301fc DE |
203 | /* This is call-clobbered in the normal ABI, but is reserved in the |
204 | home grown (aka upward compatible) embedded ABI. */ | |
205 | #define EMBMEDANY_BASE_REG "%g4" | |
206 | \f | |
207 | /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, | |
208 | and specified by the user via --with-cpu=foo. | |
209 | This specifies the cpu implementation, not the architecture size. */ | |
3aabf9a5 | 210 | /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit |
8947065c | 211 | capable cpu's. */ |
2163f11b | 212 | #define TARGET_CPU_sparc 0 |
07981468 KE |
213 | #define TARGET_CPU_v7 0 /* alias */ |
214 | #define TARGET_CPU_cypress 0 /* alias */ | |
215 | #define TARGET_CPU_v8 1 /* generic v8 implementation */ | |
216 | #define TARGET_CPU_supersparc 2 | |
217 | #define TARGET_CPU_hypersparc 3 | |
218 | #define TARGET_CPU_leon 4 | |
219 | #define TARGET_CPU_sparclite 5 | |
220 | #define TARGET_CPU_f930 5 /* alias */ | |
221 | #define TARGET_CPU_f934 5 /* alias */ | |
8947065c | 222 | #define TARGET_CPU_sparclite86x 6 |
07981468 KE |
223 | #define TARGET_CPU_sparclet 7 |
224 | #define TARGET_CPU_tsc701 7 /* alias */ | |
225 | #define TARGET_CPU_v9 8 /* generic v9 implementation */ | |
226 | #define TARGET_CPU_sparcv9 8 /* alias */ | |
227 | #define TARGET_CPU_sparc64 8 /* alias */ | |
228 | #define TARGET_CPU_ultrasparc 9 | |
229 | #define TARGET_CPU_ultrasparc3 10 | |
230 | #define TARGET_CPU_niagara 11 | |
231 | #define TARGET_CPU_niagara2 12 | |
3e64c239 DM |
232 | #define TARGET_CPU_niagara3 13 |
233 | #define TARGET_CPU_niagara4 14 | |
bafb031b | 234 | |
8947065c | 235 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ |
fae15c93 | 236 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ |
4c837a1e | 237 | || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ |
9eeaed6e | 238 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ |
3e64c239 DM |
239 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ |
240 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ | |
241 | || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 | |
345a6161 DM |
242 | |
243 | #define CPP_CPU32_DEFAULT_SPEC "" | |
244 | #define ASM_CPU32_DEFAULT_SPEC "" | |
245 | ||
a0a301fc | 246 | #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 |
bafb031b | 247 | /* ??? What does Sun's CC pass? */ |
345a6161 | 248 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
bafb031b DE |
249 | /* ??? It's not clear how other assemblers will handle this, so by default |
250 | use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
251 | is handled in sol2.h. */ | |
345a6161 | 252 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" |
bafb031b | 253 | #endif |
a0a301fc | 254 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc |
345a6161 DM |
255 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" |
256 | #define ASM_CPU64_DEFAULT_SPEC "-Av9a" | |
257 | #endif | |
fae15c93 VM |
258 | #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 |
259 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
260 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
261 | #endif | |
4c837a1e DM |
262 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara |
263 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
264 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
265 | #endif | |
9eeaed6e DM |
266 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 |
267 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
268 | #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
269 | #endif | |
3e64c239 DM |
270 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 |
271 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
e8b141b5 | 272 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG |
3e64c239 DM |
273 | #endif |
274 | #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 | |
275 | #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
e8b141b5 | 276 | #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG |
3e64c239 | 277 | #endif |
345a6161 DM |
278 | |
279 | #else | |
280 | ||
281 | #define CPP_CPU64_DEFAULT_SPEC "" | |
282 | #define ASM_CPU64_DEFAULT_SPEC "" | |
283 | ||
8947065c RH |
284 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ |
285 | || TARGET_CPU_DEFAULT == TARGET_CPU_v8 | |
345a6161 DM |
286 | #define CPP_CPU32_DEFAULT_SPEC "" |
287 | #define ASM_CPU32_DEFAULT_SPEC "" | |
288 | #endif | |
8947065c | 289 | |
345a6161 DM |
290 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet |
291 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" | |
292 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" | |
bafb031b | 293 | #endif |
8947065c | 294 | |
345a6161 DM |
295 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite |
296 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" | |
297 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
298 | #endif | |
299 | ||
07981468 KE |
300 | #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x |
301 | #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" | |
302 | #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
303 | #endif | |
304 | ||
8947065c RH |
305 | #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc |
306 | #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" | |
307 | #define ASM_CPU32_DEFAULT_SPEC "" | |
308 | #endif | |
309 | ||
310 | #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc | |
311 | #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" | |
312 | #define ASM_CPU32_DEFAULT_SPEC "" | |
313 | #endif | |
314 | ||
07981468 KE |
315 | #if TARGET_CPU_DEFAULT == TARGET_CPU_leon |
316 | #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" | |
317 | #define ASM_CPU32_DEFAULT_SPEC "" | |
8947065c RH |
318 | #endif |
319 | ||
345a6161 DM |
320 | #endif |
321 | ||
322 | #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) | |
3aabf9a5 | 323 | #error Unrecognized value in TARGET_CPU_DEFAULT. |
bafb031b DE |
324 | #endif |
325 | ||
345a6161 DM |
326 | #ifdef SPARC_BI_ARCH |
327 | ||
328 | #define CPP_CPU_DEFAULT_SPEC \ | |
329 | (DEFAULT_ARCH32_P ? "\ | |
330 | %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ | |
331 | %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ | |
332 | " : "\ | |
333 | %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ | |
334 | %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ | |
335 | ") | |
336 | #define ASM_CPU_DEFAULT_SPEC \ | |
337 | (DEFAULT_ARCH32_P ? "\ | |
338 | %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ | |
339 | %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ | |
340 | " : "\ | |
341 | %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ | |
342 | %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ | |
343 | ") | |
344 | ||
345 | #else /* !SPARC_BI_ARCH */ | |
346 | ||
347 | #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) | |
348 | #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) | |
349 | ||
350 | #endif /* !SPARC_BI_ARCH */ | |
351 | ||
885d8175 | 352 | /* Define macros to distinguish architectures. */ |
857458c4 | 353 | |
bafb031b DE |
354 | /* Common CPP definitions used by CPP_SPEC amongst the various targets |
355 | for handling -mcpu=xxx switches. */ | |
356 | #define CPP_CPU_SPEC "\ | |
9b7c06d2 | 357 | %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ |
bafb031b DE |
358 | %{mcpu=sparclite:-D__sparclite__} \ |
359 | %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
07981468 | 360 | %{mcpu=sparclite86x:-D__sparclite86x__} \ |
bafb031b DE |
361 | %{mcpu=v8:-D__sparc_v8__} \ |
362 | %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
8947065c | 363 | %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ |
07981468 | 364 | %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ |
bafb031b DE |
365 | %{mcpu=v9:-D__sparc_v9__} \ |
366 | %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
fae15c93 | 367 | %{mcpu=ultrasparc3:-D__sparc_v9__} \ |
4c837a1e | 368 | %{mcpu=niagara:-D__sparc_v9__} \ |
9eeaed6e | 369 | %{mcpu=niagara2:-D__sparc_v9__} \ |
3e64c239 DM |
370 | %{mcpu=niagara3:-D__sparc_v9__} \ |
371 | %{mcpu=niagara4:-D__sparc_v9__} \ | |
3a7b4385 | 372 | %{!mcpu*:%(cpp_cpu_default)} \ |
7a6cf439 | 373 | " |
9b8466f4 NB |
374 | #define CPP_ARCH32_SPEC "" |
375 | #define CPP_ARCH64_SPEC "-D__arch64__" | |
345a6161 | 376 | |
a0a301fc DE |
377 | #define CPP_ARCH_DEFAULT_SPEC \ |
378 | (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) | |
379 | ||
380 | #define CPP_ARCH_SPEC "\ | |
381 | %{m32:%(cpp_arch32)} \ | |
382 | %{m64:%(cpp_arch64)} \ | |
383 | %{!m32:%{!m64:%(cpp_arch_default)}} \ | |
384 | " | |
385 | ||
b11b0904 EB |
386 | /* Macros to distinguish the endianness, window model and FP support. */ |
387 | #define CPP_OTHER_SPEC "\ | |
388 | %{mlittle-endian:-D__LITTLE_ENDIAN__} \ | |
389 | %{mflat:-D_FLAT} \ | |
390 | %{msoft-float:-D_SOFT_FLOAT} \ | |
391 | " | |
a0a301fc DE |
392 | |
393 | /* Macros to distinguish the particular subtarget. */ | |
394 | #define CPP_SUBTARGET_SPEC "" | |
395 | ||
b11b0904 EB |
396 | #define CPP_SPEC \ |
397 | "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" | |
a0a301fc | 398 | |
b1fc14e5 RS |
399 | /* This used to translate -dalign to -malign, but that is no good |
400 | because it can't turn off the usual meaning of making debugging dumps. */ | |
bafb031b | 401 | |
f2060fbe | 402 | #define CC1_SPEC "" |
bafb031b | 403 | |
bafb031b DE |
404 | /* Override in target specific files. */ |
405 | #define ASM_CPU_SPEC "\ | |
9b7c06d2 | 406 | %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ |
bafb031b | 407 | %{mcpu=sparclite:-Asparclite} \ |
8d72ec32 | 408 | %{mcpu=sparclite86x:-Asparclite} \ |
bafb031b | 409 | %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ |
284d86e9 | 410 | %{mv8plus:-Av8plus} \ |
bafb031b | 411 | %{mcpu=v9:-Av9} \ |
284d86e9 | 412 | %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ |
fae15c93 | 413 | %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ |
4c837a1e | 414 | %{mcpu=niagara:%{!mv8plus:-Av9b}} \ |
9eeaed6e | 415 | %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ |
e8b141b5 DM |
416 | %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ |
417 | %{mcpu=niagara4:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ | |
3a7b4385 | 418 | %{!mcpu*:%(asm_cpu_default)} \ |
bafb031b DE |
419 | " |
420 | ||
e632a26c DE |
421 | /* Word size selection, among other things. |
422 | This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ | |
423 | ||
a0a301fc | 424 | #define ASM_ARCH32_SPEC "-32" |
6149cebb JJ |
425 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP |
426 | #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" | |
427 | #else | |
a0a301fc | 428 | #define ASM_ARCH64_SPEC "-64" |
6149cebb | 429 | #endif |
a0a301fc | 430 | #define ASM_ARCH_DEFAULT_SPEC \ |
e632a26c | 431 | (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) |
a0a301fc DE |
432 | |
433 | #define ASM_ARCH_SPEC "\ | |
434 | %{m32:%(asm_arch32)} \ | |
435 | %{m64:%(asm_arch64)} \ | |
436 | %{!m32:%{!m64:%(asm_arch_default)}} \ | |
437 | " | |
438 | ||
e95b1e6a JJ |
439 | #ifdef HAVE_AS_RELAX_OPTION |
440 | #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" | |
441 | #else | |
442 | #define ASM_RELAX_SPEC "" | |
443 | #endif | |
444 | ||
a0a301fc DE |
445 | /* Special flags to the Sun-4 assembler when using pipe for input. */ |
446 | ||
447 | #define ASM_SPEC "\ | |
6d721f67 | 448 | %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \ |
e95b1e6a | 449 | %(asm_cpu) %(asm_relax)" |
a0a301fc | 450 | |
bafb031b DE |
451 | /* This macro defines names of additional specifications to put in the specs |
452 | that can be used in various specifications like CC1_SPEC. Its definition | |
453 | is an initializer with a subgrouping for each command option. | |
454 | ||
455 | Each subgrouping contains a string constant, that defines the | |
7ec022b2 | 456 | specification name, and a string constant that used by the GCC driver |
bafb031b DE |
457 | program. |
458 | ||
459 | Do not define this macro if it does not need to do anything. */ | |
1bb87f28 | 460 | |
a0a301fc | 461 | #define EXTRA_SPECS \ |
829245be KG |
462 | { "cpp_cpu", CPP_CPU_SPEC }, \ |
463 | { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
464 | { "cpp_arch32", CPP_ARCH32_SPEC }, \ | |
465 | { "cpp_arch64", CPP_ARCH64_SPEC }, \ | |
466 | { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ | |
467 | { "cpp_arch", CPP_ARCH_SPEC }, \ | |
b11b0904 | 468 | { "cpp_other", CPP_OTHER_SPEC }, \ |
829245be KG |
469 | { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ |
470 | { "asm_cpu", ASM_CPU_SPEC }, \ | |
471 | { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ | |
472 | { "asm_arch32", ASM_ARCH32_SPEC }, \ | |
473 | { "asm_arch64", ASM_ARCH64_SPEC }, \ | |
e95b1e6a | 474 | { "asm_relax", ASM_RELAX_SPEC }, \ |
829245be KG |
475 | { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ |
476 | { "asm_arch", ASM_ARCH_SPEC }, \ | |
bafb031b | 477 | SUBTARGET_EXTRA_SPECS |
1bb87f28 | 478 | |
bafb031b | 479 | #define SUBTARGET_EXTRA_SPECS |
bbd7687d DM |
480 | |
481 | /* Because libgcc can generate references back to libc (via .umul etc.) we have | |
482 | to list libc again after the second libgcc. */ | |
483 | #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" | |
484 | ||
bafb031b | 485 | \f |
82d6b402 RH |
486 | #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") |
487 | #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") | |
7a6cf439 DE |
488 | |
489 | /* ??? This should be 32 bits for v9 but what can we do? */ | |
1bb87f28 JW |
490 | #define WCHAR_TYPE "short unsigned int" |
491 | #define WCHAR_TYPE_SIZE 16 | |
7a6cf439 | 492 | \f |
bafb031b DE |
493 | /* Mask of all CPU selection flags. */ |
494 | #define MASK_ISA \ | |
495 | (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) | |
6f64bf5f | 496 | |
284d86e9 JC |
497 | /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y. |
498 | TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y | |
499 | to get high 32 bits. False in V8+ or V9 because multiply stores | |
a7b376ee | 500 | a 64-bit result in a register. */ |
284d86e9 | 501 | |
bfd6bc60 JC |
502 | #define TARGET_HARD_MUL32 \ |
503 | ((TARGET_V8 || TARGET_SPARCLITE \ | |
504 | || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \ | |
5cb01b65 | 505 | && ! TARGET_V8PLUS && TARGET_ARCH32) |
bfd6bc60 JC |
506 | |
507 | #define TARGET_HARD_MUL \ | |
508 | (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ | |
3aabf9a5 | 509 | || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) |
bfd6bc60 | 510 | |
bafb031b DE |
511 | /* MASK_APP_REGS must always be the default because that's what |
512 | FIXED_REGISTERS is set to and -ffixed- is processed before | |
5efd84c5 NF |
513 | TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process |
514 | -mno-app-regs). */ | |
33074e5f | 515 | #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) |
84ab3bfb | 516 | |
6afca97d DE |
517 | /* Recast the cpu class to be the cpu attribute. |
518 | Every file includes us, but not every file includes insn-attr.h. */ | |
519 | #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) | |
bafb031b | 520 | |
7816bea0 DJ |
521 | /* Support for a compile-time default CPU, et cetera. The rules are: |
522 | --with-cpu is ignored if -mcpu is specified. | |
523 | --with-tune is ignored if -mtune is specified. | |
524 | --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu | |
525 | are specified. */ | |
526 | #define OPTION_DEFAULT_SPECS \ | |
527 | {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
528 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ | |
c6869789 | 529 | {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } |
7a6cf439 DE |
530 | \f |
531 | /* target machine storage layout */ | |
532 | ||
1bb87f28 JW |
533 | /* Define this if most significant bit is lowest numbered |
534 | in instructions that operate on numbered bit-fields. */ | |
535 | #define BITS_BIG_ENDIAN 1 | |
536 | ||
537 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
1bb87f28 JW |
538 | #define BYTES_BIG_ENDIAN 1 |
539 | ||
540 | /* Define this if most significant word of a multiword number is the lowest | |
541 | numbered. */ | |
1bb87f28 JW |
542 | #define WORDS_BIG_ENDIAN 1 |
543 | ||
7a6cf439 | 544 | #define MAX_BITS_PER_WORD 64 |
1bb87f28 JW |
545 | |
546 | /* Width of a word, in units (bytes). */ | |
6f64bf5f | 547 | #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) |
8b156b3e JJ |
548 | #ifdef IN_LIBGCC2 |
549 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
550 | #else | |
ef0e53ce | 551 | #define MIN_UNITS_PER_WORD 4 |
8b156b3e | 552 | #endif |
7a6cf439 DE |
553 | |
554 | /* Now define the sizes of the C data types. */ | |
555 | ||
556 | #define SHORT_TYPE_SIZE 16 | |
a0a301fc DE |
557 | #define INT_TYPE_SIZE 32 |
558 | #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) | |
7a6cf439 DE |
559 | #define LONG_LONG_TYPE_SIZE 64 |
560 | #define FLOAT_TYPE_SIZE 32 | |
561 | #define DOUBLE_TYPE_SIZE 64 | |
a2cd689a | 562 | |
9e1395f1 JM |
563 | /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the |
564 | SPARC ABI says that it is 128-bit wide. */ | |
565 | /* #define LONG_DOUBLE_TYPE_SIZE 128 */ | |
1bb87f28 | 566 | |
a2cd689a EB |
567 | /* The widest floating-point format really supported by the hardware. */ |
568 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
569 | ||
baa48dfa | 570 | /* Width in bits of a pointer. This is the size of ptr_mode. */ |
7a6cf439 | 571 | #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
1bb87f28 | 572 | |
baa48dfa PB |
573 | /* This is the machine mode used for addresses. */ |
574 | #define Pmode (TARGET_ARCH64 ? DImode : SImode) | |
575 | ||
3276910d RK |
576 | /* If we have to extend pointers (only when TARGET_ARCH64 and not |
577 | TARGET_PTR64), we want to do it unsigned. This macro does nothing | |
578 | if ptr_mode and Pmode are the same. */ | |
579 | #define POINTERS_EXTEND_UNSIGNED 1 | |
580 | ||
1bb87f28 | 581 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
6f64bf5f | 582 | #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
583 | |
584 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
a594a19c | 585 | /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because |
2358ff91 | 586 | then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ |
6f64bf5f | 587 | #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) |
2358ff91 | 588 | /* Temporary hack until the FIXME above is fixed. */ |
a594a19c | 589 | #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) |
1bb87f28 | 590 | |
10d1b70f JW |
591 | /* ALIGN FRAMES on double word boundaries */ |
592 | ||
7a6cf439 | 593 | #define SPARC_STACK_ALIGN(LOC) \ |
6f64bf5f | 594 | (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7)) |
10d1b70f | 595 | |
1bb87f28 | 596 | /* Allocation boundary (in *bits*) for the code of a function. */ |
efa3896a | 597 | #define FUNCTION_BOUNDARY 32 |
1bb87f28 JW |
598 | |
599 | /* Alignment of field after `int : 0' in a structure. */ | |
6f64bf5f | 600 | #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) |
1bb87f28 JW |
601 | |
602 | /* Every structure's size must be a multiple of this. */ | |
603 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
604 | ||
43a88a8c | 605 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
1bb87f28 JW |
606 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
607 | ||
608 | /* No data type wants to be aligned rounder than this. */ | |
6f64bf5f | 609 | #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) |
1bb87f28 | 610 | |
77a02b01 JW |
611 | /* The best alignment to use in cases where we have a choice. */ |
612 | #define FASTEST_ALIGNMENT 64 | |
613 | ||
c219ddf7 BK |
614 | /* Define this macro as an expression for the alignment of a structure |
615 | (given by STRUCT as a tree node) if the alignment computed in the | |
616 | usual way is COMPUTED and the alignment explicitly specified was | |
617 | SPECIFIED. | |
618 | ||
619 | The default is to use SPECIFIED if it is larger; otherwise, use | |
620 | the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ | |
621 | #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ | |
622 | (TARGET_FASTER_STRUCTS ? \ | |
623 | ((TREE_CODE (STRUCT) == RECORD_TYPE \ | |
624 | || TREE_CODE (STRUCT) == UNION_TYPE \ | |
625 | || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ | |
626 | && TYPE_FIELDS (STRUCT) != 0 \ | |
627 | ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ | |
628 | : MAX ((COMPUTED), (SPECIFIED))) \ | |
629 | : MAX ((COMPUTED), (SPECIFIED))) | |
630 | ||
0a222ba7 EB |
631 | /* We need 2 words, so we can save the stack pointer and the return register |
632 | of the function containing a non-local goto target. */ | |
633 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
634 | ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) | |
635 | ||
1bb87f28 JW |
636 | /* Make strings word-aligned so strcpy from constants will be faster. */ |
637 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ | |
d2a8e680 RS |
638 | ((TREE_CODE (EXP) == STRING_CST \ |
639 | && (ALIGN) < FASTEST_ALIGNMENT) \ | |
640 | ? FASTEST_ALIGNMENT : (ALIGN)) | |
1bb87f28 JW |
641 | |
642 | /* Make arrays of chars word-aligned for the same reasons. */ | |
643 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
644 | (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
645 | && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
77a02b01 | 646 | && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) |
1bb87f28 | 647 | |
9eb061d7 AL |
648 | /* Make local arrays of chars word-aligned for the same reasons. */ |
649 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) | |
650 | ||
b4ac57ab | 651 | /* Set this nonzero if move instructions will actually fail to work |
1bb87f28 | 652 | when given unaligned data. */ |
b4ac57ab | 653 | #define STRICT_ALIGNMENT 1 |
1bb87f28 JW |
654 | |
655 | /* Things that must be doubleword aligned cannot go in the text section, | |
656 | because the linker fails to align the text section enough! | |
7a6cf439 | 657 | Put them in the data section. This macro is only used in this file. */ |
1bb87f28 | 658 | #define MAX_TEXT_ALIGN 32 |
1bb87f28 JW |
659 | \f |
660 | /* Standard register usage. */ | |
661 | ||
662 | /* Number of actual hardware registers. | |
663 | The hardware registers are assigned numbers for the compiler | |
664 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
665 | All registers that the compiler knows about must be given numbers, | |
666 | even those that are not normally considered general registers. | |
667 | ||
7a6cf439 | 668 | SPARC has 32 integer registers and 32 floating point registers. |
a7b376ee | 669 | 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not |
7a6cf439 | 670 | accessible. We still account for them to simplify register computations |
112cdef5 | 671 | (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so |
7a6cf439 | 672 | 32+32+32+4 == 100. |
563c12b0 RH |
673 | Register 100 is used as the integer condition code register. |
674 | Register 101 is used as the soft frame pointer register. */ | |
1bb87f28 | 675 | |
10b859c0 | 676 | #define FIRST_PSEUDO_REGISTER 103 |
6afca97d | 677 | |
4fb4e4b8 | 678 | #define SPARC_FIRST_FP_REG 32 |
6afca97d | 679 | /* Additional V9 fp regs. */ |
4fb4e4b8 DE |
680 | #define SPARC_FIRST_V9_FP_REG 64 |
681 | #define SPARC_LAST_V9_FP_REG 95 | |
c4ce6853 DE |
682 | /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ |
683 | #define SPARC_FIRST_V9_FCC_REG 96 | |
684 | #define SPARC_LAST_V9_FCC_REG 99 | |
685 | /* V8 fcc reg. */ | |
686 | #define SPARC_FCC_REG 96 | |
687 | /* Integer CC reg. We don't distinguish %icc from %xcc. */ | |
688 | #define SPARC_ICC_REG 100 | |
10b859c0 | 689 | #define SPARC_GSR_REG 102 |
1bb87f28 | 690 | |
4fb4e4b8 DE |
691 | /* Nonzero if REGNO is an fp reg. */ |
692 | #define SPARC_FP_REG_P(REGNO) \ | |
693 | ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) | |
694 | ||
695 | /* Argument passing regs. */ | |
696 | #define SPARC_OUTGOING_INT_ARG_FIRST 8 | |
b11b0904 | 697 | #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) |
4fb4e4b8 DE |
698 | #define SPARC_FP_ARG_FIRST 32 |
699 | ||
1bb87f28 JW |
700 | /* 1 for registers that have pervasive standard uses |
701 | and are not available for the register allocator. | |
4fb4e4b8 | 702 | |
7a6cf439 | 703 | On non-v9 systems: |
34ad7aaf JW |
704 | g1 is free to use as temporary. |
705 | g2-g4 are reserved for applications. Gcc normally uses them as | |
706 | temporaries, but this can be disabled via the -mno-app-regs option. | |
7a6cf439 | 707 | g5 through g7 are reserved for the operating system. |
4fb4e4b8 | 708 | |
7a6cf439 | 709 | On v9 systems: |
a0a301fc DE |
710 | g1,g5 are free to use as temporaries, and are free to use between calls |
711 | if the call is to an external function via the PLT. | |
712 | g4 is free to use as a temporary in the non-embedded case. | |
713 | g4 is reserved in the embedded case. | |
4fb4e4b8 | 714 | g2-g3 are reserved for applications. Gcc normally uses them as |
bafb031b | 715 | temporaries, but this can be disabled via the -mno-app-regs option. |
a0a301fc DE |
716 | g6-g7 are reserved for the operating system (or application in |
717 | embedded case). | |
7a6cf439 DE |
718 | ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must |
719 | currently be a fixed register until this pattern is rewritten. | |
720 | Register 1 is also used when restoring call-preserved registers in large | |
6afca97d DE |
721 | stack frames. |
722 | ||
723 | Registers fixed in arch32 and not arch64 (or vice-versa) are marked in | |
5efd84c5 | 724 | TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. |
6afca97d | 725 | */ |
7a6cf439 | 726 | |
7a6cf439 | 727 | #define FIXED_REGISTERS \ |
e48addee | 728 | {1, 0, 2, 2, 2, 2, 1, 1, \ |
7a6cf439 DE |
729 | 0, 0, 0, 0, 0, 0, 1, 0, \ |
730 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
b11b0904 | 731 | 0, 0, 0, 0, 0, 0, 0, 1, \ |
7a6cf439 DE |
732 | \ |
733 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
734 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
735 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
736 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
737 | \ | |
738 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
739 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
740 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
741 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
742 | \ | |
10b859c0 | 743 | 0, 0, 0, 0, 0, 1, 1} |
1bb87f28 JW |
744 | |
745 | /* 1 for registers not available across function calls. | |
746 | These must include the FIXED_REGISTERS and also any | |
747 | registers that can be used without being saved. | |
748 | The latter must include the registers where values are returned | |
749 | and the register where structure-value addresses are passed. | |
750 | Aside from that, you can include as many other registers as you like. */ | |
7a6cf439 | 751 | |
bafb031b DE |
752 | #define CALL_USED_REGISTERS \ |
753 | {1, 1, 1, 1, 1, 1, 1, 1, \ | |
754 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
755 | 0, 0, 0, 0, 0, 0, 0, 0, \ | |
b11b0904 | 756 | 0, 0, 0, 0, 0, 0, 0, 1, \ |
bafb031b DE |
757 | \ |
758 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
759 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
760 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
761 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
762 | \ | |
763 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
764 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
765 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
766 | 1, 1, 1, 1, 1, 1, 1, 1, \ | |
767 | \ | |
10b859c0 | 768 | 1, 1, 1, 1, 1, 1, 1} |
1bb87f28 JW |
769 | |
770 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
771 | to hold something of mode MODE. | |
772 | This is ordinarily the length in words of a value of mode MODE | |
773 | but can be less for certain modes in special long registers. | |
774 | ||
775 | On SPARC, ordinary registers hold 32 bits worth; | |
776 | this means both integer and floating point registers. | |
7a6cf439 DE |
777 | On v9, integer regs hold 64 bits worth; floating point regs hold |
778 | 32 bits worth (this includes the new fp regs as even the odd ones are | |
779 | included in the hard register count). */ | |
1bb87f28 | 780 | |
7a6cf439 | 781 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
10b859c0 DM |
782 | ((REGNO) == SPARC_GSR_REG ? 1 : \ |
783 | (TARGET_ARCH64 \ | |
784 | ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \ | |
785 | ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \ | |
786 | : (GET_MODE_SIZE (MODE) + 3) / 4) \ | |
787 | : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) | |
1bb87f28 | 788 | |
fae778eb | 789 | /* Due to the ARCH64 discrepancy above we must override this next |
ec8e621d | 790 | macro too. */ |
ddef6bc7 JJ |
791 | #define REGMODE_NATURAL_SIZE(MODE) \ |
792 | ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD) | |
284d86e9 | 793 | |
1bb87f28 | 794 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. |
923a8d06 | 795 | See sparc.c for how we initialize this. */ |
0b5826ac | 796 | extern const int *hard_regno_mode_classes; |
7a6cf439 | 797 | extern int sparc_mode_class[]; |
ddef6bc7 JJ |
798 | |
799 | /* ??? Because of the funny way we pass parameters we should allow certain | |
800 | ??? types of float/complex values to be in integer registers during | |
801 | ??? RTL generation. This only matters on arch32. */ | |
1bb87f28 | 802 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
7a6cf439 | 803 | ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0) |
1bb87f28 | 804 | |
e31a1967 EB |
805 | /* Value is 1 if it is OK to rename a hard register FROM to another hard |
806 | register TO. We cannot rename %g1 as it may be used before the save | |
807 | register window instruction in the prologue. */ | |
808 | #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) | |
809 | ||
1bb87f28 JW |
810 | /* Value is 1 if it is a good idea to tie two pseudo registers |
811 | when one has mode MODE1 and one has mode MODE2. | |
812 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
7a6cf439 DE |
813 | for any hard reg, then this must be 0 for correct output. |
814 | ||
815 | For V9: SFmode can't be combined with other float modes, because they can't | |
816 | be allocated to the %d registers. Also, DFmode won't fit in odd %f | |
817 | registers, but SFmode will. */ | |
1bb87f28 | 818 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
7a6cf439 DE |
819 | ((MODE1) == (MODE2) \ |
820 | || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ | |
821 | && (! TARGET_V9 \ | |
822 | || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \ | |
823 | || (MODE1 != SFmode && MODE2 != SFmode))))) | |
1bb87f28 JW |
824 | |
825 | /* Specify the registers used for certain standard purposes. | |
826 | The values of these macros are register numbers. */ | |
827 | ||
1bb87f28 JW |
828 | /* Register to use for pushing function arguments. */ |
829 | #define STACK_POINTER_REGNUM 14 | |
830 | ||
563c12b0 RH |
831 | /* The stack bias (amount by which the hardware register is offset by). */ |
832 | #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) | |
833 | ||
4fb4e4b8 | 834 | /* Actual top-of-stack address is 92/176 greater than the contents of the |
7a6cf439 DE |
835 | stack pointer register for !v9/v9. That is: |
836 | - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
4fb4e4b8 DE |
837 | address, and 6*4 bytes for the 6 register parameters. |
838 | - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer | |
839 | parameter regs. */ | |
563c12b0 | 840 | #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) |
1ccfa253 | 841 | |
1bb87f28 | 842 | /* Base register for access to local variables of the function. */ |
563c12b0 RH |
843 | #define HARD_FRAME_POINTER_REGNUM 30 |
844 | ||
845 | /* The soft frame pointer does not have the stack bias applied. */ | |
846 | #define FRAME_POINTER_REGNUM 101 | |
847 | ||
848 | /* Given the stack bias, the stack pointer isn't actually aligned. */ | |
849 | #define INIT_EXPANDERS \ | |
850 | do { \ | |
3e029763 | 851 | if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \ |
563c12b0 RH |
852 | { \ |
853 | REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
854 | REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
855 | } \ | |
856 | } while (0) | |
1bb87f28 | 857 | |
1bb87f28 | 858 | /* Base register for access to arguments of the function. */ |
5c56efde | 859 | #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM |
1bb87f28 | 860 | |
6098b63e | 861 | /* Register in which static-chain is passed to a function. This must |
c8392688 | 862 | not be a register used by the prologue. */ |
6f64bf5f | 863 | #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) |
1bb87f28 | 864 | |
a6fed83f EB |
865 | /* Register which holds the global offset table, if any. */ |
866 | ||
867 | #define GLOBAL_OFFSET_TABLE_REGNUM 23 | |
868 | ||
1bb87f28 JW |
869 | /* Register which holds offset table for position-independent |
870 | data references. */ | |
871 | ||
a6fed83f EB |
872 | #define PIC_OFFSET_TABLE_REGNUM \ |
873 | (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) | |
1bb87f28 | 874 | |
82d6b402 RH |
875 | /* Pick a default value we can notice from override_options: |
876 | !v9: Default is on. | |
7a946186 AT |
877 | v9: Default is off. |
878 | Originally it was -1, but later on the container of options changed to | |
879 | unsigned byte, so we decided to pick 127 as default value, which does | |
880 | reflect an undefined default value in case of 0/1. */ | |
82d6b402 | 881 | |
7a946186 | 882 | #define DEFAULT_PCC_STRUCT_RETURN 127 |
82d6b402 | 883 | |
1bb87f28 JW |
884 | /* Functions which return large structures get the address |
885 | to place the wanted value at offset 64 from the frame. | |
7a6cf439 DE |
886 | Must reserve 64 bytes for the in and local registers. |
887 | v9: Functions which return large structures get the address to place the | |
888 | wanted value from an invisible first argument. */ | |
1bb87f28 | 889 | #define STRUCT_VALUE_OFFSET 64 |
1bb87f28 JW |
890 | \f |
891 | /* Define the classes of registers for register constraints in the | |
892 | machine description. Also define ranges of constants. | |
893 | ||
894 | One of the classes must always be named ALL_REGS and include all hard regs. | |
895 | If there is more than one class, another class must be named NO_REGS | |
896 | and contain no registers. | |
897 | ||
898 | The name GENERAL_REGS must be the name of a class (or an alias for | |
899 | another name such as ALL_REGS). This is the class of registers | |
900 | that is allowed by "g" or "r" in a register constraint. | |
901 | Also, registers outside this class are allocated only when | |
902 | instructions express preferences for them. | |
903 | ||
904 | The classes must be numbered in nondecreasing order; that is, | |
905 | a larger-numbered class must never be contained completely | |
906 | in a smaller-numbered class. | |
907 | ||
908 | For any two classes, it is very desirable that there be another | |
909 | class that represents their union. */ | |
910 | ||
4fb4e4b8 DE |
911 | /* The SPARC has various kinds of registers: general, floating point, |
912 | and condition codes [well, it has others as well, but none that we | |
913 | care directly about]. | |
24b63396 JW |
914 | |
915 | For v9 we must distinguish between the upper and lower floating point | |
916 | registers because the upper ones can't hold SFmode values. | |
917 | HARD_REGNO_MODE_OK won't help here because reload assumes that register(s) | |
918 | satisfying a group need for a class will also satisfy a single need for | |
919 | that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp | |
920 | regs. | |
921 | ||
922 | It is important that one class contains all the general and all the standard | |
923 | fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
924 | because reg_class_record() will bias the selection in favor of fp regs, | |
925 | because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
926 | because FP_REGS > GENERAL_REGS. | |
927 | ||
107a4b41 NS |
928 | It is also important that one class contain all the general and all |
929 | the fp regs. Otherwise when spilling a DFmode reg, it may be from | |
930 | EXTRA_FP_REGS but find_reloads() may use class | |
931 | GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die | |
932 | because the compiler thinks it doesn't have a spill reg when in | |
933 | fact it does. | |
24b63396 | 934 | |
7a6cf439 DE |
935 | v9 also has 4 floating point condition code registers. Since we don't |
936 | have a class that is the union of FPCC_REGS with either of the others, | |
937 | it is important that it appear first. Otherwise the compiler will die | |
938 | trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
c4ce6853 DE |
939 | constraints. |
940 | ||
941 | It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine | |
942 | may try to use it to hold an SImode value. See register_operand. | |
956d6950 | 943 | ??? Should %fcc[0123] be handled similarly? |
c4ce6853 | 944 | */ |
7a6cf439 | 945 | |
284d86e9 JC |
946 | enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, |
947 | EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
7a6cf439 | 948 | ALL_REGS, LIM_REG_CLASSES }; |
1bb87f28 JW |
949 | |
950 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
951 | ||
80ffc95e | 952 | /* Give names of register classes as strings for dump file. */ |
1bb87f28 JW |
953 | |
954 | #define REG_CLASS_NAMES \ | |
284d86e9 JC |
955 | { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ |
956 | "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ | |
957 | "ALL_REGS" } | |
1bb87f28 JW |
958 | |
959 | /* Define which registers fit in which classes. | |
960 | This is an initializer for a vector of HARD_REG_SET | |
961 | of length N_REG_CLASSES. */ | |
962 | ||
563c12b0 RH |
963 | #define REG_CLASS_CONTENTS \ |
964 | {{0, 0, 0, 0}, /* NO_REGS */ \ | |
965 | {0, 0, 0, 0xf}, /* FPCC_REGS */ \ | |
966 | {0xffff, 0, 0, 0}, /* I64_REGS */ \ | |
967 | {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ | |
968 | {0, -1, 0, 0}, /* FP_REGS */ \ | |
969 | {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ | |
970 | {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ | |
971 | {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ | |
10b859c0 | 972 | {-1, -1, -1, 0x7f}} /* ALL_REGS */ |
1bb87f28 | 973 | |
948bf106 EB |
974 | /* The same information, inverted: |
975 | Return the class number of the smallest class containing | |
976 | reg number REGNO. This could be a conditional expression | |
977 | or could index an array. */ | |
978 | ||
979 | extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; | |
980 | ||
981 | #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] | |
982 | ||
1b4bda70 EB |
983 | /* Defines invalid mode changes. Borrowed from pa64-regs.h. |
984 | ||
985 | SImode loads to floating-point registers are not zero-extended. | |
986 | The definition for LOAD_EXTEND_OP specifies that integer loads | |
987 | narrower than BITS_PER_WORD will be zero-extended. As a result, | |
988 | we inhibit changes from SImode unless they are to a mode that is | |
989 | identical in size. */ | |
990 | ||
991 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ | |
992 | (TARGET_ARCH64 \ | |
993 | && (FROM) == SImode \ | |
994 | && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
995 | ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) | |
996 | ||
3aabf9a5 EC |
997 | /* This is the order in which to allocate registers normally. |
998 | ||
af54350e | 999 | We put %f0-%f7 last among the float registers, so as to make it more |
6a4bb1fa | 1000 | likely that a pseudo-register which dies in the float return register |
af54350e DM |
1001 | area will get allocated to the float return register, thus saving a move |
1002 | instruction at the end of the function. | |
1003 | ||
1004 | Similarly for integer return value registers. | |
1005 | ||
1006 | We know in this case that we will not end up with a leaf function. | |
1007 | ||
fae778eb | 1008 | The register allocator is given the global and out registers first |
af54350e DM |
1009 | because these registers are call clobbered and thus less useful to |
1010 | global register allocation. | |
1011 | ||
1012 | Next we list the local and in registers. They are not call clobbered | |
1013 | and thus very useful for global register allocation. We list the input | |
1014 | registers before the locals so that it is more likely the incoming | |
1015 | arguments received in those registers can just stay there and not be | |
1016 | reloaded. */ | |
6afca97d | 1017 | |
7a6cf439 | 1018 | #define REG_ALLOC_ORDER \ |
af54350e DM |
1019 | { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ |
1020 | 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
1021 | 15, /* %o7 */ \ | |
1022 | 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
1023 | 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ | |
7a6cf439 | 1024 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ |
7a6cf439 DE |
1025 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ |
1026 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1027 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1028 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
4fb4e4b8 DE |
1029 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ |
1030 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
af54350e DM |
1031 | 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ |
1032 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
10b859c0 | 1033 | 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ |
1bb87f28 JW |
1034 | |
1035 | /* This is the order in which to allocate registers for | |
af54350e DM |
1036 | leaf functions. If all registers can fit in the global and |
1037 | output registers, then we have the possibility of having a leaf | |
1038 | function. | |
1039 | ||
1040 | The macro actually mentioned the input registers first, | |
1041 | because they get renumbered into the output registers once | |
1042 | we know really do have a leaf function. | |
1043 | ||
1044 | To be more precise, this register allocation order is used | |
1045 | when %o7 is found to not be clobbered right before register | |
1046 | allocation. Normally, the reason %o7 would be clobbered is | |
1047 | due to a call which could not be transformed into a sibling | |
1048 | call. | |
1049 | ||
1050 | As a consequence, it is possible to use the leaf register | |
1051 | allocation order and not end up with a leaf function. We will | |
1052 | not get suboptimal register allocation in that case because by | |
1053 | definition of being potentially leaf, there were no function | |
1054 | calls. Therefore, allocation order within the local register | |
1055 | window is not critical like it is when we do have function calls. */ | |
6afca97d | 1056 | |
7a6cf439 | 1057 | #define REG_LEAF_ALLOC_ORDER \ |
af54350e DM |
1058 | { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ |
1059 | 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ | |
1060 | 15, /* %o7 */ \ | |
1061 | 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
1062 | 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
1063 | 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
1064 | 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
1065 | 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
1066 | 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
1067 | 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
1068 | 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
1069 | 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
1070 | 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
1071 | 96, 97, 98, 99, /* %fcc0-3 */ \ | |
10b859c0 | 1072 | 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ |
3aabf9a5 | 1073 | |
5a733826 | 1074 | #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () |
1bb87f28 | 1075 | |
7d167afd JJ |
1076 | extern char sparc_leaf_regs[]; |
1077 | #define LEAF_REGISTERS sparc_leaf_regs | |
1bb87f28 | 1078 | |
d70e94ec | 1079 | extern char leaf_reg_remap[]; |
1bb87f28 | 1080 | #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) |
1bb87f28 | 1081 | |
1bb87f28 JW |
1082 | /* The class value for index registers, and the one for base regs. */ |
1083 | #define INDEX_REG_CLASS GENERAL_REGS | |
1084 | #define BASE_REG_CLASS GENERAL_REGS | |
1085 | ||
24b63396 | 1086 | /* Local macro to handle the two v9 classes of FP regs. */ |
24b63396 | 1087 | #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) |
24b63396 | 1088 | |
0e5d569c | 1089 | /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */ |
1ccfa253 DE |
1090 | #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) |
1091 | #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) | |
1092 | #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) | |
0e5d569c EB |
1093 | |
1094 | /* 10- and 11-bit immediates are only used for a few specific insns. | |
18c5947f DE |
1095 | SMALL_INT is used throughout the port so we continue to use it. */ |
1096 | #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) | |
0e5d569c EB |
1097 | |
1098 | /* Predicate for constants that can be loaded with a sethi instruction. | |
1099 | This is the general, 64-bit aware, bitwise version that ensures that | |
1100 | only constants whose representation fits in the mask | |
1101 | ||
1102 | 0x00000000fffffc00 | |
1103 | ||
1104 | are accepted. It will reject, for example, negative SImode constants | |
1105 | on 64-bit hosts, so correct handling is to mask the value beforehand | |
1106 | according to the mode of the instruction. */ | |
1ccfa253 | 1107 | #define SPARC_SETHI_P(X) \ |
7d6040e8 AO |
1108 | (((unsigned HOST_WIDE_INT) (X) \ |
1109 | & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) | |
0e5d569c EB |
1110 | |
1111 | /* Version of the above predicate for SImode constants and below. */ | |
7d6040e8 AO |
1112 | #define SPARC_SETHI32_P(X) \ |
1113 | (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) | |
1bb87f28 | 1114 | |
1bb87f28 JW |
1115 | /* Return the register class of a scratch register needed to load IN into |
1116 | a register of class CLASS in MODE. | |
1117 | ||
e0d80184 | 1118 | We need a temporary when loading/storing a HImode/QImode value |
ae51bd97 | 1119 | between memory and the FPU registers. This can happen when combine puts |
26aeede4 JJ |
1120 | a paradoxical subreg in a float/fix conversion insn. |
1121 | ||
1122 | We need a temporary when loading/storing a DFmode value between | |
1123 | unaligned memory and the upper FPU registers. */ | |
ae51bd97 JW |
1124 | |
1125 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
e0d80184 DM |
1126 | ((FP_REG_CLASS_P (CLASS) \ |
1127 | && ((MODE) == HImode || (MODE) == QImode) \ | |
24b63396 | 1128 | && (GET_CODE (IN) == MEM \ |
e0d80184 DM |
1129 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ |
1130 | && true_regnum (IN) == -1))) \ | |
1131 | ? GENERAL_REGS \ | |
26aeede4 JJ |
1132 | : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ |
1133 | && GET_CODE (IN) == MEM && TARGET_ARCH32 \ | |
1134 | && ! mem_min_alignment ((IN), 8)) \ | |
1135 | ? FP_REGS \ | |
1136 | : (((TARGET_CM_MEDANY \ | |
1137 | && symbolic_operand ((IN), (MODE))) \ | |
1138 | || (TARGET_CM_EMBMEDANY \ | |
1139 | && text_segment_operand ((IN), (MODE)))) \ | |
1140 | && !flag_pic) \ | |
1141 | ? GENERAL_REGS \ | |
1142 | : NO_REGS) | |
ae51bd97 JW |
1143 | |
1144 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
26aeede4 | 1145 | ((FP_REG_CLASS_P (CLASS) \ |
e0d80184 DM |
1146 | && ((MODE) == HImode || (MODE) == QImode) \ |
1147 | && (GET_CODE (IN) == MEM \ | |
1148 | || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \ | |
1149 | && true_regnum (IN) == -1))) \ | |
26aeede4 JJ |
1150 | ? GENERAL_REGS \ |
1151 | : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \ | |
1152 | && GET_CODE (IN) == MEM && TARGET_ARCH32 \ | |
1153 | && ! mem_min_alignment ((IN), 8)) \ | |
1154 | ? FP_REGS \ | |
1155 | : (((TARGET_CM_MEDANY \ | |
1156 | && symbolic_operand ((IN), (MODE))) \ | |
1157 | || (TARGET_CM_EMBMEDANY \ | |
1158 | && text_segment_operand ((IN), (MODE)))) \ | |
1159 | && !flag_pic) \ | |
1160 | ? GENERAL_REGS \ | |
1161 | : NO_REGS) | |
1bb87f28 | 1162 | |
3aabf9a5 | 1163 | /* On SPARC it is not possible to directly move data between |
b924cef0 | 1164 | GENERAL_REGS and FP_REGS. */ |
24b63396 JW |
1165 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
1166 | (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) | |
b924cef0 | 1167 | |
9ec36da5 | 1168 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9 |
7a6cf439 DE |
1169 | because the movsi and movsf patterns don't handle r/f moves. |
1170 | For v8 we copy the default definition. */ | |
1171 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
6f64bf5f | 1172 | (TARGET_ARCH64 \ |
fb3eb6f6 JW |
1173 | ? (GET_MODE_BITSIZE (MODE) < 32 \ |
1174 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 | 1175 | : MODE) \ |
fb3eb6f6 JW |
1176 | : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \ |
1177 | ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \ | |
7a6cf439 DE |
1178 | : MODE)) |
1179 | ||
1bb87f28 JW |
1180 | /* Return the maximum number of consecutive registers |
1181 | needed to represent mode MODE in a register of class CLASS. */ | |
1182 | /* On SPARC, this is the size of MODE in words. */ | |
1183 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
24b63396 | 1184 | (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ |
7a6cf439 | 1185 | : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) |
1bb87f28 JW |
1186 | \f |
1187 | /* Stack layout; function entry, exit and calling. */ | |
1188 | ||
1bb87f28 JW |
1189 | /* Define this if pushing a word on the stack |
1190 | makes the stack pointer a smaller address. */ | |
1191 | #define STACK_GROWS_DOWNWARD | |
1192 | ||
a4d05547 | 1193 | /* Define this to nonzero if the nominal address of the stack frame |
1bb87f28 JW |
1194 | is at the high-address end of the local variables; |
1195 | that is, each additional local variable allocated | |
1196 | goes at a more negative offset in the frame. */ | |
f62c8a5c | 1197 | #define FRAME_GROWS_DOWNWARD 1 |
1bb87f28 JW |
1198 | |
1199 | /* Offset within stack frame to start allocating local variables at. | |
1200 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1201 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
1202 | of the first local allocated. */ | |
3106d8e5 | 1203 | #define STARTING_FRAME_OFFSET 0 |
1bb87f28 | 1204 | |
1bb87f28 | 1205 | /* Offset of first parameter from the argument pointer register value. |
7a6cf439 DE |
1206 | !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg |
1207 | even if this function isn't going to use it. | |
4fb4e4b8 | 1208 | v9: This is 128 for the ins and locals. */ |
7a6cf439 | 1209 | #define FIRST_PARM_OFFSET(FNDECL) \ |
563c12b0 | 1210 | (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) |
1bb87f28 | 1211 | |
2c849145 JM |
1212 | /* Offset from the argument pointer register value to the CFA. |
1213 | This is different from FIRST_PARM_OFFSET because the register window | |
1214 | comes between the CFA and the arguments. */ | |
c2c9f6c9 | 1215 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 |
71038426 | 1216 | |
1bb87f28 | 1217 | /* When a parameter is passed in a register, stack space is still |
82d6b402 RH |
1218 | allocated for it. |
1219 | !v9: All 6 possible integer registers have backing store allocated. | |
80ffc95e | 1220 | v9: Only space for the arguments passed is allocated. */ |
82d6b402 RH |
1221 | /* ??? Ideally, we'd use zero here (as the minimum), but zero has special |
1222 | meaning to the backend. Further, we need to be able to detect if a | |
1223 | varargs/unprototyped function is called, as they may want to spill more | |
1224 | registers than we've provided space. Ugly, ugly. So for now we retain | |
1225 | all 6 slots even for v9. */ | |
4fb4e4b8 | 1226 | #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) |
1bb87f28 | 1227 | |
563c12b0 | 1228 | /* Definitions for register elimination. */ |
3aabf9a5 | 1229 | |
563c12b0 | 1230 | #define ELIMINABLE_REGS \ |
e387e99b JJ |
1231 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
1232 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } | |
563c12b0 | 1233 | |
9ac617d4 EB |
1234 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1235 | do { \ | |
9ac617d4 | 1236 | if ((TO) == STACK_POINTER_REGNUM) \ |
b11b0904 EB |
1237 | (OFFSET) = sparc_compute_frame_size (get_frame_size (), \ |
1238 | current_function_is_leaf); \ | |
5be9b7a1 EB |
1239 | else \ |
1240 | (OFFSET) = 0; \ | |
9ac617d4 | 1241 | (OFFSET) += SPARC_STACK_BIAS; \ |
e387e99b | 1242 | } while (0) |
563c12b0 | 1243 | |
1bb87f28 | 1244 | /* Keep the stack pointer constant throughout the function. |
b4ac57ab | 1245 | This is both an optimization and a necessity: longjmp |
1bb87f28 JW |
1246 | doesn't behave itself when the stack pointer moves within |
1247 | the function! */ | |
f73ad30e | 1248 | #define ACCUMULATE_OUTGOING_ARGS 1 |
1bb87f28 | 1249 | |
92ea370b TW |
1250 | /* Define this macro if the target machine has "register windows". This |
1251 | C expression returns the register number as seen by the called function | |
1252 | corresponding to register number OUT as seen by the calling function. | |
1253 | Return OUT if register number OUT is not an outbound register. */ | |
1254 | ||
1255 | #define INCOMING_REGNO(OUT) \ | |
b11b0904 | 1256 | ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) |
92ea370b TW |
1257 | |
1258 | /* Define this macro if the target machine has "register windows". This | |
1259 | C expression returns the register number as seen by the calling function | |
1260 | corresponding to register number IN as seen by the called function. | |
1261 | Return IN if register number IN is not an inbound register. */ | |
1262 | ||
1263 | #define OUTGOING_REGNO(IN) \ | |
b11b0904 | 1264 | ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) |
92ea370b | 1265 | |
2a3e384f RH |
1266 | /* Define this macro if the target machine has register windows. This |
1267 | C expression returns true if the register is call-saved but is in the | |
1268 | register window. */ | |
1269 | ||
1270 | #define LOCAL_REGNO(REGNO) \ | |
b11b0904 | 1271 | (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) |
2a3e384f | 1272 | |
34aaacec JW |
1273 | /* Define the size of space to allocate for the return value of an |
1274 | untyped_call. */ | |
1275 | ||
d24088cc | 1276 | #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) |
34aaacec | 1277 | |
1bb87f28 | 1278 | /* 1 if N is a possible register number for function argument passing. |
4fb4e4b8 | 1279 | On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ |
1bb87f28 | 1280 | |
7a6cf439 | 1281 | #define FUNCTION_ARG_REGNO_P(N) \ |
4fb4e4b8 DE |
1282 | (TARGET_ARCH64 \ |
1283 | ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \ | |
1284 | : ((N) >= 8 && (N) <= 13)) | |
1bb87f28 JW |
1285 | \f |
1286 | /* Define a data type for recording info about an argument list | |
1287 | during the scan of that argument list. This data type should | |
1288 | hold all necessary information about the function itself | |
1289 | and about the args processed so far, enough to enable macros | |
1290 | such as FUNCTION_ARG to determine where the next arg should go. | |
1291 | ||
7a6cf439 | 1292 | On SPARC (!v9), this is a single integer, which is a number of words |
1bb87f28 JW |
1293 | of arguments scanned so far (including the invisible argument, |
1294 | if any, which holds the structure-value-address). | |
7a6cf439 DE |
1295 | Thus 7 or more means all following args should go on the stack. |
1296 | ||
4fb4e4b8 | 1297 | For v9, we also need to know whether a prototype is present. */ |
7a6cf439 | 1298 | |
7a6cf439 | 1299 | struct sparc_args { |
4fb4e4b8 | 1300 | int words; /* number of words passed so far */ |
5e7a8ee0 KH |
1301 | int prototype_p; /* nonzero if a prototype is present */ |
1302 | int libcall_p; /* nonzero if a library call */ | |
7a6cf439 DE |
1303 | }; |
1304 | #define CUMULATIVE_ARGS struct sparc_args | |
1305 | ||
1bb87f28 JW |
1306 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1307 | for a call to a function whose data type is FNTYPE. | |
4fb4e4b8 | 1308 | For a library call, FNTYPE is 0. */ |
1bb87f28 | 1309 | |
0f6937fe | 1310 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
563a317a | 1311 | init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); |
1bb87f28 | 1312 | |
4fb4e4b8 DE |
1313 | /* If defined, a C expression which determines whether, and in which direction, |
1314 | to pad out an argument with extra space. The value should be of type | |
1315 | `enum direction': either `upward' to pad above the argument, | |
1316 | `downward' to pad below, or `none' to inhibit padding. */ | |
284d86e9 | 1317 | |
4fb4e4b8 DE |
1318 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ |
1319 | function_arg_padding ((MODE), (TYPE)) | |
1320 | ||
1bb87f28 | 1321 | \f |
4b69d2a3 RS |
1322 | /* Generate the special assembly code needed to tell the assembler whatever |
1323 | it might need to know about the return value of a function. | |
1324 | ||
56149abc | 1325 | For SPARC assemblers, we need to output a .proc pseudo-op which conveys |
4b69d2a3 RS |
1326 | information to the assembler relating to peephole optimization (done in |
1327 | the assembler). */ | |
1328 | ||
1329 | #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
4f70758f | 1330 | fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) |
4b69d2a3 | 1331 | |
1cb36a98 | 1332 | /* Output the special assembly code needed to tell the assembler some |
3aabf9a5 | 1333 | register is used as global register variable. |
730f0207 JJ |
1334 | |
1335 | SPARC 64bit psABI declares registers %g2 and %g3 as application | |
1336 | registers and %g6 and %g7 as OS registers. Any object using them | |
1337 | should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them | |
1338 | and how they are used (scratch or some global variable). | |
1339 | Linker will then refuse to link together objects which use those | |
1340 | registers incompatibly. | |
1341 | ||
1342 | Unless the registers are used for scratch, two different global | |
1343 | registers cannot be declared to the same name, so in the unlikely | |
1344 | case of a global register variable occupying more than one register | |
1345 | we prefix the second and following registers with .gnu.part1. etc. */ | |
1346 | ||
94fcbf65 | 1347 | extern GTY(()) char sparc_hard_reg_printed[8]; |
1cb36a98 RH |
1348 | |
1349 | #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
1350 | #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ | |
1351 | do { \ | |
1352 | if (TARGET_ARCH64) \ | |
1353 | { \ | |
730f0207 JJ |
1354 | int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ |
1355 | int reg; \ | |
1356 | for (reg = (REGNO); reg < 8 && reg < end; reg++) \ | |
1357 | if ((reg & ~1) == 2 || (reg & ~1) == 6) \ | |
1cb36a98 | 1358 | { \ |
730f0207 JJ |
1359 | if (reg == (REGNO)) \ |
1360 | fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ | |
1cb36a98 RH |
1361 | else \ |
1362 | fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ | |
730f0207 JJ |
1363 | reg, reg - (REGNO), (NAME)); \ |
1364 | sparc_hard_reg_printed[reg] = 1; \ | |
1cb36a98 RH |
1365 | } \ |
1366 | } \ | |
1367 | } while (0) | |
1368 | #endif | |
1369 | ||
c4ce6853 | 1370 | \f |
89a8b315 RH |
1371 | /* Emit rtl for profiling. */ |
1372 | #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) | |
6f334f44 | 1373 | |
89a8b315 RH |
1374 | /* All the work done in PROFILE_HOOK, but still required. */ |
1375 | #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) | |
1bb87f28 | 1376 | |
2be15d0f | 1377 | /* Set the name of the mcount function for the system. */ |
2be15d0f | 1378 | #define MCOUNT_FUNCTION "*mcount" |
c4ce6853 | 1379 | \f |
1bb87f28 JW |
1380 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
1381 | the stack pointer does not matter. The value is tested only in | |
b11b0904 EB |
1382 | functions that have frame pointers. */ |
1383 | #define EXIT_IGNORE_STACK 1 | |
1bb87f28 | 1384 | |
1bb87f28 | 1385 | /* Length in units of the trampoline for entering a nested function. */ |
c6b0465b JC |
1386 | #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) |
1387 | ||
bc6d3f91 | 1388 | /* Alignment required for trampolines, in bits. */ |
bc6d3f91 | 1389 | #define TRAMPOLINE_ALIGNMENT 128 |
6a4bb1fa | 1390 | \f |
953fe179 JW |
1391 | /* Generate RTL to flush the register windows so as to make arbitrary frames |
1392 | available. */ | |
b11b0904 EB |
1393 | #define SETUP_FRAME_ADDRESSES() \ |
1394 | do { \ | |
1395 | if (!TARGET_FLAT) \ | |
1396 | emit_insn (gen_flush_register_windows ());\ | |
1397 | } while (0) | |
953fe179 JW |
1398 | |
1399 | /* Given an rtx for the address of a frame, | |
1400 | return an rtx for the address of the word in the frame | |
60b85c4c | 1401 | that holds the dynamic chain--the previous frame's address. */ |
8773135d JS |
1402 | #define DYNAMIC_CHAIN_ADDRESS(frame) \ |
1403 | plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) | |
953fe179 | 1404 | |
224869d9 EB |
1405 | /* Given an rtx for the frame pointer, |
1406 | return an rtx for the address of the frame. */ | |
1407 | #define FRAME_ADDR_RTX(frame) plus_constant (frame, SPARC_STACK_BIAS) | |
1408 | ||
953fe179 JW |
1409 | /* The return address isn't on the stack, it is in a register, so we can't |
1410 | access it from the current frame pointer. We can access it from the | |
1411 | previous frame pointer though by reading a value from the register window | |
1412 | save area. */ | |
1413 | #define RETURN_ADDR_IN_PREVIOUS_FRAME | |
1414 | ||
5b6faa70 | 1415 | /* This is the offset of the return address to the true next instruction to be |
80ffc95e | 1416 | executed for the current function. */ |
6f64bf5f | 1417 | #define RETURN_ADDR_OFFSET \ |
e3b5732b | 1418 | (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) |
5b6faa70 | 1419 | |
953fe179 JW |
1420 | /* The current return address is in %i7. The return address of anything |
1421 | farther back is in the register window save area at [%fp+60]. */ | |
1422 | /* ??? This ignores the fact that the actual return address is +8 for normal | |
1423 | returns, and +12 for structure returns. */ | |
b11b0904 | 1424 | #define RETURN_ADDR_REGNUM 31 |
953fe179 JW |
1425 | #define RETURN_ADDR_RTX(count, frame) \ |
1426 | ((count == -1) \ | |
b11b0904 | 1427 | ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ |
284d86e9 | 1428 | : gen_rtx_MEM (Pmode, \ |
c5c76735 | 1429 | memory_address (Pmode, plus_constant (frame, \ |
cd49f073 AM |
1430 | 15 * UNITS_PER_WORD \ |
1431 | + SPARC_STACK_BIAS)))) | |
9704efe6 | 1432 | |
d60bee3a DE |
1433 | /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's |
1434 | +12, but always using +8 is close enough for frame unwind purposes. | |
1435 | Actually, just using %o7 is close enough for unwinding, but %o7+8 | |
1436 | is something you can return to. */ | |
b11b0904 | 1437 | #define INCOMING_RETURN_ADDR_REGNUM 15 |
d60bee3a | 1438 | #define INCOMING_RETURN_ADDR_RTX \ |
b11b0904 EB |
1439 | plus_constant (gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) |
1440 | #define DWARF_FRAME_RETURN_COLUMN \ | |
1441 | DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) | |
d60bee3a DE |
1442 | |
1443 | /* The offset from the incoming value of %sp to the top of the stack frame | |
1444 | for the current function. On sparc64, we have to account for the stack | |
1445 | bias if present. */ | |
1446 | #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS | |
1447 | ||
1150a841 | 1448 | /* Describe how we implement __builtin_eh_return. */ |
b11b0904 | 1449 | #define EH_RETURN_REGNUM 1 |
1150a841 | 1450 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) |
b11b0904 EB |
1451 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) |
1452 | ||
1453 | /* Define registers used by the epilogue and return instruction. */ | |
1454 | #define EPILOGUE_USES(REGNO) \ | |
1455 | ((REGNO) == RETURN_ADDR_REGNUM \ | |
1456 | || (TARGET_FLAT \ | |
1457 | && epilogue_completed \ | |
1458 | && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ | |
1459 | || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) | |
17e9e88c JJ |
1460 | |
1461 | /* Select a format to encode pointers in exception handling data. CODE | |
1462 | is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
1463 | true if the symbol may be affected by dynamic relocations. | |
1464 | ||
1465 | If assembler and linker properly support .uaword %r_disp32(foo), | |
1466 | then use PC relative 32-bit relocations instead of absolute relocs | |
1467 | for shared libraries. On sparc64, use pc relative 32-bit relocs even | |
cf7b8b0d JJ |
1468 | for binaries, to save memory. |
1469 | ||
1470 | binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the | |
1471 | symbol %r_disp32() is against was not local, but .hidden. In that | |
1472 | case, we have to use DW_EH_PE_absptr for pic personality. */ | |
17e9e88c | 1473 | #ifdef HAVE_AS_SPARC_UA_PCREL |
cf7b8b0d | 1474 | #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN |
17e9e88c JJ |
1475 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ |
1476 | (flag_pic \ | |
1477 | ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ | |
1478 | : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1479 | ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1480 | : DW_EH_PE_absptr)) | |
cf7b8b0d JJ |
1481 | #else |
1482 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1483 | (flag_pic \ | |
1484 | ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ | |
1485 | : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1486 | ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1487 | : DW_EH_PE_absptr)) | |
1488 | #endif | |
17e9e88c JJ |
1489 | |
1490 | /* Emit a PC-relative relocation. */ | |
1491 | #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
1492 | do { \ | |
1493 | fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
1494 | fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ | |
1495 | assemble_name (FILE, LABEL); \ | |
1496 | fputc (')', FILE); \ | |
1497 | } while (0) | |
1498 | #endif | |
1bb87f28 JW |
1499 | \f |
1500 | /* Addressing modes, and classification of registers for them. */ | |
1501 | ||
1bb87f28 JW |
1502 | /* Macros to check register numbers against specific register classes. */ |
1503 | ||
1504 | /* These assume that REGNO is a hard or pseudo reg number. | |
1505 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1506 | or a pseudo reg currently allocated to a suitable hard reg. | |
1507 | Since they use reg_renumber, they are safe only once reg_renumber | |
1508 | has been allocated, which happens in local-alloc.c. */ | |
1509 | ||
1510 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
563c12b0 RH |
1511 | ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \ |
1512 | || (REGNO) == FRAME_POINTER_REGNUM \ | |
1513 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) | |
1514 | ||
1515 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
1516 | ||
1bb87f28 | 1517 | #define REGNO_OK_FOR_FP_P(REGNO) \ |
4f70758f KG |
1518 | (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ |
1519 | || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) | |
0a222ba7 | 1520 | |
7a6cf439 DE |
1521 | #define REGNO_OK_FOR_CCFP_P(REGNO) \ |
1522 | (TARGET_V9 \ | |
4f70758f KG |
1523 | && (((unsigned) (REGNO) - 96 < (unsigned)4) \ |
1524 | || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) | |
1bb87f28 JW |
1525 | \f |
1526 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1527 | ||
1528 | #define MAX_REGS_PER_ADDRESS 2 | |
1529 | ||
7aca9b9c JW |
1530 | /* Recognize any constant value that is a valid address. |
1531 | When PIC, we do not accept an address that would require a scratch reg | |
1532 | to load into a register. */ | |
1bb87f28 | 1533 | |
5751a10b | 1534 | #define CONSTANT_ADDRESS_P(X) constant_address_p (X) |
7aca9b9c JW |
1535 | |
1536 | /* Define this, so that when PIC, reload won't try to reload invalid | |
1537 | addresses which require two reload registers. */ | |
1538 | ||
5751a10b | 1539 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) |
1bb87f28 | 1540 | \f |
1cb36a98 RH |
1541 | /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ |
1542 | ||
1543 | #ifdef HAVE_AS_OFFSETABLE_LO10 | |
1544 | #define USE_AS_OFFSETABLE_LO10 1 | |
1545 | #else | |
1546 | #define USE_AS_OFFSETABLE_LO10 0 | |
1547 | #endif | |
1bb87f28 | 1548 | \f |
8947065c RH |
1549 | /* Try a machine-dependent way of reloading an illegitimate address |
1550 | operand. If we find one, push the reload and jump to WIN. This | |
58e6223e EB |
1551 | macro is used in only one place: `find_reloads_address' in reload.c. */ |
1552 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
1553 | do { \ | |
1554 | int win; \ | |
1555 | (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ | |
1556 | (int)(TYPE), (IND_LEVELS), &win); \ | |
1557 | if (win) \ | |
1558 | goto WIN; \ | |
8947065c | 1559 | } while (0) |
1bb87f28 JW |
1560 | \f |
1561 | /* Specify the machine mode that this machine uses | |
1562 | for the index in the tablejump instruction. */ | |
67cb8900 JJ |
1563 | /* If we ever implement any of the full models (such as CM_FULLANY), |
1564 | this has to be DImode in that case */ | |
d1accaa3 | 1565 | #ifdef HAVE_GAS_SUBSECTION_ORDERING |
67cb8900 JJ |
1566 | #define CASE_VECTOR_MODE \ |
1567 | (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
d1accaa3 JJ |
1568 | #else |
1569 | /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise | |
80ffc95e | 1570 | we have to sign extend which slows things down. */ |
d1accaa3 JJ |
1571 | #define CASE_VECTOR_MODE \ |
1572 | (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
1573 | #endif | |
1bb87f28 | 1574 | |
1bb87f28 JW |
1575 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1576 | #define DEFAULT_SIGNED_CHAR 1 | |
1577 | ||
1578 | /* Max number of bytes we can move from memory to memory | |
1579 | in one reasonably fast instruction. */ | |
2eef2ef1 | 1580 | #define MOVE_MAX 8 |
1bb87f28 | 1581 | |
5162e02a | 1582 | /* If a memory-to-memory move would take MOVE_RATIO or more simple |
70128ad9 | 1583 | move-instruction pairs, we will do a movmem or libcall instead. */ |
5162e02a | 1584 | |
e04ad03d | 1585 | #define MOVE_RATIO(speed) ((speed) ? 8 : 3) |
5162e02a | 1586 | |
9a63901f RK |
1587 | /* Define if operations between registers always perform the operation |
1588 | on the full register even if a narrower mode is specified. */ | |
1589 | #define WORD_REGISTER_OPERATIONS | |
1590 | ||
1591 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1592 | will either zero-extend or sign-extend. The value of this macro should | |
1593 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1594 | done, UNKNOWN if none. */ |
9a63901f | 1595 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
1bb87f28 JW |
1596 | |
1597 | /* Nonzero if access to memory by bytes is slow and undesirable. | |
1598 | For RISC chips, it means that access to memory by bytes is no | |
1599 | better than access by words when possible, so grab a whole word | |
1600 | and maybe make use of that. */ | |
1601 | #define SLOW_BYTE_ACCESS 1 | |
1602 | ||
d969caf8 | 1603 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
80ffc95e | 1604 | few bits. */ |
d969caf8 | 1605 | #define SHIFT_COUNT_TRUNCATED 1 |
1bb87f28 JW |
1606 | |
1607 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1608 | is done just by pretending it is already truncated. */ | |
1609 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1610 | ||
dc78280f DM |
1611 | /* For SImode, we make sure the top 32-bits of the register are clear and |
1612 | then we subtract 32 from the lzd instruction result. */ | |
1613 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1614 | ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) | |
1615 | ||
1bb87f28 | 1616 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
4d449554 | 1617 | return the mode to be used for the comparison. For floating-point, |
7913f3d0 RH |
1618 | CCFP[E]mode is used. CC_NOOVmode should be used when the first operand |
1619 | is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special | |
922bd191 | 1620 | processing is needed. */ |
e267e177 | 1621 | #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) |
1bb87f28 | 1622 | |
5e7a8ee0 | 1623 | /* Return nonzero if MODE implies a floating point inequality can be |
56149abc | 1624 | reversed. For SPARC this is always true because we have a full |
46238b7d JJ |
1625 | compliment of ordered and unordered comparisons, but until generic |
1626 | code knows how to reverse it correctly we keep the old definition. */ | |
1627 | #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) | |
b331b745 | 1628 | |
3276910d RK |
1629 | /* A function address in a call instruction for indexing purposes. */ |
1630 | #define FUNCTION_MODE Pmode | |
1bb87f28 JW |
1631 | |
1632 | /* Define this if addresses of constant functions | |
1633 | shouldn't be put through pseudo regs where they can be cse'd. | |
1634 | Desirable on machines where ordinary constants are expensive | |
1635 | but a CALL with constant address is cheap. */ | |
1636 | #define NO_FUNCTION_CSE | |
1637 | ||
c15c90bb ZW |
1638 | /* The _Q_* comparison libcalls return booleans. */ |
1639 | #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) | |
8248e2bc | 1640 | |
4e7d5d27 DM |
1641 | /* Assume by default that the _Qp_* 64-bit libcalls are implemented such |
1642 | that the inputs are fully consumed before the output memory is clobbered. */ | |
1643 | ||
1644 | #define TARGET_BUGGY_QP_LIB 0 | |
1645 | ||
c15c90bb ZW |
1646 | /* Assume by default that we do not have the Solaris-specific conversion |
1647 | routines nor 64-bit integer multiply and divide routines. */ | |
78e9b5df | 1648 | |
45dcc026 JJ |
1649 | #define SUN_CONVERSION_LIBFUNCS 0 |
1650 | #define DITF_CONVERSION_LIBFUNCS 0 | |
1651 | #define SUN_INTEGER_MULTIPLY_64 0 | |
c5c60e15 | 1652 | |
2f82dbf8 DM |
1653 | /* Provide the cost of a branch. For pre-v9 processors we use |
1654 | a value of 3 to take into account the potential annulling of | |
1655 | the delay slot (which ends up being a bubble in the pipeline slot) | |
1656 | plus a cycle to take into consideration the instruction cache | |
1657 | effects. | |
1658 | ||
1659 | On v9 and later, which have branch prediction facilities, we set | |
1660 | it to the depth of the pipeline as that is the cost of a | |
4c837a1e DM |
1661 | mispredicted branch. |
1662 | ||
1663 | On Niagara, normal branches insert 3 bubbles into the pipe | |
9eeaed6e DM |
1664 | and annulled branches insert 4 bubbles. |
1665 | ||
3e64c239 DM |
1666 | On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas |
1667 | a taken branch costs 6 cycles. */ | |
2f82dbf8 | 1668 | |
1f494b6d | 1669 | #define BRANCH_COST(speed_p, predictable_p) \ |
2f82dbf8 DM |
1670 | ((sparc_cpu == PROCESSOR_V9 \ |
1671 | || sparc_cpu == PROCESSOR_ULTRASPARC) \ | |
84643cbf DM |
1672 | ? 7 \ |
1673 | : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ | |
4c837a1e DM |
1674 | ? 9 \ |
1675 | : (sparc_cpu == PROCESSOR_NIAGARA \ | |
1676 | ? 4 \ | |
3e64c239 DM |
1677 | : ((sparc_cpu == PROCESSOR_NIAGARA2 \ |
1678 | || sparc_cpu == PROCESSOR_NIAGARA3) \ | |
9eeaed6e DM |
1679 | ? 5 \ |
1680 | : 3)))) | |
1bb87f28 JW |
1681 | \f |
1682 | /* Control the assembler format that we output. */ | |
1683 | ||
1ccfa253 DE |
1684 | /* A C string constant describing how to begin a comment in the target |
1685 | assembler language. The compiler assumes that the comment will end at | |
1686 | the end of the line. */ | |
1687 | ||
1688 | #define ASM_COMMENT_START "!" | |
1689 | ||
1bb87f28 JW |
1690 | /* Output to assembler file text saying following lines |
1691 | may contain character constants, extra white space, comments, etc. */ | |
1692 | ||
1693 | #define ASM_APP_ON "" | |
1694 | ||
1695 | /* Output to assembler file text saying following lines | |
1696 | no longer contain unusual constructs. */ | |
1697 | ||
1698 | #define ASM_APP_OFF "" | |
1699 | ||
1bb87f28 JW |
1700 | /* How to refer to registers in assembler output. |
1701 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
1702 | ||
7a6cf439 DE |
1703 | #define REGISTER_NAMES \ |
1704 | {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
1705 | "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
1706 | "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
1707 | "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
1708 | "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
1709 | "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
1710 | "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
1711 | "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
1712 | "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
1713 | "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
1714 | "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
1715 | "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
10b859c0 | 1716 | "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } |
ea3fa5f7 | 1717 | |
c4ce6853 | 1718 | /* Define additional names for use in asm clobbers and asm declarations. */ |
ea3fa5f7 | 1719 | |
c4ce6853 DE |
1720 | #define ADDITIONAL_REGISTER_NAMES \ |
1721 | {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} | |
ea3fa5f7 | 1722 | |
5bcb3f13 JM |
1723 | /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length |
1724 | can run past this up to a continuation point. Once we used 1500, but | |
1725 | a single entry in C++ can run more than 500 bytes, due to the length of | |
1726 | mangled symbol names. dbxout.c should really be fixed to do | |
1727 | continuations when they are actually needed instead of trying to | |
1728 | guess... */ | |
1729 | #define DBX_CONTIN_LENGTH 1000 | |
1bb87f28 | 1730 | |
1bb87f28 JW |
1731 | /* This is how to output a command to make the user-level label named NAME |
1732 | defined for reference from other files. */ | |
1733 | ||
506a61b1 KG |
1734 | /* Globalizing directive for a label. */ |
1735 | #define GLOBAL_ASM_OP "\t.global " | |
1bb87f28 | 1736 | |
80ffc95e | 1737 | /* The prefix to add to user-visible assembler symbols. */ |
1bb87f28 | 1738 | |
4e0c8ad2 | 1739 | #define USER_LABEL_PREFIX "_" |
1bb87f28 | 1740 | |
1bb87f28 JW |
1741 | /* This is how to store into the string LABEL |
1742 | the symbol_ref name of an internal numbered label where | |
1743 | PREFIX is the class of label and NUM is the number within the class. | |
1744 | This is suitable for output with `assemble_name'. */ | |
1745 | ||
1746 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
4f70758f | 1747 | sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) |
1bb87f28 | 1748 | |
e0d80184 DM |
1749 | /* This is how we hook in and defer the case-vector until the end of |
1750 | the function. */ | |
e0d80184 DM |
1751 | #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ |
1752 | sparc_defer_case_vector ((LAB),(VEC), 0) | |
1753 | ||
1754 | #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ | |
1755 | sparc_defer_case_vector ((LAB),(VEC), 1) | |
1756 | ||
1bb87f28 JW |
1757 | /* This is how to output an element of a case-vector that is absolute. */ |
1758 | ||
1759 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
4b69d2a3 RS |
1760 | do { \ |
1761 | char label[30]; \ | |
1762 | ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
67cb8900 | 1763 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 1764 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
1765 | else \ |
1766 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 1767 | assemble_name (FILE, label); \ |
e0d80184 | 1768 | fputc ('\n', FILE); \ |
4b69d2a3 | 1769 | } while (0) |
1bb87f28 JW |
1770 | |
1771 | /* This is how to output an element of a case-vector that is relative. | |
1772 | (SPARC uses such vectors only when generating PIC.) */ | |
1773 | ||
33f7f353 | 1774 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
4b69d2a3 RS |
1775 | do { \ |
1776 | char label[30]; \ | |
e0d80184 | 1777 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ |
67cb8900 | 1778 | if (CASE_VECTOR_MODE == SImode) \ |
7a6cf439 | 1779 | fprintf (FILE, "\t.word\t"); \ |
7a6cf439 DE |
1780 | else \ |
1781 | fprintf (FILE, "\t.xword\t"); \ | |
4b69d2a3 | 1782 | assemble_name (FILE, label); \ |
e0d80184 DM |
1783 | ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ |
1784 | fputc ('-', FILE); \ | |
1785 | assemble_name (FILE, label); \ | |
1786 | fputc ('\n', FILE); \ | |
4b69d2a3 | 1787 | } while (0) |
1bb87f28 | 1788 | |
d1accaa3 JJ |
1789 | /* This is what to output before and after case-vector (both |
1790 | relative and absolute). If .subsection -1 works, we put case-vectors | |
1791 | at the beginning of the current section. */ | |
1792 | ||
1793 | #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
1794 | ||
1795 | #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ | |
1796 | fprintf(FILE, "\t.subsection\t-1\n") | |
1797 | ||
1798 | #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ | |
1799 | fprintf(FILE, "\t.previous\n") | |
1800 | ||
1801 | #endif | |
1802 | ||
1bb87f28 JW |
1803 | /* This is how to output an assembler line |
1804 | that says to advance the location counter | |
1805 | to a multiple of 2**LOG bytes. */ | |
1806 | ||
1807 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1808 | if ((LOG) != 0) \ | |
1809 | fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
1810 | ||
1811 | #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
58e15542 | 1812 | fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
1bb87f28 JW |
1813 | |
1814 | /* This says how to output an assembler line | |
1815 | to define a global common symbol. */ | |
1816 | ||
1817 | #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
b277ceaf | 1818 | ( fputs ("\t.common ", (FILE)), \ |
1bb87f28 | 1819 | assemble_name ((FILE), (NAME)), \ |
58e15542 | 1820 | fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) |
1bb87f28 | 1821 | |
b277ceaf JW |
1822 | /* This says how to output an assembler line to define a local common |
1823 | symbol. */ | |
1bb87f28 | 1824 | |
b277ceaf JW |
1825 | #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ |
1826 | ( fputs ("\t.reserve ", (FILE)), \ | |
1827 | assemble_name ((FILE), (NAME)), \ | |
58e15542 | 1828 | fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ |
b277ceaf | 1829 | (SIZE), ((ALIGNED) / BITS_PER_UNIT))) |
1bb87f28 | 1830 | |
101d9529 JM |
1831 | /* A C statement (sans semicolon) to output to the stdio stream |
1832 | FILE the assembler definition of uninitialized global DECL named | |
1833 | NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
1834 | Try to use asm_output_aligned_bss to implement this macro. */ | |
1835 | ||
1836 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1837 | do { \ | |
101d9529 JM |
1838 | ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ |
1839 | } while (0) | |
1840 | ||
471b6f1b | 1841 | #define IDENT_ASM_OP "\t.ident\t" |
c14f2655 RS |
1842 | |
1843 | /* Output #ident as a .ident. */ | |
1844 | ||
1845 | #define ASM_OUTPUT_IDENT(FILE, NAME) \ | |
b9f7d63e | 1846 | fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); |
c14f2655 | 1847 | |
4e5b002b EB |
1848 | /* Prettify the assembly. */ |
1849 | ||
1850 | extern int sparc_indent_opcode; | |
1851 | ||
1852 | #define ASM_OUTPUT_OPCODE(FILE, PTR) \ | |
1853 | do { \ | |
1854 | if (sparc_indent_opcode) \ | |
1855 | { \ | |
1856 | putc (' ', FILE); \ | |
1857 | sparc_indent_opcode = 0; \ | |
1858 | } \ | |
1859 | } while (0) | |
1860 | ||
fdbe66f2 EB |
1861 | /* TLS support defaulting to original Sun flavor. GNU extensions |
1862 | must be activated in separate configuration files. */ | |
5751a10b JJ |
1863 | #ifdef HAVE_AS_TLS |
1864 | #define TARGET_TLS 1 | |
1865 | #else | |
1866 | #define TARGET_TLS 0 | |
1867 | #endif | |
fdbe66f2 | 1868 | |
5751a10b JJ |
1869 | #define TARGET_SUN_TLS TARGET_TLS |
1870 | #define TARGET_GNU_TLS 0 | |
1871 | ||
e8b141b5 DM |
1872 | #ifndef HAVE_AS_FMAF_HPC_VIS3 |
1873 | #define AS_NIAGARA3_FLAG "b" | |
e8b141b5 DM |
1874 | #else |
1875 | #define AS_NIAGARA3_FLAG "d" | |
1876 | #endif | |
1877 | ||
27a36778 MS |
1878 | /* The number of Pmode words for the setjmp buffer. */ |
1879 | #define JMP_BUF_SIZE 12 | |
c5fcd670 AT |
1880 | |
1881 | /* We use gcc _mcount for profiling. */ | |
1882 | #define NO_PROFILE_COUNTERS 0 |