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dd552284 | 1 | ;; Scheduling description for Tilera TILE-Gx chip. |
7adcbafe | 2 | ;; Copyright (C) 2011-2022 Free Software Foundation, Inc. |
dd552284 WL |
3 | ;; Contributed by Walter Lee (walt@tilera.com) |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | (define_automaton "tile") | |
22 | ||
23 | ; Make the scheduling automaton an ndfa. | |
24 | (automata_option "ndfa") | |
25 | ||
26 | ; Name the three pipes. | |
27 | (define_cpu_unit "X0" "tile") | |
28 | (define_cpu_unit "X1" "tile") | |
29 | (define_cpu_unit "Y0" "tile") | |
30 | (define_cpu_unit "Y1" "tile") | |
31 | (define_cpu_unit "Y2" "tile") | |
32 | ||
33 | (define_insn_reservation "X0" 1 | |
34 | (eq_attr "type" "X0") | |
35 | "X0") | |
36 | ||
37 | (define_insn_reservation "X0_2cycle" 2 | |
38 | (eq_attr "type" "X0_2cycle") | |
39 | "X0,nothing") | |
40 | ||
41 | (define_insn_reservation "X1" 1 | |
42 | (eq_attr "type" "X1,X1_branch") | |
43 | "X1") | |
44 | ||
45 | (define_insn_reservation "X1_2cycle" 2 | |
46 | (eq_attr "type" "X1_2cycle") | |
47 | "X1,nothing") | |
48 | ||
49 | (define_insn_reservation "X1_L2" 11 | |
50 | (eq_attr "type" "X1_L2") | |
51 | "X1") | |
52 | ||
9b0370aa WL |
53 | (define_insn_reservation "X1_remote" 50 |
54 | (eq_attr "type" "X1_remote") | |
55 | "X1") | |
56 | ||
dd552284 WL |
57 | (define_insn_reservation "X1_miss" 80 |
58 | (eq_attr "type" "X1_miss") | |
59 | "X1") | |
60 | ||
61 | (define_insn_reservation "X01" 1 | |
62 | (eq_attr "type" "X01") | |
63 | "X0|X1") | |
64 | ||
65 | (define_insn_reservation "Y0" 1 | |
66 | (eq_attr "type" "Y0") | |
67 | "Y0|X0") | |
68 | ||
69 | (define_insn_reservation "Y0_2cycle" 2 | |
70 | (eq_attr "type" "Y0_2cycle") | |
71 | "Y0|X0,nothing") | |
72 | ||
73 | (define_insn_reservation "Y1" 1 | |
74 | (eq_attr "type" "Y1") | |
75 | "Y1|X1") | |
76 | ||
77 | (define_insn_reservation "Y2" 1 | |
78 | (eq_attr "type" "Y2") | |
79 | "Y2|X1") | |
80 | ||
81 | (define_insn_reservation "Y2_2cycle" 2 | |
82 | (eq_attr "type" "Y2_2cycle") | |
83 | "Y2|X1,nothing") | |
84 | ||
85 | (define_insn_reservation "Y2_L2" 11 | |
86 | (eq_attr "type" "Y2_L2") | |
87 | "Y2|X1") | |
88 | ||
89 | (define_insn_reservation "Y2_miss" 80 | |
90 | (eq_attr "type" "Y2_miss") | |
91 | "Y2|X1") | |
92 | ||
93 | (define_insn_reservation "Y01" 1 | |
94 | (eq_attr "type" "Y01") | |
95 | "Y0|Y1|X0|X1") | |
96 | ||
97 | (define_insn_reservation "nothing" 0 | |
98 | (eq_attr "type" "nothing") | |
99 | "nothing") | |
100 | ||
101 | (define_insn_reservation "cannot_bundle" 1 | |
102 | (eq_attr "type" "cannot_bundle") | |
103 | "X0+X1") | |
104 | ||
105 | (define_insn_reservation "cannot_bundle_3cycle" 3 | |
106 | (eq_attr "type" "cannot_bundle_3cycle") | |
107 | "X0+X1") | |
108 | ||
109 | (define_insn_reservation "cannot_bundle_4cycle" 4 | |
110 | (eq_attr "type" "cannot_bundle_4cycle") | |
111 | "X0+X1") | |
112 | ||
113 | ||
114 | ; A bundle must be in either X format or Y format. | |
115 | (exclusion_set "X0,X1" "Y0,Y1,Y2") |