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7adcbafe | 1 | @c Copyright (C) 1988-2022 Free Software Foundation, Inc. |
03dda8e3 RK |
2 | @c This is part of the GCC manual. |
3 | @c For copying conditions, see the file gcc.texi. | |
4 | ||
5 | @ifset INTERNALS | |
6 | @node Machine Desc | |
7 | @chapter Machine Descriptions | |
8 | @cindex machine descriptions | |
9 | ||
10 | A machine description has two parts: a file of instruction patterns | |
11 | (@file{.md} file) and a C header file of macro definitions. | |
12 | ||
13 | The @file{.md} file for a target machine contains a pattern for each | |
14 | instruction that the target machine supports (or at least each instruction | |
15 | that is worth telling the compiler about). It may also contain comments. | |
16 | A semicolon causes the rest of the line to be a comment, unless the semicolon | |
17 | is inside a quoted string. | |
18 | ||
19 | See the next chapter for information on the C header file. | |
20 | ||
21 | @menu | |
55e4756f | 22 | * Overview:: How the machine description is used. |
03dda8e3 RK |
23 | * Patterns:: How to write instruction patterns. |
24 | * Example:: An explained example of a @code{define_insn} pattern. | |
25 | * RTL Template:: The RTL template defines what insns match a pattern. | |
26 | * Output Template:: The output template says how to make assembler code | |
6ccde948 | 27 | from such an insn. |
03dda8e3 | 28 | * Output Statement:: For more generality, write C code to output |
6ccde948 | 29 | the assembler code. |
e543e219 | 30 | * Predicates:: Controlling what kinds of operands can be used |
6ccde948 | 31 | for an insn. |
e543e219 | 32 | * Constraints:: Fine-tuning operand selection. |
03dda8e3 RK |
33 | * Standard Names:: Names mark patterns to use for code generation. |
34 | * Pattern Ordering:: When the order of patterns makes a difference. | |
35 | * Dependent Patterns:: Having one pattern may make you need another. | |
36 | * Jump Patterns:: Special considerations for patterns for jump insns. | |
6e4fcc95 | 37 | * Looping Patterns:: How to define patterns for special looping insns. |
03dda8e3 | 38 | * Insn Canonicalizations::Canonicalization of Instructions |
03dda8e3 | 39 | * Expander Definitions::Generating a sequence of several RTL insns |
6ccde948 | 40 | for a standard operation. |
f3a3d0d3 | 41 | * Insn Splitting:: Splitting Instructions into Multiple Instructions. |
6ccde948 | 42 | * Including Patterns:: Including Patterns in Machine Descriptions. |
f3a3d0d3 | 43 | * Peephole Definitions::Defining machine-specific peephole optimizations. |
03dda8e3 | 44 | * Insn Attributes:: Specifying the value of attributes for generated insns. |
3262c1f5 | 45 | * Conditional Execution::Generating @code{define_insn} patterns for |
6ccde948 | 46 | predication. |
477c104e MK |
47 | * Define Subst:: Generating @code{define_insn} and @code{define_expand} |
48 | patterns from other patterns. | |
c25c12b8 R |
49 | * Constant Definitions::Defining symbolic constants that can be used in the |
50 | md file. | |
3abcb3a7 | 51 | * Iterators:: Using iterators to generate patterns from a template. |
03dda8e3 RK |
52 | @end menu |
53 | ||
55e4756f DD |
54 | @node Overview |
55 | @section Overview of How the Machine Description is Used | |
56 | ||
57 | There are three main conversions that happen in the compiler: | |
58 | ||
59 | @enumerate | |
60 | ||
61 | @item | |
62 | The front end reads the source code and builds a parse tree. | |
63 | ||
64 | @item | |
65 | The parse tree is used to generate an RTL insn list based on named | |
66 | instruction patterns. | |
67 | ||
68 | @item | |
69 | The insn list is matched against the RTL templates to produce assembler | |
70 | code. | |
71 | ||
72 | @end enumerate | |
73 | ||
74 | For the generate pass, only the names of the insns matter, from either a | |
75 | named @code{define_insn} or a @code{define_expand}. The compiler will | |
76 | choose the pattern with the right name and apply the operands according | |
77 | to the documentation later in this chapter, without regard for the RTL | |
78 | template or operand constraints. Note that the names the compiler looks | |
d7d9c429 | 79 | for are hard-coded in the compiler---it will ignore unnamed patterns and |
55e4756f DD |
80 | patterns with names it doesn't know about, but if you don't provide a |
81 | named pattern it needs, it will abort. | |
82 | ||
83 | If a @code{define_insn} is used, the template given is inserted into the | |
84 | insn list. If a @code{define_expand} is used, one of three things | |
85 | happens, based on the condition logic. The condition logic may manually | |
86 | create new insns for the insn list, say via @code{emit_insn()}, and | |
aee96fe9 | 87 | invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the |
55e4756f DD |
88 | compiler to use an alternate way of performing that task. If it invokes |
89 | neither @code{DONE} nor @code{FAIL}, the template given in the pattern | |
90 | is inserted, as if the @code{define_expand} were a @code{define_insn}. | |
91 | ||
92 | Once the insn list is generated, various optimization passes convert, | |
93 | replace, and rearrange the insns in the insn list. This is where the | |
94 | @code{define_split} and @code{define_peephole} patterns get used, for | |
95 | example. | |
96 | ||
97 | Finally, the insn list's RTL is matched up with the RTL templates in the | |
98 | @code{define_insn} patterns, and those patterns are used to emit the | |
99 | final assembly code. For this purpose, each named @code{define_insn} | |
100 | acts like it's unnamed, since the names are ignored. | |
101 | ||
03dda8e3 RK |
102 | @node Patterns |
103 | @section Everything about Instruction Patterns | |
104 | @cindex patterns | |
105 | @cindex instruction patterns | |
106 | ||
107 | @findex define_insn | |
2f9d3709 JG |
108 | A @code{define_insn} expression is used to define instruction patterns |
109 | to which insns may be matched. A @code{define_insn} expression contains | |
110 | an incomplete RTL expression, with pieces to be filled in later, operand | |
111 | constraints that restrict how the pieces can be filled in, and an output | |
112 | template or C code to generate the assembler output. | |
03dda8e3 RK |
113 | |
114 | A @code{define_insn} is an RTL expression containing four or five operands: | |
115 | ||
116 | @enumerate | |
117 | @item | |
0016d8d9 RS |
118 | An optional name @var{n}. When a name is present, the compiler |
119 | automically generates a C++ function @samp{gen_@var{n}} that takes | |
120 | the operands of the instruction as arguments and returns the instruction's | |
121 | rtx pattern. The compiler also assigns the instruction a unique code | |
122 | @samp{CODE_FOR_@var{n}}, with all such codes belonging to an enum | |
123 | called @code{insn_code}. | |
124 | ||
125 | These names serve one of two purposes. The first is to indicate that the | |
126 | instruction performs a certain standard job for the RTL-generation | |
127 | pass of the compiler, such as a move, an addition, or a conditional | |
128 | jump. The second is to help the target generate certain target-specific | |
129 | operations, such as when implementing target-specific intrinsic functions. | |
130 | ||
131 | It is better to prefix target-specific names with the name of the | |
132 | target, to avoid any clash with current or future standard names. | |
03dda8e3 RK |
133 | |
134 | The absence of a name is indicated by writing an empty string | |
135 | where the name should go. Nameless instruction patterns are never | |
136 | used for generating RTL code, but they may permit several simpler insns | |
137 | to be combined later on. | |
138 | ||
661cb0b7 RK |
139 | For the purpose of debugging the compiler, you may also specify a |
140 | name beginning with the @samp{*} character. Such a name is used only | |
2f9d3709 JG |
141 | for identifying the instruction in RTL dumps; it is equivalent to having |
142 | a nameless pattern for all other purposes. Names beginning with the | |
143 | @samp{*} character are not required to be unique. | |
661cb0b7 | 144 | |
0016d8d9 RS |
145 | The name may also have the form @samp{@@@var{n}}. This has the same |
146 | effect as a name @samp{@var{n}}, but in addition tells the compiler to | |
8bdea528 | 147 | generate further helper functions; see @ref{Parameterized Names} for details. |
0016d8d9 | 148 | |
03dda8e3 | 149 | @item |
2f9d3709 JG |
150 | The @dfn{RTL template}: This is a vector of incomplete RTL expressions |
151 | which describe the semantics of the instruction (@pxref{RTL Template}). | |
152 | It is incomplete because it may contain @code{match_operand}, | |
03dda8e3 RK |
153 | @code{match_operator}, and @code{match_dup} expressions that stand for |
154 | operands of the instruction. | |
155 | ||
2f9d3709 JG |
156 | If the vector has multiple elements, the RTL template is treated as a |
157 | @code{parallel} expression. | |
03dda8e3 RK |
158 | |
159 | @item | |
160 | @cindex pattern conditions | |
161 | @cindex conditions, in patterns | |
2f9d3709 JG |
162 | The condition: This is a string which contains a C expression. When the |
163 | compiler attempts to match RTL against a pattern, the condition is | |
164 | evaluated. If the condition evaluates to @code{true}, the match is | |
165 | permitted. The condition may be an empty string, which is treated | |
166 | as always @code{true}. | |
03dda8e3 RK |
167 | |
168 | @cindex named patterns and conditions | |
2f9d3709 JG |
169 | For a named pattern, the condition may not depend on the data in the |
170 | insn being matched, but only the target-machine-type flags. The compiler | |
171 | needs to test these conditions during initialization in order to learn | |
172 | exactly which named instructions are available in a particular run. | |
03dda8e3 RK |
173 | |
174 | @findex operands | |
175 | For nameless patterns, the condition is applied only when matching an | |
176 | individual insn, and only after the insn has matched the pattern's | |
177 | recognition template. The insn's operands may be found in the vector | |
2f9d3709 JG |
178 | @code{operands}. |
179 | ||
49e478af RS |
180 | An instruction condition cannot become more restrictive as compilation |
181 | progresses. If the condition accepts a particular RTL instruction at | |
182 | one stage of compilation, it must continue to accept that instruction | |
183 | until the final pass. For example, @samp{!reload_completed} and | |
184 | @samp{can_create_pseudo_p ()} are both invalid instruction conditions, | |
185 | because they are true during the earlier RTL passes and false during | |
186 | the later ones. For the same reason, if a condition accepts an | |
187 | instruction before register allocation, it cannot later try to control | |
188 | register allocation by excluding certain register or value combinations. | |
189 | ||
190 | Although a condition cannot become more restrictive as compilation | |
191 | progresses, the condition for a nameless pattern @emph{can} become | |
192 | more permissive. For example, a nameless instruction can require | |
193 | @samp{reload_completed} to be true, in which case it only matches | |
194 | after register allocation. | |
03dda8e3 RK |
195 | |
196 | @item | |
2f9d3709 JG |
197 | The @dfn{output template} or @dfn{output statement}: This is either |
198 | a string, or a fragment of C code which returns a string. | |
03dda8e3 RK |
199 | |
200 | When simple substitution isn't general enough, you can specify a piece | |
201 | of C code to compute the output. @xref{Output Statement}. | |
202 | ||
203 | @item | |
2f9d3709 JG |
204 | The @dfn{insn attributes}: This is an optional vector containing the values of |
205 | attributes for insns matching this pattern (@pxref{Insn Attributes}). | |
03dda8e3 RK |
206 | @end enumerate |
207 | ||
208 | @node Example | |
209 | @section Example of @code{define_insn} | |
210 | @cindex @code{define_insn} example | |
211 | ||
2f9d3709 JG |
212 | Here is an example of an instruction pattern, taken from the machine |
213 | description for the 68000/68020. | |
03dda8e3 | 214 | |
3ab51846 | 215 | @smallexample |
03dda8e3 RK |
216 | (define_insn "tstsi" |
217 | [(set (cc0) | |
218 | (match_operand:SI 0 "general_operand" "rm"))] | |
219 | "" | |
220 | "* | |
f282ffb3 | 221 | @{ |
0f40f9f7 | 222 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) |
03dda8e3 | 223 | return \"tstl %0\"; |
f282ffb3 | 224 | return \"cmpl #0,%0\"; |
0f40f9f7 | 225 | @}") |
3ab51846 | 226 | @end smallexample |
0f40f9f7 ZW |
227 | |
228 | @noindent | |
229 | This can also be written using braced strings: | |
230 | ||
3ab51846 | 231 | @smallexample |
0f40f9f7 ZW |
232 | (define_insn "tstsi" |
233 | [(set (cc0) | |
234 | (match_operand:SI 0 "general_operand" "rm"))] | |
235 | "" | |
f282ffb3 | 236 | @{ |
0f40f9f7 ZW |
237 | if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) |
238 | return "tstl %0"; | |
f282ffb3 | 239 | return "cmpl #0,%0"; |
0f40f9f7 | 240 | @}) |
3ab51846 | 241 | @end smallexample |
03dda8e3 | 242 | |
2f9d3709 JG |
243 | This describes an instruction which sets the condition codes based on the |
244 | value of a general operand. It has no condition, so any insn with an RTL | |
245 | description of the form shown may be matched to this pattern. The name | |
246 | @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL | |
247 | generation pass that, when it is necessary to test such a value, an insn | |
248 | to do so can be constructed using this pattern. | |
03dda8e3 RK |
249 | |
250 | The output control string is a piece of C code which chooses which | |
251 | output template to return based on the kind of operand and the specific | |
252 | type of CPU for which code is being generated. | |
253 | ||
254 | @samp{"rm"} is an operand constraint. Its meaning is explained below. | |
255 | ||
256 | @node RTL Template | |
257 | @section RTL Template | |
258 | @cindex RTL insn template | |
259 | @cindex generating insns | |
260 | @cindex insns, generating | |
261 | @cindex recognizing insns | |
262 | @cindex insns, recognizing | |
263 | ||
264 | The RTL template is used to define which insns match the particular pattern | |
265 | and how to find their operands. For named patterns, the RTL template also | |
266 | says how to construct an insn from specified operands. | |
267 | ||
268 | Construction involves substituting specified operands into a copy of the | |
269 | template. Matching involves determining the values that serve as the | |
270 | operands in the insn being matched. Both of these activities are | |
271 | controlled by special expression types that direct matching and | |
272 | substitution of the operands. | |
273 | ||
274 | @table @code | |
275 | @findex match_operand | |
276 | @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint}) | |
277 | This expression is a placeholder for operand number @var{n} of | |
278 | the insn. When constructing an insn, operand number @var{n} | |
279 | will be substituted at this point. When matching an insn, whatever | |
280 | appears at this position in the insn will be taken as operand | |
281 | number @var{n}; but it must satisfy @var{predicate} or this instruction | |
282 | pattern will not match at all. | |
283 | ||
284 | Operand numbers must be chosen consecutively counting from zero in | |
285 | each instruction pattern. There may be only one @code{match_operand} | |
286 | expression in the pattern for each operand number. Usually operands | |
287 | are numbered in the order of appearance in @code{match_operand} | |
72938a4c MM |
288 | expressions. In the case of a @code{define_expand}, any operand numbers |
289 | used only in @code{match_dup} expressions have higher values than all | |
290 | other operand numbers. | |
03dda8e3 | 291 | |
e543e219 ZW |
292 | @var{predicate} is a string that is the name of a function that |
293 | accepts two arguments, an expression and a machine mode. | |
294 | @xref{Predicates}. During matching, the function will be called with | |
295 | the putative operand as the expression and @var{m} as the mode | |
296 | argument (if @var{m} is not specified, @code{VOIDmode} will be used, | |
297 | which normally causes @var{predicate} to accept any mode). If it | |
298 | returns zero, this instruction pattern fails to match. | |
299 | @var{predicate} may be an empty string; then it means no test is to be | |
300 | done on the operand, so anything which occurs in this position is | |
301 | valid. | |
03dda8e3 RK |
302 | |
303 | Most of the time, @var{predicate} will reject modes other than @var{m}---but | |
304 | not always. For example, the predicate @code{address_operand} uses | |
305 | @var{m} as the mode of memory ref that the address should be valid for. | |
306 | Many predicates accept @code{const_int} nodes even though their mode is | |
307 | @code{VOIDmode}. | |
308 | ||
309 | @var{constraint} controls reloading and the choice of the best register | |
310 | class to use for a value, as explained later (@pxref{Constraints}). | |
e543e219 | 311 | If the constraint would be an empty string, it can be omitted. |
03dda8e3 RK |
312 | |
313 | People are often unclear on the difference between the constraint and the | |
314 | predicate. The predicate helps decide whether a given insn matches the | |
315 | pattern. The constraint plays no role in this decision; instead, it | |
316 | controls various decisions in the case of an insn which does match. | |
317 | ||
03dda8e3 RK |
318 | @findex match_scratch |
319 | @item (match_scratch:@var{m} @var{n} @var{constraint}) | |
320 | This expression is also a placeholder for operand number @var{n} | |
321 | and indicates that operand must be a @code{scratch} or @code{reg} | |
322 | expression. | |
323 | ||
324 | When matching patterns, this is equivalent to | |
325 | ||
326 | @smallexample | |
e80f9fef | 327 | (match_operand:@var{m} @var{n} "scratch_operand" @var{constraint}) |
03dda8e3 RK |
328 | @end smallexample |
329 | ||
330 | but, when generating RTL, it produces a (@code{scratch}:@var{m}) | |
331 | expression. | |
332 | ||
333 | If the last few expressions in a @code{parallel} are @code{clobber} | |
334 | expressions whose operands are either a hard register or | |
335 | @code{match_scratch}, the combiner can add or delete them when | |
336 | necessary. @xref{Side Effects}. | |
337 | ||
338 | @findex match_dup | |
339 | @item (match_dup @var{n}) | |
340 | This expression is also a placeholder for operand number @var{n}. | |
341 | It is used when the operand needs to appear more than once in the | |
342 | insn. | |
343 | ||
344 | In construction, @code{match_dup} acts just like @code{match_operand}: | |
345 | the operand is substituted into the insn being constructed. But in | |
346 | matching, @code{match_dup} behaves differently. It assumes that operand | |
347 | number @var{n} has already been determined by a @code{match_operand} | |
348 | appearing earlier in the recognition template, and it matches only an | |
349 | identical-looking expression. | |
350 | ||
55e4756f DD |
351 | Note that @code{match_dup} should not be used to tell the compiler that |
352 | a particular register is being used for two operands (example: | |
353 | @code{add} that adds one register to another; the second register is | |
354 | both an input operand and the output operand). Use a matching | |
355 | constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one | |
356 | operand is used in two places in the template, such as an instruction | |
357 | that computes both a quotient and a remainder, where the opcode takes | |
358 | two input operands but the RTL template has to refer to each of those | |
359 | twice; once for the quotient pattern and once for the remainder pattern. | |
360 | ||
03dda8e3 RK |
361 | @findex match_operator |
362 | @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}]) | |
363 | This pattern is a kind of placeholder for a variable RTL expression | |
364 | code. | |
365 | ||
366 | When constructing an insn, it stands for an RTL expression whose | |
367 | expression code is taken from that of operand @var{n}, and whose | |
368 | operands are constructed from the patterns @var{operands}. | |
369 | ||
370 | When matching an expression, it matches an expression if the function | |
371 | @var{predicate} returns nonzero on that expression @emph{and} the | |
372 | patterns @var{operands} match the operands of the expression. | |
373 | ||
374 | Suppose that the function @code{commutative_operator} is defined as | |
375 | follows, to match any expression whose operator is one of the | |
376 | commutative arithmetic operators of RTL and whose mode is @var{mode}: | |
377 | ||
378 | @smallexample | |
379 | int | |
ec8e098d | 380 | commutative_integer_operator (x, mode) |
03dda8e3 | 381 | rtx x; |
ef4bddc2 | 382 | machine_mode mode; |
03dda8e3 RK |
383 | @{ |
384 | enum rtx_code code = GET_CODE (x); | |
385 | if (GET_MODE (x) != mode) | |
386 | return 0; | |
ec8e098d | 387 | return (GET_RTX_CLASS (code) == RTX_COMM_ARITH |
03dda8e3 RK |
388 | || code == EQ || code == NE); |
389 | @} | |
390 | @end smallexample | |
391 | ||
392 | Then the following pattern will match any RTL expression consisting | |
393 | of a commutative operator applied to two general operands: | |
394 | ||
395 | @smallexample | |
396 | (match_operator:SI 3 "commutative_operator" | |
397 | [(match_operand:SI 1 "general_operand" "g") | |
398 | (match_operand:SI 2 "general_operand" "g")]) | |
399 | @end smallexample | |
400 | ||
401 | Here the vector @code{[@var{operands}@dots{}]} contains two patterns | |
402 | because the expressions to be matched all contain two operands. | |
403 | ||
404 | When this pattern does match, the two operands of the commutative | |
405 | operator are recorded as operands 1 and 2 of the insn. (This is done | |
406 | by the two instances of @code{match_operand}.) Operand 3 of the insn | |
407 | will be the entire commutative expression: use @code{GET_CODE | |
408 | (operands[3])} to see which commutative operator was used. | |
409 | ||
410 | The machine mode @var{m} of @code{match_operator} works like that of | |
411 | @code{match_operand}: it is passed as the second argument to the | |
412 | predicate function, and that function is solely responsible for | |
413 | deciding whether the expression to be matched ``has'' that mode. | |
414 | ||
415 | When constructing an insn, argument 3 of the gen-function will specify | |
e979f9e8 | 416 | the operation (i.e.@: the expression code) for the expression to be |
03dda8e3 RK |
417 | made. It should be an RTL expression, whose expression code is copied |
418 | into a new expression whose operands are arguments 1 and 2 of the | |
419 | gen-function. The subexpressions of argument 3 are not used; | |
420 | only its expression code matters. | |
421 | ||
422 | When @code{match_operator} is used in a pattern for matching an insn, | |
423 | it usually best if the operand number of the @code{match_operator} | |
424 | is higher than that of the actual operands of the insn. This improves | |
425 | register allocation because the register allocator often looks at | |
426 | operands 1 and 2 of insns to see if it can do register tying. | |
427 | ||
428 | There is no way to specify constraints in @code{match_operator}. The | |
429 | operand of the insn which corresponds to the @code{match_operator} | |
430 | never has any constraints because it is never reloaded as a whole. | |
431 | However, if parts of its @var{operands} are matched by | |
432 | @code{match_operand} patterns, those parts may have constraints of | |
433 | their own. | |
434 | ||
435 | @findex match_op_dup | |
436 | @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}]) | |
437 | Like @code{match_dup}, except that it applies to operators instead of | |
438 | operands. When constructing an insn, operand number @var{n} will be | |
439 | substituted at this point. But in matching, @code{match_op_dup} behaves | |
440 | differently. It assumes that operand number @var{n} has already been | |
441 | determined by a @code{match_operator} appearing earlier in the | |
442 | recognition template, and it matches only an identical-looking | |
443 | expression. | |
444 | ||
445 | @findex match_parallel | |
446 | @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}]) | |
447 | This pattern is a placeholder for an insn that consists of a | |
448 | @code{parallel} expression with a variable number of elements. This | |
449 | expression should only appear at the top level of an insn pattern. | |
450 | ||
451 | When constructing an insn, operand number @var{n} will be substituted at | |
452 | this point. When matching an insn, it matches if the body of the insn | |
453 | is a @code{parallel} expression with at least as many elements as the | |
454 | vector of @var{subpat} expressions in the @code{match_parallel}, if each | |
455 | @var{subpat} matches the corresponding element of the @code{parallel}, | |
456 | @emph{and} the function @var{predicate} returns nonzero on the | |
457 | @code{parallel} that is the body of the insn. It is the responsibility | |
458 | of the predicate to validate elements of the @code{parallel} beyond | |
bd819a4a | 459 | those listed in the @code{match_parallel}. |
03dda8e3 RK |
460 | |
461 | A typical use of @code{match_parallel} is to match load and store | |
462 | multiple expressions, which can contain a variable number of elements | |
463 | in a @code{parallel}. For example, | |
03dda8e3 RK |
464 | |
465 | @smallexample | |
466 | (define_insn "" | |
467 | [(match_parallel 0 "load_multiple_operation" | |
468 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
469 | (match_operand:SI 2 "memory_operand" "m")) | |
470 | (use (reg:SI 179)) | |
471 | (clobber (reg:SI 179))])] | |
472 | "" | |
473 | "loadm 0,0,%1,%2") | |
474 | @end smallexample | |
475 | ||
476 | This example comes from @file{a29k.md}. The function | |
9c34dbbf | 477 | @code{load_multiple_operation} is defined in @file{a29k.c} and checks |
03dda8e3 RK |
478 | that subsequent elements in the @code{parallel} are the same as the |
479 | @code{set} in the pattern, except that they are referencing subsequent | |
480 | registers and memory locations. | |
481 | ||
482 | An insn that matches this pattern might look like: | |
483 | ||
484 | @smallexample | |
485 | (parallel | |
486 | [(set (reg:SI 20) (mem:SI (reg:SI 100))) | |
487 | (use (reg:SI 179)) | |
488 | (clobber (reg:SI 179)) | |
489 | (set (reg:SI 21) | |
490 | (mem:SI (plus:SI (reg:SI 100) | |
491 | (const_int 4)))) | |
492 | (set (reg:SI 22) | |
493 | (mem:SI (plus:SI (reg:SI 100) | |
494 | (const_int 8))))]) | |
495 | @end smallexample | |
496 | ||
497 | @findex match_par_dup | |
498 | @item (match_par_dup @var{n} [@var{subpat}@dots{}]) | |
499 | Like @code{match_op_dup}, but for @code{match_parallel} instead of | |
500 | @code{match_operator}. | |
501 | ||
03dda8e3 RK |
502 | @end table |
503 | ||
504 | @node Output Template | |
505 | @section Output Templates and Operand Substitution | |
506 | @cindex output templates | |
507 | @cindex operand substitution | |
508 | ||
509 | @cindex @samp{%} in template | |
510 | @cindex percent sign | |
511 | The @dfn{output template} is a string which specifies how to output the | |
512 | assembler code for an instruction pattern. Most of the template is a | |
513 | fixed string which is output literally. The character @samp{%} is used | |
514 | to specify where to substitute an operand; it can also be used to | |
515 | identify places where different variants of the assembler require | |
516 | different syntax. | |
517 | ||
518 | In the simplest case, a @samp{%} followed by a digit @var{n} says to output | |
519 | operand @var{n} at that point in the string. | |
520 | ||
521 | @samp{%} followed by a letter and a digit says to output an operand in an | |
522 | alternate fashion. Four letters have standard, built-in meanings described | |
523 | below. The machine description macro @code{PRINT_OPERAND} can define | |
524 | additional letters with nonstandard meanings. | |
525 | ||
526 | @samp{%c@var{digit}} can be used to substitute an operand that is a | |
527 | constant value without the syntax that normally indicates an immediate | |
528 | operand. | |
529 | ||
530 | @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of | |
531 | the constant is negated before printing. | |
532 | ||
533 | @samp{%a@var{digit}} can be used to substitute an operand as if it were a | |
534 | memory reference, with the actual operand treated as the address. This may | |
535 | be useful when outputting a ``load address'' instruction, because often the | |
536 | assembler syntax for such an instruction requires you to write the operand | |
537 | as if it were a memory reference. | |
538 | ||
539 | @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump | |
540 | instruction. | |
541 | ||
542 | @samp{%=} outputs a number which is unique to each instruction in the | |
543 | entire compilation. This is useful for making local labels to be | |
544 | referred to more than once in a single template that generates multiple | |
545 | assembler instructions. | |
546 | ||
547 | @samp{%} followed by a punctuation character specifies a substitution that | |
548 | does not use an operand. Only one case is standard: @samp{%%} outputs a | |
549 | @samp{%} into the assembler code. Other nonstandard cases can be | |
550 | defined in the @code{PRINT_OPERAND} macro. You must also define | |
551 | which punctuation characters are valid with the | |
552 | @code{PRINT_OPERAND_PUNCT_VALID_P} macro. | |
553 | ||
554 | @cindex \ | |
555 | @cindex backslash | |
556 | The template may generate multiple assembler instructions. Write the text | |
557 | for the instructions, with @samp{\;} between them. | |
558 | ||
559 | @cindex matching operands | |
560 | When the RTL contains two operands which are required by constraint to match | |
561 | each other, the output template must refer only to the lower-numbered operand. | |
562 | Matching operands are not always identical, and the rest of the compiler | |
563 | arranges to put the proper RTL expression for printing into the lower-numbered | |
564 | operand. | |
565 | ||
566 | One use of nonstandard letters or punctuation following @samp{%} is to | |
567 | distinguish between different assembler languages for the same machine; for | |
568 | example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax | |
569 | requires periods in most opcode names, while MIT syntax does not. For | |
570 | example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola | |
571 | syntax. The same file of patterns is used for both kinds of output syntax, | |
572 | but the character sequence @samp{%.} is used in each place where Motorola | |
573 | syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax | |
574 | defines the sequence to output a period; the macro for MIT syntax defines | |
575 | it to do nothing. | |
576 | ||
577 | @cindex @code{#} in template | |
578 | As a special case, a template consisting of the single character @code{#} | |
579 | instructs the compiler to first split the insn, and then output the | |
580 | resulting instructions separately. This helps eliminate redundancy in the | |
581 | output templates. If you have a @code{define_insn} that needs to emit | |
e4ae5e77 | 582 | multiple assembler instructions, and there is a matching @code{define_split} |
03dda8e3 RK |
583 | already defined, then you can simply use @code{#} as the output template |
584 | instead of writing an output template that emits the multiple assembler | |
585 | instructions. | |
586 | ||
49e478af RS |
587 | Note that @code{#} only has an effect while generating assembly code; |
588 | it does not affect whether a split occurs earlier. An associated | |
589 | @code{define_split} must exist and it must be suitable for use after | |
590 | register allocation. | |
591 | ||
03dda8e3 RK |
592 | If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct |
593 | of the form @samp{@{option0|option1|option2@}} in the templates. These | |
594 | describe multiple variants of assembler language syntax. | |
595 | @xref{Instruction Output}. | |
596 | ||
597 | @node Output Statement | |
598 | @section C Statements for Assembler Output | |
599 | @cindex output statements | |
600 | @cindex C statements for assembler output | |
601 | @cindex generating assembler output | |
602 | ||
603 | Often a single fixed template string cannot produce correct and efficient | |
604 | assembler code for all the cases that are recognized by a single | |
605 | instruction pattern. For example, the opcodes may depend on the kinds of | |
606 | operands; or some unfortunate combinations of operands may require extra | |
607 | machine instructions. | |
608 | ||
609 | If the output control string starts with a @samp{@@}, then it is actually | |
610 | a series of templates, each on a separate line. (Blank lines and | |
611 | leading spaces and tabs are ignored.) The templates correspond to the | |
612 | pattern's constraint alternatives (@pxref{Multi-Alternative}). For example, | |
613 | if a target machine has a two-address add instruction @samp{addr} to add | |
614 | into a register and another @samp{addm} to add a register to memory, you | |
615 | might write this pattern: | |
616 | ||
617 | @smallexample | |
618 | (define_insn "addsi3" | |
619 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
620 | (plus:SI (match_operand:SI 1 "general_operand" "0,0") | |
621 | (match_operand:SI 2 "general_operand" "g,r")))] | |
622 | "" | |
623 | "@@ | |
624 | addr %2,%0 | |
625 | addm %2,%0") | |
626 | @end smallexample | |
627 | ||
628 | @cindex @code{*} in template | |
629 | @cindex asterisk in template | |
630 | If the output control string starts with a @samp{*}, then it is not an | |
631 | output template but rather a piece of C program that should compute a | |
632 | template. It should execute a @code{return} statement to return the | |
633 | template-string you want. Most such templates use C string literals, which | |
634 | require doublequote characters to delimit them. To include these | |
635 | doublequote characters in the string, prefix each one with @samp{\}. | |
636 | ||
0f40f9f7 ZW |
637 | If the output control string is written as a brace block instead of a |
638 | double-quoted string, it is automatically assumed to be C code. In that | |
639 | case, it is not necessary to put in a leading asterisk, or to escape the | |
640 | doublequotes surrounding C string literals. | |
641 | ||
03dda8e3 RK |
642 | The operands may be found in the array @code{operands}, whose C data type |
643 | is @code{rtx []}. | |
644 | ||
645 | It is very common to select different ways of generating assembler code | |
646 | based on whether an immediate operand is within a certain range. Be | |
647 | careful when doing this, because the result of @code{INTVAL} is an | |
648 | integer on the host machine. If the host machine has more bits in an | |
649 | @code{int} than the target machine has in the mode in which the constant | |
650 | will be used, then some of the bits you get from @code{INTVAL} will be | |
651 | superfluous. For proper results, you must carefully disregard the | |
652 | values of those bits. | |
653 | ||
654 | @findex output_asm_insn | |
655 | It is possible to output an assembler instruction and then go on to output | |
656 | or compute more of them, using the subroutine @code{output_asm_insn}. This | |
657 | receives two arguments: a template-string and a vector of operands. The | |
658 | vector may be @code{operands}, or it may be another array of @code{rtx} | |
659 | that you declare locally and initialize yourself. | |
660 | ||
661 | @findex which_alternative | |
662 | When an insn pattern has multiple alternatives in its constraints, often | |
663 | the appearance of the assembler code is determined mostly by which alternative | |
664 | was matched. When this is so, the C code can test the variable | |
665 | @code{which_alternative}, which is the ordinal number of the alternative | |
666 | that was actually satisfied (0 for the first, 1 for the second alternative, | |
667 | etc.). | |
668 | ||
669 | For example, suppose there are two opcodes for storing zero, @samp{clrreg} | |
670 | for registers and @samp{clrmem} for memory locations. Here is how | |
671 | a pattern could use @code{which_alternative} to choose between them: | |
672 | ||
673 | @smallexample | |
674 | (define_insn "" | |
675 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
676 | (const_int 0))] | |
677 | "" | |
0f40f9f7 | 678 | @{ |
03dda8e3 | 679 | return (which_alternative == 0 |
0f40f9f7 ZW |
680 | ? "clrreg %0" : "clrmem %0"); |
681 | @}) | |
03dda8e3 RK |
682 | @end smallexample |
683 | ||
684 | The example above, where the assembler code to generate was | |
685 | @emph{solely} determined by the alternative, could also have been specified | |
686 | as follows, having the output control string start with a @samp{@@}: | |
687 | ||
688 | @smallexample | |
689 | @group | |
690 | (define_insn "" | |
691 | [(set (match_operand:SI 0 "general_operand" "=r,m") | |
692 | (const_int 0))] | |
693 | "" | |
694 | "@@ | |
695 | clrreg %0 | |
696 | clrmem %0") | |
697 | @end group | |
698 | @end smallexample | |
e543e219 | 699 | |
94c765ab R |
700 | If you just need a little bit of C code in one (or a few) alternatives, |
701 | you can use @samp{*} inside of a @samp{@@} multi-alternative template: | |
702 | ||
703 | @smallexample | |
704 | @group | |
705 | (define_insn "" | |
706 | [(set (match_operand:SI 0 "general_operand" "=r,<,m") | |
707 | (const_int 0))] | |
708 | "" | |
709 | "@@ | |
710 | clrreg %0 | |
711 | * return stack_mem_p (operands[0]) ? \"push 0\" : \"clrmem %0\"; | |
712 | clrmem %0") | |
713 | @end group | |
714 | @end smallexample | |
715 | ||
e543e219 ZW |
716 | @node Predicates |
717 | @section Predicates | |
718 | @cindex predicates | |
719 | @cindex operand predicates | |
720 | @cindex operator predicates | |
721 | ||
722 | A predicate determines whether a @code{match_operand} or | |
723 | @code{match_operator} expression matches, and therefore whether the | |
724 | surrounding instruction pattern will be used for that combination of | |
725 | operands. GCC has a number of machine-independent predicates, and you | |
726 | can define machine-specific predicates as needed. By convention, | |
727 | predicates used with @code{match_operand} have names that end in | |
728 | @samp{_operand}, and those used with @code{match_operator} have names | |
729 | that end in @samp{_operator}. | |
730 | ||
527a3750 | 731 | All predicates are boolean functions (in the mathematical sense) of |
e543e219 ZW |
732 | two arguments: the RTL expression that is being considered at that |
733 | position in the instruction pattern, and the machine mode that the | |
734 | @code{match_operand} or @code{match_operator} specifies. In this | |
735 | section, the first argument is called @var{op} and the second argument | |
736 | @var{mode}. Predicates can be called from C as ordinary two-argument | |
737 | functions; this can be useful in output templates or other | |
738 | machine-specific code. | |
739 | ||
740 | Operand predicates can allow operands that are not actually acceptable | |
741 | to the hardware, as long as the constraints give reload the ability to | |
742 | fix them up (@pxref{Constraints}). However, GCC will usually generate | |
743 | better code if the predicates specify the requirements of the machine | |
744 | instructions as closely as possible. Reload cannot fix up operands | |
745 | that must be constants (``immediate operands''); you must use a | |
746 | predicate that allows only constants, or else enforce the requirement | |
747 | in the extra condition. | |
748 | ||
749 | @cindex predicates and machine modes | |
750 | @cindex normal predicates | |
751 | @cindex special predicates | |
752 | Most predicates handle their @var{mode} argument in a uniform manner. | |
753 | If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have | |
754 | any mode. If @var{mode} is anything else, then @var{op} must have the | |
755 | same mode, unless @var{op} is a @code{CONST_INT} or integer | |
756 | @code{CONST_DOUBLE}. These RTL expressions always have | |
757 | @code{VOIDmode}, so it would be counterproductive to check that their | |
758 | mode matches. Instead, predicates that accept @code{CONST_INT} and/or | |
759 | integer @code{CONST_DOUBLE} check that the value stored in the | |
760 | constant will fit in the requested mode. | |
761 | ||
762 | Predicates with this behavior are called @dfn{normal}. | |
763 | @command{genrecog} can optimize the instruction recognizer based on | |
764 | knowledge of how normal predicates treat modes. It can also diagnose | |
765 | certain kinds of common errors in the use of normal predicates; for | |
766 | instance, it is almost always an error to use a normal predicate | |
767 | without specifying a mode. | |
768 | ||
769 | Predicates that do something different with their @var{mode} argument | |
770 | are called @dfn{special}. The generic predicates | |
771 | @code{address_operand} and @code{pmode_register_operand} are special | |
772 | predicates. @command{genrecog} does not do any optimizations or | |
773 | diagnosis when special predicates are used. | |
774 | ||
775 | @menu | |
776 | * Machine-Independent Predicates:: Predicates available to all back ends. | |
777 | * Defining Predicates:: How to write machine-specific predicate | |
778 | functions. | |
779 | @end menu | |
780 | ||
781 | @node Machine-Independent Predicates | |
782 | @subsection Machine-Independent Predicates | |
783 | @cindex machine-independent predicates | |
784 | @cindex generic predicates | |
785 | ||
786 | These are the generic predicates available to all back ends. They are | |
e53b6e56 | 787 | defined in @file{recog.cc}. The first category of predicates allow |
e543e219 ZW |
788 | only constant, or @dfn{immediate}, operands. |
789 | ||
790 | @defun immediate_operand | |
791 | This predicate allows any sort of constant that fits in @var{mode}. | |
792 | It is an appropriate choice for instructions that take operands that | |
793 | must be constant. | |
794 | @end defun | |
795 | ||
796 | @defun const_int_operand | |
797 | This predicate allows any @code{CONST_INT} expression that fits in | |
798 | @var{mode}. It is an appropriate choice for an immediate operand that | |
799 | does not allow a symbol or label. | |
800 | @end defun | |
801 | ||
802 | @defun const_double_operand | |
803 | This predicate accepts any @code{CONST_DOUBLE} expression that has | |
804 | exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also | |
805 | accept @code{CONST_INT}. It is intended for immediate floating point | |
806 | constants. | |
807 | @end defun | |
808 | ||
809 | @noindent | |
810 | The second category of predicates allow only some kind of machine | |
811 | register. | |
812 | ||
813 | @defun register_operand | |
814 | This predicate allows any @code{REG} or @code{SUBREG} expression that | |
815 | is valid for @var{mode}. It is often suitable for arithmetic | |
816 | instruction operands on a RISC machine. | |
817 | @end defun | |
818 | ||
819 | @defun pmode_register_operand | |
820 | This is a slight variant on @code{register_operand} which works around | |
821 | a limitation in the machine-description reader. | |
822 | ||
cd1a8088 | 823 | @smallexample |
e543e219 | 824 | (match_operand @var{n} "pmode_register_operand" @var{constraint}) |
cd1a8088 | 825 | @end smallexample |
e543e219 ZW |
826 | |
827 | @noindent | |
828 | means exactly what | |
829 | ||
cd1a8088 | 830 | @smallexample |
e543e219 | 831 | (match_operand:P @var{n} "register_operand" @var{constraint}) |
cd1a8088 | 832 | @end smallexample |
e543e219 ZW |
833 | |
834 | @noindent | |
835 | would mean, if the machine-description reader accepted @samp{:P} | |
836 | mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an | |
837 | alias for some other mode, and might vary with machine-specific | |
8a36672b | 838 | options. @xref{Misc}. |
e543e219 ZW |
839 | @end defun |
840 | ||
841 | @defun scratch_operand | |
842 | This predicate allows hard registers and @code{SCRATCH} expressions, | |
843 | but not pseudo-registers. It is used internally by @code{match_scratch}; | |
844 | it should not be used directly. | |
845 | @end defun | |
846 | ||
847 | @noindent | |
848 | The third category of predicates allow only some kind of memory reference. | |
849 | ||
850 | @defun memory_operand | |
851 | This predicate allows any valid reference to a quantity of mode | |
852 | @var{mode} in memory, as determined by the weak form of | |
853 | @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}). | |
854 | @end defun | |
855 | ||
856 | @defun address_operand | |
857 | This predicate is a little unusual; it allows any operand that is a | |
858 | valid expression for the @emph{address} of a quantity of mode | |
859 | @var{mode}, again determined by the weak form of | |
860 | @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if | |
861 | @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to | |
862 | @code{memory_operand}, then @var{exp} is acceptable to | |
863 | @code{address_operand}. Note that @var{exp} does not necessarily have | |
864 | the mode @var{mode}. | |
865 | @end defun | |
866 | ||
867 | @defun indirect_operand | |
868 | This is a stricter form of @code{memory_operand} which allows only | |
869 | memory references with a @code{general_operand} as the address | |
870 | expression. New uses of this predicate are discouraged, because | |
871 | @code{general_operand} is very permissive, so it's hard to tell what | |
872 | an @code{indirect_operand} does or does not allow. If a target has | |
873 | different requirements for memory operands for different instructions, | |
874 | it is better to define target-specific predicates which enforce the | |
875 | hardware's requirements explicitly. | |
876 | @end defun | |
877 | ||
878 | @defun push_operand | |
879 | This predicate allows a memory reference suitable for pushing a value | |
880 | onto the stack. This will be a @code{MEM} which refers to | |
df18c24a | 881 | @code{stack_pointer_rtx}, with a side effect in its address expression |
e543e219 ZW |
882 | (@pxref{Incdec}); which one is determined by the |
883 | @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}). | |
884 | @end defun | |
885 | ||
886 | @defun pop_operand | |
887 | This predicate allows a memory reference suitable for popping a value | |
888 | off the stack. Again, this will be a @code{MEM} referring to | |
df18c24a | 889 | @code{stack_pointer_rtx}, with a side effect in its address |
e543e219 ZW |
890 | expression. However, this time @code{STACK_POP_CODE} is expected. |
891 | @end defun | |
892 | ||
893 | @noindent | |
894 | The fourth category of predicates allow some combination of the above | |
895 | operands. | |
896 | ||
897 | @defun nonmemory_operand | |
898 | This predicate allows any immediate or register operand valid for @var{mode}. | |
899 | @end defun | |
900 | ||
901 | @defun nonimmediate_operand | |
902 | This predicate allows any register or memory operand valid for @var{mode}. | |
903 | @end defun | |
904 | ||
905 | @defun general_operand | |
906 | This predicate allows any immediate, register, or memory operand | |
907 | valid for @var{mode}. | |
908 | @end defun | |
909 | ||
910 | @noindent | |
c6963675 | 911 | Finally, there are two generic operator predicates. |
e543e219 ZW |
912 | |
913 | @defun comparison_operator | |
914 | This predicate matches any expression which performs an arithmetic | |
915 | comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the | |
916 | expression code. | |
917 | @end defun | |
918 | ||
c6963675 PB |
919 | @defun ordered_comparison_operator |
920 | This predicate matches any expression which performs an arithmetic | |
921 | comparison in @var{mode} and whose expression code is valid for integer | |
922 | modes; that is, the expression code will be one of @code{eq}, @code{ne}, | |
923 | @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu}, | |
924 | @code{ge}, @code{geu}. | |
925 | @end defun | |
926 | ||
e543e219 ZW |
927 | @node Defining Predicates |
928 | @subsection Defining Machine-Specific Predicates | |
929 | @cindex defining predicates | |
930 | @findex define_predicate | |
931 | @findex define_special_predicate | |
932 | ||
933 | Many machines have requirements for their operands that cannot be | |
934 | expressed precisely using the generic predicates. You can define | |
935 | additional predicates using @code{define_predicate} and | |
936 | @code{define_special_predicate} expressions. These expressions have | |
937 | three operands: | |
938 | ||
939 | @itemize @bullet | |
940 | @item | |
941 | The name of the predicate, as it will be referred to in | |
942 | @code{match_operand} or @code{match_operator} expressions. | |
943 | ||
944 | @item | |
945 | An RTL expression which evaluates to true if the predicate allows the | |
946 | operand @var{op}, false if it does not. This expression can only use | |
947 | the following RTL codes: | |
948 | ||
949 | @table @code | |
950 | @item MATCH_OPERAND | |
951 | When written inside a predicate expression, a @code{MATCH_OPERAND} | |
952 | expression evaluates to true if the predicate it names would allow | |
953 | @var{op}. The operand number and constraint are ignored. Due to | |
954 | limitations in @command{genrecog}, you can only refer to generic | |
955 | predicates and predicates that have already been defined. | |
956 | ||
957 | @item MATCH_CODE | |
6e7a4706 ZW |
958 | This expression evaluates to true if @var{op} or a specified |
959 | subexpression of @var{op} has one of a given list of RTX codes. | |
960 | ||
961 | The first operand of this expression is a string constant containing a | |
962 | comma-separated list of RTX code names (in lower case). These are the | |
963 | codes for which the @code{MATCH_CODE} will be true. | |
964 | ||
965 | The second operand is a string constant which indicates what | |
966 | subexpression of @var{op} to examine. If it is absent or the empty | |
967 | string, @var{op} itself is examined. Otherwise, the string constant | |
968 | must be a sequence of digits and/or lowercase letters. Each character | |
969 | indicates a subexpression to extract from the current expression; for | |
970 | the first character this is @var{op}, for the second and subsequent | |
971 | characters it is the result of the previous character. A digit | |
972 | @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l} | |
973 | extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the | |
974 | alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The | |
975 | @code{MATCH_CODE} then examines the RTX code of the subexpression | |
976 | extracted by the complete string. It is not possible to extract | |
977 | components of an @code{rtvec} that is not at position 0 within its RTX | |
978 | object. | |
e543e219 ZW |
979 | |
980 | @item MATCH_TEST | |
981 | This expression has one operand, a string constant containing a C | |
982 | expression. The predicate's arguments, @var{op} and @var{mode}, are | |
983 | available with those names in the C expression. The @code{MATCH_TEST} | |
984 | evaluates to true if the C expression evaluates to a nonzero value. | |
985 | @code{MATCH_TEST} expressions must not have side effects. | |
986 | ||
987 | @item AND | |
988 | @itemx IOR | |
989 | @itemx NOT | |
990 | @itemx IF_THEN_ELSE | |
991 | The basic @samp{MATCH_} expressions can be combined using these | |
992 | logical operators, which have the semantics of the C operators | |
6e7a4706 ZW |
993 | @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As |
994 | in Common Lisp, you may give an @code{AND} or @code{IOR} expression an | |
995 | arbitrary number of arguments; this has exactly the same effect as | |
996 | writing a chain of two-argument @code{AND} or @code{IOR} expressions. | |
e543e219 ZW |
997 | @end table |
998 | ||
999 | @item | |
f0eb93a8 | 1000 | An optional block of C code, which should execute |
e543e219 ZW |
1001 | @samp{@w{return true}} if the predicate is found to match and |
1002 | @samp{@w{return false}} if it does not. It must not have any side | |
1003 | effects. The predicate arguments, @var{op} and @var{mode}, are | |
1004 | available with those names. | |
1005 | ||
1006 | If a code block is present in a predicate definition, then the RTL | |
1007 | expression must evaluate to true @emph{and} the code block must | |
1008 | execute @samp{@w{return true}} for the predicate to allow the operand. | |
1009 | The RTL expression is evaluated first; do not re-check anything in the | |
1010 | code block that was checked in the RTL expression. | |
1011 | @end itemize | |
1012 | ||
1013 | The program @command{genrecog} scans @code{define_predicate} and | |
1014 | @code{define_special_predicate} expressions to determine which RTX | |
1015 | codes are possibly allowed. You should always make this explicit in | |
1016 | the RTL predicate expression, using @code{MATCH_OPERAND} and | |
1017 | @code{MATCH_CODE}. | |
1018 | ||
1019 | Here is an example of a simple predicate definition, from the IA64 | |
1020 | machine description: | |
1021 | ||
1022 | @smallexample | |
1023 | @group | |
1024 | ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.} | |
1025 | (define_predicate "small_addr_symbolic_operand" | |
1026 | (and (match_code "symbol_ref") | |
1027 | (match_test "SYMBOL_REF_SMALL_ADDR_P (op)"))) | |
1028 | @end group | |
1029 | @end smallexample | |
1030 | ||
1031 | @noindent | |
1032 | And here is another, showing the use of the C block. | |
1033 | ||
1034 | @smallexample | |
1035 | @group | |
1036 | ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.} | |
1037 | (define_predicate "gr_register_operand" | |
1038 | (match_operand 0 "register_operand") | |
1039 | @{ | |
1040 | unsigned int regno; | |
1041 | if (GET_CODE (op) == SUBREG) | |
1042 | op = SUBREG_REG (op); | |
1043 | ||
1044 | regno = REGNO (op); | |
1045 | return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno)); | |
1046 | @}) | |
1047 | @end group | |
1048 | @end smallexample | |
1049 | ||
1050 | Predicates written with @code{define_predicate} automatically include | |
1051 | a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same | |
1052 | mode as @var{mode}, or @var{op} is a @code{CONST_INT} or | |
1053 | @code{CONST_DOUBLE}. They do @emph{not} check specifically for | |
1054 | integer @code{CONST_DOUBLE}, nor do they test that the value of either | |
1055 | kind of constant fits in the requested mode. This is because | |
1056 | target-specific predicates that take constants usually have to do more | |
1057 | stringent value checks anyway. If you need the exact same treatment | |
1058 | of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates | |
1059 | provide, use a @code{MATCH_OPERAND} subexpression to call | |
1060 | @code{const_int_operand}, @code{const_double_operand}, or | |
1061 | @code{immediate_operand}. | |
1062 | ||
1063 | Predicates written with @code{define_special_predicate} do not get any | |
1064 | automatic mode checks, and are treated as having special mode handling | |
1065 | by @command{genrecog}. | |
1066 | ||
1067 | The program @command{genpreds} is responsible for generating code to | |
1068 | test predicates. It also writes a header file containing function | |
1069 | declarations for all machine-specific predicates. It is not necessary | |
1070 | to declare these predicates in @file{@var{cpu}-protos.h}. | |
03dda8e3 RK |
1071 | @end ifset |
1072 | ||
1073 | @c Most of this node appears by itself (in a different place) even | |
b11cc610 JM |
1074 | @c when the INTERNALS flag is clear. Passages that require the internals |
1075 | @c manual's context are conditionalized to appear only in the internals manual. | |
03dda8e3 RK |
1076 | @ifset INTERNALS |
1077 | @node Constraints | |
1078 | @section Operand Constraints | |
1079 | @cindex operand constraints | |
1080 | @cindex constraints | |
1081 | ||
e543e219 ZW |
1082 | Each @code{match_operand} in an instruction pattern can specify |
1083 | constraints for the operands allowed. The constraints allow you to | |
1084 | fine-tune matching within the set of operands allowed by the | |
1085 | predicate. | |
1086 | ||
03dda8e3 RK |
1087 | @end ifset |
1088 | @ifclear INTERNALS | |
1089 | @node Constraints | |
1090 | @section Constraints for @code{asm} Operands | |
1091 | @cindex operand constraints, @code{asm} | |
1092 | @cindex constraints, @code{asm} | |
1093 | @cindex @code{asm} constraints | |
1094 | ||
1095 | Here are specific details on what constraint letters you can use with | |
1096 | @code{asm} operands. | |
1097 | @end ifclear | |
1098 | Constraints can say whether | |
1099 | an operand may be in a register, and which kinds of register; whether the | |
1100 | operand can be a memory reference, and which kinds of address; whether the | |
1101 | operand may be an immediate constant, and which possible values it may | |
1102 | have. Constraints can also require two operands to match. | |
54f044eb JJ |
1103 | Side-effects aren't allowed in operands of inline @code{asm}, unless |
1104 | @samp{<} or @samp{>} constraints are used, because there is no guarantee | |
df18c24a | 1105 | that the side effects will happen exactly once in an instruction that can update |
54f044eb | 1106 | the addressing register. |
03dda8e3 RK |
1107 | |
1108 | @ifset INTERNALS | |
1109 | @menu | |
1110 | * Simple Constraints:: Basic use of constraints. | |
1111 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
1112 | * Class Preferences:: Constraints guide which hard register to put things in. | |
1113 | * Modifiers:: More precise control over effects of constraints. | |
1114 | * Machine Constraints:: Existing constraints for some particular machines. | |
9840b2fa | 1115 | * Disable Insn Alternatives:: Disable insn alternatives using attributes. |
f38840db ZW |
1116 | * Define Constraints:: How to define machine-specific constraints. |
1117 | * C Constraint Interface:: How to test constraints from C code. | |
03dda8e3 RK |
1118 | @end menu |
1119 | @end ifset | |
1120 | ||
1121 | @ifclear INTERNALS | |
1122 | @menu | |
1123 | * Simple Constraints:: Basic use of constraints. | |
1124 | * Multi-Alternative:: When an insn has two alternative constraint-patterns. | |
1125 | * Modifiers:: More precise control over effects of constraints. | |
1126 | * Machine Constraints:: Special constraints for some particular machines. | |
1127 | @end menu | |
1128 | @end ifclear | |
1129 | ||
1130 | @node Simple Constraints | |
1131 | @subsection Simple Constraints | |
1132 | @cindex simple constraints | |
1133 | ||
1134 | The simplest kind of constraint is a string full of letters, each of | |
1135 | which describes one kind of operand that is permitted. Here are | |
1136 | the letters that are allowed: | |
1137 | ||
1138 | @table @asis | |
88a56c2e HPN |
1139 | @item whitespace |
1140 | Whitespace characters are ignored and can be inserted at any position | |
1141 | except the first. This enables each alternative for different operands to | |
1142 | be visually aligned in the machine description even if they have different | |
1143 | number of constraints and modifiers. | |
1144 | ||
03dda8e3 RK |
1145 | @cindex @samp{m} in constraint |
1146 | @cindex memory references in constraints | |
1147 | @item @samp{m} | |
1148 | A memory operand is allowed, with any kind of address that the machine | |
1149 | supports in general. | |
a4edaf83 AK |
1150 | Note that the letter used for the general memory constraint can be |
1151 | re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro. | |
03dda8e3 RK |
1152 | |
1153 | @cindex offsettable address | |
1154 | @cindex @samp{o} in constraint | |
1155 | @item @samp{o} | |
1156 | A memory operand is allowed, but only if the address is | |
1157 | @dfn{offsettable}. This means that adding a small integer (actually, | |
1158 | the width in bytes of the operand, as determined by its machine mode) | |
1159 | may be added to the address and the result is also a valid memory | |
1160 | address. | |
1161 | ||
1162 | @cindex autoincrement/decrement addressing | |
1163 | For example, an address which is constant is offsettable; so is an | |
1164 | address that is the sum of a register and a constant (as long as a | |
1165 | slightly larger constant is also within the range of address-offsets | |
1166 | supported by the machine); but an autoincrement or autodecrement | |
1167 | address is not offsettable. More complicated indirect/indexed | |
1168 | addresses may or may not be offsettable depending on the other | |
1169 | addressing modes that the machine supports. | |
1170 | ||
1171 | Note that in an output operand which can be matched by another | |
1172 | operand, the constraint letter @samp{o} is valid only when accompanied | |
1173 | by both @samp{<} (if the target machine has predecrement addressing) | |
1174 | and @samp{>} (if the target machine has preincrement addressing). | |
1175 | ||
1176 | @cindex @samp{V} in constraint | |
1177 | @item @samp{V} | |
1178 | A memory operand that is not offsettable. In other words, anything that | |
1179 | would fit the @samp{m} constraint but not the @samp{o} constraint. | |
1180 | ||
1181 | @cindex @samp{<} in constraint | |
1182 | @item @samp{<} | |
1183 | A memory operand with autodecrement addressing (either predecrement or | |
54f044eb JJ |
1184 | postdecrement) is allowed. In inline @code{asm} this constraint is only |
1185 | allowed if the operand is used exactly once in an instruction that can | |
df18c24a | 1186 | handle the side effects. Not using an operand with @samp{<} in constraint |
54f044eb | 1187 | string in the inline @code{asm} pattern at all or using it in multiple |
df18c24a | 1188 | instructions isn't valid, because the side effects wouldn't be performed |
54f044eb JJ |
1189 | or would be performed more than once. Furthermore, on some targets |
1190 | the operand with @samp{<} in constraint string must be accompanied by | |
1191 | special instruction suffixes like @code{%U0} instruction suffix on PowerPC | |
1192 | or @code{%P0} on IA-64. | |
03dda8e3 RK |
1193 | |
1194 | @cindex @samp{>} in constraint | |
1195 | @item @samp{>} | |
1196 | A memory operand with autoincrement addressing (either preincrement or | |
54f044eb JJ |
1197 | postincrement) is allowed. In inline @code{asm} the same restrictions |
1198 | as for @samp{<} apply. | |
03dda8e3 RK |
1199 | |
1200 | @cindex @samp{r} in constraint | |
1201 | @cindex registers in constraints | |
1202 | @item @samp{r} | |
1203 | A register operand is allowed provided that it is in a general | |
1204 | register. | |
1205 | ||
03dda8e3 RK |
1206 | @cindex constants in constraints |
1207 | @cindex @samp{i} in constraint | |
1208 | @item @samp{i} | |
1209 | An immediate integer operand (one with constant value) is allowed. | |
1210 | This includes symbolic constants whose values will be known only at | |
8ac658b6 | 1211 | assembly time or later. |
03dda8e3 RK |
1212 | |
1213 | @cindex @samp{n} in constraint | |
1214 | @item @samp{n} | |
1215 | An immediate integer operand with a known numeric value is allowed. | |
1216 | Many systems cannot support assembly-time constants for operands less | |
1217 | than a word wide. Constraints for these operands should use @samp{n} | |
1218 | rather than @samp{i}. | |
1219 | ||
1220 | @cindex @samp{I} in constraint | |
1221 | @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P} | |
1222 | Other letters in the range @samp{I} through @samp{P} may be defined in | |
1223 | a machine-dependent fashion to permit immediate integer operands with | |
1224 | explicit integer values in specified ranges. For example, on the | |
1225 | 68000, @samp{I} is defined to stand for the range of values 1 to 8. | |
1226 | This is the range permitted as a shift count in the shift | |
1227 | instructions. | |
1228 | ||
1229 | @cindex @samp{E} in constraint | |
1230 | @item @samp{E} | |
1231 | An immediate floating operand (expression code @code{const_double}) is | |
1232 | allowed, but only if the target floating point format is the same as | |
1233 | that of the host machine (on which the compiler is running). | |
1234 | ||
1235 | @cindex @samp{F} in constraint | |
1236 | @item @samp{F} | |
bf7cd754 R |
1237 | An immediate floating operand (expression code @code{const_double} or |
1238 | @code{const_vector}) is allowed. | |
03dda8e3 RK |
1239 | |
1240 | @cindex @samp{G} in constraint | |
1241 | @cindex @samp{H} in constraint | |
1242 | @item @samp{G}, @samp{H} | |
1243 | @samp{G} and @samp{H} may be defined in a machine-dependent fashion to | |
1244 | permit immediate floating operands in particular ranges of values. | |
1245 | ||
1246 | @cindex @samp{s} in constraint | |
1247 | @item @samp{s} | |
1248 | An immediate integer operand whose value is not an explicit integer is | |
1249 | allowed. | |
1250 | ||
1251 | This might appear strange; if an insn allows a constant operand with a | |
1252 | value not known at compile time, it certainly must allow any known | |
1253 | value. So why use @samp{s} instead of @samp{i}? Sometimes it allows | |
1254 | better code to be generated. | |
1255 | ||
1256 | For example, on the 68000 in a fullword instruction it is possible to | |
630d3d5a | 1257 | use an immediate operand; but if the immediate value is between @minus{}128 |
03dda8e3 RK |
1258 | and 127, better code results from loading the value into a register and |
1259 | using the register. This is because the load into the register can be | |
1260 | done with a @samp{moveq} instruction. We arrange for this to happen | |
1261 | by defining the letter @samp{K} to mean ``any integer outside the | |
630d3d5a | 1262 | range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand |
03dda8e3 RK |
1263 | constraints. |
1264 | ||
1265 | @cindex @samp{g} in constraint | |
1266 | @item @samp{g} | |
1267 | Any register, memory or immediate integer operand is allowed, except for | |
1268 | registers that are not general registers. | |
1269 | ||
1270 | @cindex @samp{X} in constraint | |
1271 | @item @samp{X} | |
1272 | @ifset INTERNALS | |
1273 | Any operand whatsoever is allowed, even if it does not satisfy | |
1274 | @code{general_operand}. This is normally used in the constraint of | |
1275 | a @code{match_scratch} when certain alternatives will not actually | |
1276 | require a scratch register. | |
1277 | @end ifset | |
1278 | @ifclear INTERNALS | |
1279 | Any operand whatsoever is allowed. | |
1280 | @end ifclear | |
1281 | ||
1282 | @cindex @samp{0} in constraint | |
1283 | @cindex digits in constraint | |
1284 | @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9} | |
1285 | An operand that matches the specified operand number is allowed. If a | |
1286 | digit is used together with letters within the same alternative, the | |
1287 | digit should come last. | |
1288 | ||
84b72302 | 1289 | This number is allowed to be more than a single digit. If multiple |
c0478a66 | 1290 | digits are encountered consecutively, they are interpreted as a single |
84b72302 RH |
1291 | decimal integer. There is scant chance for ambiguity, since to-date |
1292 | it has never been desirable that @samp{10} be interpreted as matching | |
1293 | either operand 1 @emph{or} operand 0. Should this be desired, one | |
1294 | can use multiple alternatives instead. | |
1295 | ||
03dda8e3 RK |
1296 | @cindex matching constraint |
1297 | @cindex constraint, matching | |
1298 | This is called a @dfn{matching constraint} and what it really means is | |
1299 | that the assembler has only a single operand that fills two roles | |
1300 | @ifset INTERNALS | |
1301 | considered separate in the RTL insn. For example, an add insn has two | |
1302 | input operands and one output operand in the RTL, but on most CISC | |
1303 | @end ifset | |
1304 | @ifclear INTERNALS | |
1305 | which @code{asm} distinguishes. For example, an add instruction uses | |
1306 | two input operands and an output operand, but on most CISC | |
1307 | @end ifclear | |
1308 | machines an add instruction really has only two operands, one of them an | |
1309 | input-output operand: | |
1310 | ||
1311 | @smallexample | |
1312 | addl #35,r12 | |
1313 | @end smallexample | |
1314 | ||
1315 | Matching constraints are used in these circumstances. | |
1316 | More precisely, the two operands that match must include one input-only | |
1317 | operand and one output-only operand. Moreover, the digit must be a | |
1318 | smaller number than the number of the operand that uses it in the | |
1319 | constraint. | |
1320 | ||
1321 | @ifset INTERNALS | |
1322 | For operands to match in a particular case usually means that they | |
1323 | are identical-looking RTL expressions. But in a few special cases | |
1324 | specific kinds of dissimilarity are allowed. For example, @code{*x} | |
1325 | as an input operand will match @code{*x++} as an output operand. | |
1326 | For proper results in such cases, the output template should always | |
1327 | use the output-operand's number when printing the operand. | |
1328 | @end ifset | |
1329 | ||
1330 | @cindex load address instruction | |
1331 | @cindex push address instruction | |
1332 | @cindex address constraints | |
1333 | @cindex @samp{p} in constraint | |
1334 | @item @samp{p} | |
1335 | An operand that is a valid memory address is allowed. This is | |
1336 | for ``load address'' and ``push address'' instructions. | |
1337 | ||
1338 | @findex address_operand | |
1339 | @samp{p} in the constraint must be accompanied by @code{address_operand} | |
1340 | as the predicate in the @code{match_operand}. This predicate interprets | |
1341 | the mode specified in the @code{match_operand} as the mode of the memory | |
1342 | reference for which the address would be valid. | |
1343 | ||
c2cba7a9 | 1344 | @cindex other register constraints |
03dda8e3 | 1345 | @cindex extensible constraints |
630d3d5a | 1346 | @item @var{other-letters} |
c2cba7a9 RH |
1347 | Other letters can be defined in machine-dependent fashion to stand for |
1348 | particular classes of registers or other arbitrary operand types. | |
1349 | @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand | |
1350 | for data, address and floating point registers. | |
03dda8e3 RK |
1351 | @end table |
1352 | ||
1353 | @ifset INTERNALS | |
1354 | In order to have valid assembler code, each operand must satisfy | |
1355 | its constraint. But a failure to do so does not prevent the pattern | |
1356 | from applying to an insn. Instead, it directs the compiler to modify | |
1357 | the code so that the constraint will be satisfied. Usually this is | |
1358 | done by copying an operand into a register. | |
1359 | ||
1360 | Contrast, therefore, the two instruction patterns that follow: | |
1361 | ||
1362 | @smallexample | |
1363 | (define_insn "" | |
1364 | [(set (match_operand:SI 0 "general_operand" "=r") | |
1365 | (plus:SI (match_dup 0) | |
1366 | (match_operand:SI 1 "general_operand" "r")))] | |
1367 | "" | |
1368 | "@dots{}") | |
1369 | @end smallexample | |
1370 | ||
1371 | @noindent | |
1372 | which has two operands, one of which must appear in two places, and | |
1373 | ||
1374 | @smallexample | |
1375 | (define_insn "" | |
1376 | [(set (match_operand:SI 0 "general_operand" "=r") | |
1377 | (plus:SI (match_operand:SI 1 "general_operand" "0") | |
1378 | (match_operand:SI 2 "general_operand" "r")))] | |
1379 | "" | |
1380 | "@dots{}") | |
1381 | @end smallexample | |
1382 | ||
1383 | @noindent | |
1384 | which has three operands, two of which are required by a constraint to be | |
1385 | identical. If we are considering an insn of the form | |
1386 | ||
1387 | @smallexample | |
1388 | (insn @var{n} @var{prev} @var{next} | |
1389 | (set (reg:SI 3) | |
1390 | (plus:SI (reg:SI 6) (reg:SI 109))) | |
1391 | @dots{}) | |
1392 | @end smallexample | |
1393 | ||
1394 | @noindent | |
1395 | the first pattern would not apply at all, because this insn does not | |
1396 | contain two identical subexpressions in the right place. The pattern would | |
d78aa55c | 1397 | say, ``That does not look like an add instruction; try other patterns''. |
03dda8e3 | 1398 | The second pattern would say, ``Yes, that's an add instruction, but there |
d78aa55c | 1399 | is something wrong with it''. It would direct the reload pass of the |
03dda8e3 RK |
1400 | compiler to generate additional insns to make the constraint true. The |
1401 | results might look like this: | |
1402 | ||
1403 | @smallexample | |
1404 | (insn @var{n2} @var{prev} @var{n} | |
1405 | (set (reg:SI 3) (reg:SI 6)) | |
1406 | @dots{}) | |
1407 | ||
1408 | (insn @var{n} @var{n2} @var{next} | |
1409 | (set (reg:SI 3) | |
1410 | (plus:SI (reg:SI 3) (reg:SI 109))) | |
1411 | @dots{}) | |
1412 | @end smallexample | |
1413 | ||
1414 | It is up to you to make sure that each operand, in each pattern, has | |
1415 | constraints that can handle any RTL expression that could be present for | |
1416 | that operand. (When multiple alternatives are in use, each pattern must, | |
1417 | for each possible combination of operand expressions, have at least one | |
1418 | alternative which can handle that combination of operands.) The | |
1419 | constraints don't need to @emph{allow} any possible operand---when this is | |
1420 | the case, they do not constrain---but they must at least point the way to | |
1421 | reloading any possible operand so that it will fit. | |
1422 | ||
1423 | @itemize @bullet | |
1424 | @item | |
1425 | If the constraint accepts whatever operands the predicate permits, | |
1426 | there is no problem: reloading is never necessary for this operand. | |
1427 | ||
1428 | For example, an operand whose constraints permit everything except | |
1429 | registers is safe provided its predicate rejects registers. | |
1430 | ||
1431 | An operand whose predicate accepts only constant values is safe | |
1432 | provided its constraints include the letter @samp{i}. If any possible | |
1433 | constant value is accepted, then nothing less than @samp{i} will do; | |
1434 | if the predicate is more selective, then the constraints may also be | |
1435 | more selective. | |
1436 | ||
1437 | @item | |
1438 | Any operand expression can be reloaded by copying it into a register. | |
1439 | So if an operand's constraints allow some kind of register, it is | |
1440 | certain to be safe. It need not permit all classes of registers; the | |
1441 | compiler knows how to copy a register into another register of the | |
1442 | proper class in order to make an instruction valid. | |
1443 | ||
1444 | @cindex nonoffsettable memory reference | |
1445 | @cindex memory reference, nonoffsettable | |
1446 | @item | |
1447 | A nonoffsettable memory reference can be reloaded by copying the | |
1448 | address into a register. So if the constraint uses the letter | |
1449 | @samp{o}, all memory references are taken care of. | |
1450 | ||
1451 | @item | |
1452 | A constant operand can be reloaded by allocating space in memory to | |
1453 | hold it as preinitialized data. Then the memory reference can be used | |
1454 | in place of the constant. So if the constraint uses the letters | |
1455 | @samp{o} or @samp{m}, constant operands are not a problem. | |
1456 | ||
1457 | @item | |
1458 | If the constraint permits a constant and a pseudo register used in an insn | |
1459 | was not allocated to a hard register and is equivalent to a constant, | |
1460 | the register will be replaced with the constant. If the predicate does | |
1461 | not permit a constant and the insn is re-recognized for some reason, the | |
1462 | compiler will crash. Thus the predicate must always recognize any | |
1463 | objects allowed by the constraint. | |
1464 | @end itemize | |
1465 | ||
1466 | If the operand's predicate can recognize registers, but the constraint does | |
1467 | not permit them, it can make the compiler crash. When this operand happens | |
1468 | to be a register, the reload pass will be stymied, because it does not know | |
1469 | how to copy a register temporarily into memory. | |
1470 | ||
1471 | If the predicate accepts a unary operator, the constraint applies to the | |
1472 | operand. For example, the MIPS processor at ISA level 3 supports an | |
1473 | instruction which adds two registers in @code{SImode} to produce a | |
1474 | @code{DImode} result, but only if the registers are correctly sign | |
1475 | extended. This predicate for the input operands accepts a | |
1476 | @code{sign_extend} of an @code{SImode} register. Write the constraint | |
1477 | to indicate the type of register that is required for the operand of the | |
1478 | @code{sign_extend}. | |
1479 | @end ifset | |
1480 | ||
1481 | @node Multi-Alternative | |
1482 | @subsection Multiple Alternative Constraints | |
1483 | @cindex multiple alternative constraints | |
1484 | ||
1485 | Sometimes a single instruction has multiple alternative sets of possible | |
1486 | operands. For example, on the 68000, a logical-or instruction can combine | |
1487 | register or an immediate value into memory, or it can combine any kind of | |
1488 | operand into a register; but it cannot combine one memory location into | |
1489 | another. | |
1490 | ||
1491 | These constraints are represented as multiple alternatives. An alternative | |
1492 | can be described by a series of letters for each operand. The overall | |
1493 | constraint for an operand is made from the letters for this operand | |
1494 | from the first alternative, a comma, the letters for this operand from | |
1495 | the second alternative, a comma, and so on until the last alternative. | |
a6fa947e DW |
1496 | All operands for a single instruction must have the same number of |
1497 | alternatives. | |
03dda8e3 RK |
1498 | @ifset INTERNALS |
1499 | Here is how it is done for fullword logical-or on the 68000: | |
1500 | ||
1501 | @smallexample | |
1502 | (define_insn "iorsi3" | |
1503 | [(set (match_operand:SI 0 "general_operand" "=m,d") | |
1504 | (ior:SI (match_operand:SI 1 "general_operand" "%0,0") | |
1505 | (match_operand:SI 2 "general_operand" "dKs,dmKs")))] | |
1506 | @dots{}) | |
1507 | @end smallexample | |
1508 | ||
1509 | The first alternative has @samp{m} (memory) for operand 0, @samp{0} for | |
1510 | operand 1 (meaning it must match operand 0), and @samp{dKs} for operand | |
1511 | 2. The second alternative has @samp{d} (data register) for operand 0, | |
1512 | @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and | |
1513 | @samp{%} in the constraints apply to all the alternatives; their | |
1514 | meaning is explained in the next section (@pxref{Class Preferences}). | |
03dda8e3 | 1515 | |
03dda8e3 RK |
1516 | If all the operands fit any one alternative, the instruction is valid. |
1517 | Otherwise, for each alternative, the compiler counts how many instructions | |
1518 | must be added to copy the operands so that that alternative applies. | |
1519 | The alternative requiring the least copying is chosen. If two alternatives | |
1520 | need the same amount of copying, the one that comes first is chosen. | |
1521 | These choices can be altered with the @samp{?} and @samp{!} characters: | |
1522 | ||
1523 | @table @code | |
1524 | @cindex @samp{?} in constraint | |
1525 | @cindex question mark | |
1526 | @item ? | |
1527 | Disparage slightly the alternative that the @samp{?} appears in, | |
1528 | as a choice when no alternative applies exactly. The compiler regards | |
1529 | this alternative as one unit more costly for each @samp{?} that appears | |
1530 | in it. | |
1531 | ||
1532 | @cindex @samp{!} in constraint | |
1533 | @cindex exclamation point | |
1534 | @item ! | |
1535 | Disparage severely the alternative that the @samp{!} appears in. | |
1536 | This alternative can still be used if it fits without reloading, | |
1537 | but if reloading is needed, some other alternative will be used. | |
d1457701 VM |
1538 | |
1539 | @cindex @samp{^} in constraint | |
1540 | @cindex caret | |
1541 | @item ^ | |
1542 | This constraint is analogous to @samp{?} but it disparages slightly | |
0ab9eed6 | 1543 | the alternative only if the operand with the @samp{^} needs a reload. |
d1457701 VM |
1544 | |
1545 | @cindex @samp{$} in constraint | |
1546 | @cindex dollar sign | |
1547 | @item $ | |
1548 | This constraint is analogous to @samp{!} but it disparages severely | |
1549 | the alternative only if the operand with the @samp{$} needs a reload. | |
03dda8e3 RK |
1550 | @end table |
1551 | ||
03dda8e3 RK |
1552 | When an insn pattern has multiple alternatives in its constraints, often |
1553 | the appearance of the assembler code is determined mostly by which | |
1554 | alternative was matched. When this is so, the C code for writing the | |
1555 | assembler code can use the variable @code{which_alternative}, which is | |
1556 | the ordinal number of the alternative that was actually satisfied (0 for | |
1557 | the first, 1 for the second alternative, etc.). @xref{Output Statement}. | |
1558 | @end ifset | |
a6fa947e DW |
1559 | @ifclear INTERNALS |
1560 | ||
1561 | So the first alternative for the 68000's logical-or could be written as | |
1562 | @code{"+m" (output) : "ir" (input)}. The second could be @code{"+r" | |
1563 | (output): "irm" (input)}. However, the fact that two memory locations | |
1564 | cannot be used in a single instruction prevents simply using @code{"+rm" | |
1565 | (output) : "irm" (input)}. Using multi-alternatives, this might be | |
1566 | written as @code{"+m,r" (output) : "ir,irm" (input)}. This describes | |
1567 | all the available alternatives to the compiler, allowing it to choose | |
1568 | the most efficient one for the current conditions. | |
1569 | ||
1570 | There is no way within the template to determine which alternative was | |
1571 | chosen. However you may be able to wrap your @code{asm} statements with | |
1572 | builtins such as @code{__builtin_constant_p} to achieve the desired results. | |
1573 | @end ifclear | |
03dda8e3 RK |
1574 | |
1575 | @ifset INTERNALS | |
1576 | @node Class Preferences | |
1577 | @subsection Register Class Preferences | |
1578 | @cindex class preference constraints | |
1579 | @cindex register class preference constraints | |
1580 | ||
1581 | @cindex voting between constraint alternatives | |
1582 | The operand constraints have another function: they enable the compiler | |
1583 | to decide which kind of hardware register a pseudo register is best | |
1584 | allocated to. The compiler examines the constraints that apply to the | |
1585 | insns that use the pseudo register, looking for the machine-dependent | |
1586 | letters such as @samp{d} and @samp{a} that specify classes of registers. | |
1587 | The pseudo register is put in whichever class gets the most ``votes''. | |
1588 | The constraint letters @samp{g} and @samp{r} also vote: they vote in | |
1589 | favor of a general register. The machine description says which registers | |
1590 | are considered general. | |
1591 | ||
1592 | Of course, on some machines all registers are equivalent, and no register | |
1593 | classes are defined. Then none of this complexity is relevant. | |
1594 | @end ifset | |
1595 | ||
1596 | @node Modifiers | |
1597 | @subsection Constraint Modifier Characters | |
1598 | @cindex modifiers in constraints | |
1599 | @cindex constraint modifier characters | |
1600 | ||
1601 | @c prevent bad page break with this line | |
1602 | Here are constraint modifier characters. | |
1603 | ||
1604 | @table @samp | |
1605 | @cindex @samp{=} in constraint | |
1606 | @item = | |
5fd4bc96 JG |
1607 | Means that this operand is written to by this instruction: |
1608 | the previous value is discarded and replaced by new data. | |
03dda8e3 RK |
1609 | |
1610 | @cindex @samp{+} in constraint | |
1611 | @item + | |
1612 | Means that this operand is both read and written by the instruction. | |
1613 | ||
1614 | When the compiler fixes up the operands to satisfy the constraints, | |
5fd4bc96 JG |
1615 | it needs to know which operands are read by the instruction and |
1616 | which are written by it. @samp{=} identifies an operand which is only | |
1617 | written; @samp{+} identifies an operand that is both read and written; all | |
1618 | other operands are assumed to only be read. | |
03dda8e3 | 1619 | |
c5c76735 JL |
1620 | If you specify @samp{=} or @samp{+} in a constraint, you put it in the |
1621 | first character of the constraint string. | |
1622 | ||
03dda8e3 RK |
1623 | @cindex @samp{&} in constraint |
1624 | @cindex earlyclobber operand | |
1625 | @item & | |
1626 | Means (in a particular alternative) that this operand is an | |
5fd4bc96 | 1627 | @dfn{earlyclobber} operand, which is written before the instruction is |
03dda8e3 | 1628 | finished using the input operands. Therefore, this operand may not lie |
5fd4bc96 | 1629 | in a register that is read by the instruction or as part of any memory |
03dda8e3 RK |
1630 | address. |
1631 | ||
1632 | @samp{&} applies only to the alternative in which it is written. In | |
1633 | constraints with multiple alternatives, sometimes one alternative | |
1634 | requires @samp{&} while others do not. See, for example, the | |
1635 | @samp{movdf} insn of the 68000. | |
1636 | ||
61fecd4d | 1637 | An operand which is read by the instruction can be tied to an earlyclobber |
5fd4bc96 JG |
1638 | operand if its only use as an input occurs before the early result is |
1639 | written. Adding alternatives of this form often allows GCC to produce | |
1640 | better code when only some of the read operands can be affected by the | |
1641 | earlyclobber. See, for example, the @samp{mulsi3} insn of the ARM@. | |
03dda8e3 | 1642 | |
5fd4bc96 JG |
1643 | Furthermore, if the @dfn{earlyclobber} operand is also a read/write |
1644 | operand, then that operand is written only after it's used. | |
34386e79 | 1645 | |
5fd4bc96 JG |
1646 | @samp{&} does not obviate the need to write @samp{=} or @samp{+}. As |
1647 | @dfn{earlyclobber} operands are always written, a read-only | |
1648 | @dfn{earlyclobber} operand is ill-formed and will be rejected by the | |
1649 | compiler. | |
03dda8e3 RK |
1650 | |
1651 | @cindex @samp{%} in constraint | |
1652 | @item % | |
1653 | Declares the instruction to be commutative for this operand and the | |
1654 | following operand. This means that the compiler may interchange the | |
1655 | two operands if that is the cheapest way to make all operands fit the | |
73f793e3 | 1656 | constraints. @samp{%} applies to all alternatives and must appear as |
5fd4bc96 | 1657 | the first character in the constraint. Only read-only operands can use |
73f793e3 RS |
1658 | @samp{%}. |
1659 | ||
03dda8e3 RK |
1660 | @ifset INTERNALS |
1661 | This is often used in patterns for addition instructions | |
1662 | that really have only two operands: the result must go in one of the | |
1663 | arguments. Here for example, is how the 68000 halfword-add | |
1664 | instruction is defined: | |
1665 | ||
1666 | @smallexample | |
1667 | (define_insn "addhi3" | |
1668 | [(set (match_operand:HI 0 "general_operand" "=m,r") | |
1669 | (plus:HI (match_operand:HI 1 "general_operand" "%0,0") | |
1670 | (match_operand:HI 2 "general_operand" "di,g")))] | |
1671 | @dots{}) | |
1672 | @end smallexample | |
1673 | @end ifset | |
daf2f129 | 1674 | GCC can only handle one commutative pair in an asm; if you use more, |
595163db EB |
1675 | the compiler may fail. Note that you need not use the modifier if |
1676 | the two alternatives are strictly identical; this would only waste | |
4f237f2e DW |
1677 | time in the reload pass. |
1678 | @ifset INTERNALS | |
1679 | The modifier is not operational after | |
be3914df HPN |
1680 | register allocation, so the result of @code{define_peephole2} |
1681 | and @code{define_split}s performed after reload cannot rely on | |
1682 | @samp{%} to make the intended insn match. | |
03dda8e3 RK |
1683 | |
1684 | @cindex @samp{#} in constraint | |
1685 | @item # | |
1686 | Says that all following characters, up to the next comma, are to be | |
1687 | ignored as a constraint. They are significant only for choosing | |
1688 | register preferences. | |
1689 | ||
03dda8e3 RK |
1690 | @cindex @samp{*} in constraint |
1691 | @item * | |
1692 | Says that the following character should be ignored when choosing | |
1693 | register preferences. @samp{*} has no effect on the meaning of the | |
55a2c322 VM |
1694 | constraint as a constraint, and no effect on reloading. For LRA |
1695 | @samp{*} additionally disparages slightly the alternative if the | |
1696 | following character matches the operand. | |
03dda8e3 RK |
1697 | |
1698 | Here is an example: the 68000 has an instruction to sign-extend a | |
1699 | halfword in a data register, and can also sign-extend a value by | |
1700 | copying it into an address register. While either kind of register is | |
1701 | acceptable, the constraints on an address-register destination are | |
1702 | less strict, so it is best if register allocation makes an address | |
1703 | register its goal. Therefore, @samp{*} is used so that the @samp{d} | |
1704 | constraint letter (for data register) is ignored when computing | |
1705 | register preferences. | |
1706 | ||
1707 | @smallexample | |
1708 | (define_insn "extendhisi2" | |
1709 | [(set (match_operand:SI 0 "general_operand" "=*d,a") | |
1710 | (sign_extend:SI | |
1711 | (match_operand:HI 1 "general_operand" "0,g")))] | |
1712 | @dots{}) | |
1713 | @end smallexample | |
1714 | @end ifset | |
1715 | @end table | |
1716 | ||
1717 | @node Machine Constraints | |
1718 | @subsection Constraints for Particular Machines | |
1719 | @cindex machine specific constraints | |
1720 | @cindex constraints, machine specific | |
1721 | ||
1722 | Whenever possible, you should use the general-purpose constraint letters | |
1723 | in @code{asm} arguments, since they will convey meaning more readily to | |
1724 | people reading your code. Failing that, use the constraint letters | |
1725 | that usually have very similar meanings across architectures. The most | |
1726 | commonly used constraints are @samp{m} and @samp{r} (for memory and | |
1727 | general-purpose registers respectively; @pxref{Simple Constraints}), and | |
1728 | @samp{I}, usually the letter indicating the most common | |
1729 | immediate-constant format. | |
1730 | ||
f38840db ZW |
1731 | Each architecture defines additional constraints. These constraints |
1732 | are used by the compiler itself for instruction generation, as well as | |
1733 | for @code{asm} statements; therefore, some of the constraints are not | |
1734 | particularly useful for @code{asm}. Here is a summary of some of the | |
1735 | machine-dependent constraints available on some particular machines; | |
1736 | it includes both constraints that are useful for @code{asm} and | |
1737 | constraints that aren't. The compiler source file mentioned in the | |
1738 | table heading for each architecture is the definitive reference for | |
1739 | the meanings of that architecture's constraints. | |
6ccde948 | 1740 | |
b4fbcb1b | 1741 | @c Please keep this table alphabetized by target! |
03dda8e3 | 1742 | @table @emph |
5c0da018 IB |
1743 | @item AArch64 family---@file{config/aarch64/constraints.md} |
1744 | @table @code | |
1745 | @item k | |
1746 | The stack pointer register (@code{SP}) | |
1747 | ||
1748 | @item w | |
43cacb12 RS |
1749 | Floating point register, Advanced SIMD vector register or SVE vector register |
1750 | ||
163b1f6a RS |
1751 | @item x |
1752 | Like @code{w}, but restricted to registers 0 to 15 inclusive. | |
1753 | ||
1754 | @item y | |
1755 | Like @code{w}, but restricted to registers 0 to 7 inclusive. | |
1756 | ||
43cacb12 RS |
1757 | @item Upl |
1758 | One of the low eight SVE predicate registers (@code{P0} to @code{P7}) | |
1759 | ||
1760 | @item Upa | |
1761 | Any of the SVE predicate registers (@code{P0} to @code{P15}) | |
5c0da018 IB |
1762 | |
1763 | @item I | |
1764 | Integer constant that is valid as an immediate operand in an @code{ADD} | |
1765 | instruction | |
1766 | ||
1767 | @item J | |
1768 | Integer constant that is valid as an immediate operand in a @code{SUB} | |
1769 | instruction (once negated) | |
1770 | ||
1771 | @item K | |
1772 | Integer constant that can be used with a 32-bit logical instruction | |
1773 | ||
1774 | @item L | |
1775 | Integer constant that can be used with a 64-bit logical instruction | |
1776 | ||
1777 | @item M | |
1778 | Integer constant that is valid as an immediate operand in a 32-bit @code{MOV} | |
1779 | pseudo instruction. The @code{MOV} may be assembled to one of several different | |
1780 | machine instructions depending on the value | |
1781 | ||
1782 | @item N | |
1783 | Integer constant that is valid as an immediate operand in a 64-bit @code{MOV} | |
1784 | pseudo instruction | |
1785 | ||
1786 | @item S | |
1787 | An absolute symbolic address or a label reference | |
1788 | ||
1789 | @item Y | |
1790 | Floating point constant zero | |
1791 | ||
1792 | @item Z | |
1793 | Integer constant zero | |
1794 | ||
5c0da018 IB |
1795 | @item Ush |
1796 | The high part (bits 12 and upwards) of the pc-relative address of a symbol | |
1797 | within 4GB of the instruction | |
1798 | ||
1799 | @item Q | |
1800 | A memory address which uses a single base register with no offset | |
1801 | ||
1802 | @item Ump | |
1803 | A memory address suitable for a load/store pair instruction in SI, DI, SF and | |
1804 | DF modes | |
1805 | ||
5c0da018 IB |
1806 | @end table |
1807 | ||
1808 | ||
1b7ee8b4 AS |
1809 | @item AMD GCN ---@file{config/gcn/constraints.md} |
1810 | @table @code | |
1811 | @item I | |
1812 | Immediate integer in the range @minus{}16 to 64 | |
1813 | ||
1814 | @item J | |
1815 | Immediate 16-bit signed integer | |
1816 | ||
1817 | @item Kf | |
1818 | Immediate constant @minus{}1 | |
1819 | ||
1820 | @item L | |
1821 | Immediate 15-bit unsigned integer | |
1822 | ||
1823 | @item A | |
1824 | Immediate constant that can be inlined in an instruction encoding: integer | |
1825 | @minus{}16..64, or float 0.0, +/@minus{}0.5, +/@minus{}1.0, +/@minus{}2.0, | |
1826 | +/@minus{}4.0, 1.0/(2.0*PI) | |
1827 | ||
1828 | @item B | |
1829 | Immediate 32-bit signed integer that can be attached to an instruction encoding | |
1830 | ||
1831 | @item C | |
1832 | Immediate 32-bit integer in range @minus{}16..4294967295 (i.e. 32-bit unsigned | |
1833 | integer or @samp{A} constraint) | |
1834 | ||
1835 | @item DA | |
1836 | Immediate 64-bit constant that can be split into two @samp{A} constants | |
1837 | ||
1838 | @item DB | |
1839 | Immediate 64-bit constant that can be split into two @samp{B} constants | |
1840 | ||
1841 | @item U | |
1842 | Any @code{unspec} | |
1843 | ||
1844 | @item Y | |
1845 | Any @code{symbol_ref} or @code{label_ref} | |
1846 | ||
1847 | @item v | |
1848 | VGPR register | |
1849 | ||
1850 | @item Sg | |
1851 | SGPR register | |
1852 | ||
1853 | @item SD | |
1854 | SGPR registers valid for instruction destinations, including VCC, M0 and EXEC | |
1855 | ||
1856 | @item SS | |
1857 | SGPR registers valid for instruction sources, including VCC, M0, EXEC and SCC | |
1858 | ||
1859 | @item Sm | |
1860 | SGPR registers valid as a source for scalar memory instructions (excludes M0 | |
1861 | and EXEC) | |
1862 | ||
1863 | @item Sv | |
1864 | SGPR registers valid as a source or destination for vector instructions | |
1865 | (excludes EXEC) | |
1866 | ||
1867 | @item ca | |
1868 | All condition registers: SCC, VCCZ, EXECZ | |
1869 | ||
1870 | @item cs | |
1871 | Scalar condition register: SCC | |
1872 | ||
1873 | @item cV | |
1874 | Vector condition register: VCC, VCC_LO, VCC_HI | |
1875 | ||
1876 | @item e | |
1877 | EXEC register (EXEC_LO and EXEC_HI) | |
1878 | ||
1879 | @item RB | |
1880 | Memory operand with address space suitable for @code{buffer_*} instructions | |
1881 | ||
1882 | @item RF | |
1883 | Memory operand with address space suitable for @code{flat_*} instructions | |
1884 | ||
1885 | @item RS | |
1886 | Memory operand with address space suitable for @code{s_*} instructions | |
1887 | ||
1888 | @item RL | |
1889 | Memory operand with address space suitable for @code{ds_*} LDS instructions | |
1890 | ||
1891 | @item RG | |
1892 | Memory operand with address space suitable for @code{ds_*} GDS instructions | |
1893 | ||
1894 | @item RD | |
1895 | Memory operand with address space suitable for any @code{ds_*} instructions | |
1896 | ||
1897 | @item RM | |
1898 | Memory operand with address space suitable for @code{global_*} instructions | |
1899 | ||
1900 | @end table | |
1901 | ||
1902 | ||
5d5f6720 JR |
1903 | @item ARC ---@file{config/arc/constraints.md} |
1904 | @table @code | |
1905 | @item q | |
1906 | Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3}, | |
1907 | @code{r12}-@code{r15}. This constraint can only match when the @option{-mq} | |
1908 | option is in effect. | |
1909 | ||
1910 | @item e | |
1911 | Registers usable as base-regs of memory addresses in ARCompact 16-bit memory | |
1912 | instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}. | |
1913 | This constraint can only match when the @option{-mq} | |
1914 | option is in effect. | |
1915 | @item D | |
1916 | ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}. | |
1917 | ||
1918 | @item I | |
1919 | A signed 12-bit integer constant. | |
1920 | ||
1921 | @item Cal | |
1922 | constant for arithmetic/logical operations. This might be any constant | |
1923 | that can be put into a long immediate by the assmbler or linker without | |
1924 | involving a PIC relocation. | |
1925 | ||
1926 | @item K | |
1927 | A 3-bit unsigned integer constant. | |
1928 | ||
1929 | @item L | |
1930 | A 6-bit unsigned integer constant. | |
1931 | ||
1932 | @item CnL | |
1933 | One's complement of a 6-bit unsigned integer constant. | |
1934 | ||
1935 | @item CmL | |
1936 | Two's complement of a 6-bit unsigned integer constant. | |
1937 | ||
1938 | @item M | |
1939 | A 5-bit unsigned integer constant. | |
1940 | ||
1941 | @item O | |
1942 | A 7-bit unsigned integer constant. | |
1943 | ||
1944 | @item P | |
1945 | A 8-bit unsigned integer constant. | |
1946 | ||
1947 | @item H | |
1948 | Any const_double value. | |
1949 | @end table | |
1950 | ||
dae840fc | 1951 | @item ARM family---@file{config/arm/constraints.md} |
03dda8e3 | 1952 | @table @code |
b24671f7 RR |
1953 | |
1954 | @item h | |
1955 | In Thumb state, the core registers @code{r8}-@code{r15}. | |
1956 | ||
1957 | @item k | |
1958 | The stack pointer register. | |
1959 | ||
1960 | @item l | |
1961 | In Thumb State the core registers @code{r0}-@code{r7}. In ARM state this | |
1962 | is an alias for the @code{r} constraint. | |
1963 | ||
1964 | @item t | |
1965 | VFP floating-point registers @code{s0}-@code{s31}. Used for 32 bit values. | |
1966 | ||
9b66ebb1 | 1967 | @item w |
b24671f7 RR |
1968 | VFP floating-point registers @code{d0}-@code{d31} and the appropriate |
1969 | subset @code{d0}-@code{d15} based on command line options. | |
1970 | Used for 64 bit values only. Not valid for Thumb1. | |
1971 | ||
1972 | @item y | |
1973 | The iWMMX co-processor registers. | |
1974 | ||
1975 | @item z | |
1976 | The iWMMX GR registers. | |
9b66ebb1 | 1977 | |
03dda8e3 | 1978 | @item G |
dae840fc | 1979 | The floating-point constant 0.0 |
03dda8e3 RK |
1980 | |
1981 | @item I | |
1982 | Integer that is valid as an immediate operand in a data processing | |
1983 | instruction. That is, an integer in the range 0 to 255 rotated by a | |
1984 | multiple of 2 | |
1985 | ||
1986 | @item J | |
630d3d5a | 1987 | Integer in the range @minus{}4095 to 4095 |
03dda8e3 RK |
1988 | |
1989 | @item K | |
1990 | Integer that satisfies constraint @samp{I} when inverted (ones complement) | |
1991 | ||
1992 | @item L | |
1993 | Integer that satisfies constraint @samp{I} when negated (twos complement) | |
1994 | ||
1995 | @item M | |
1996 | Integer in the range 0 to 32 | |
1997 | ||
1998 | @item Q | |
1999 | A memory reference where the exact address is in a single register | |
2000 | (`@samp{m}' is preferable for @code{asm} statements) | |
2001 | ||
2002 | @item R | |
2003 | An item in the constant pool | |
2004 | ||
2005 | @item S | |
2006 | A symbol in the text segment of the current file | |
03dda8e3 | 2007 | |
1e1ab407 | 2008 | @item Uv |
9b66ebb1 PB |
2009 | A memory reference suitable for VFP load/store insns (reg+constant offset) |
2010 | ||
fdd695fd PB |
2011 | @item Uy |
2012 | A memory reference suitable for iWMMXt load/store instructions. | |
2013 | ||
1e1ab407 | 2014 | @item Uq |
0bdcd332 | 2015 | A memory reference suitable for the ARMv4 ldrsb instruction. |
db875b15 | 2016 | @end table |
1e1ab407 | 2017 | |
fc262682 | 2018 | @item AVR family---@file{config/avr/constraints.md} |
052a4b28 DC |
2019 | @table @code |
2020 | @item l | |
2021 | Registers from r0 to r15 | |
2022 | ||
2023 | @item a | |
2024 | Registers from r16 to r23 | |
2025 | ||
2026 | @item d | |
2027 | Registers from r16 to r31 | |
2028 | ||
2029 | @item w | |
3a69a7d5 | 2030 | Registers from r24 to r31. These registers can be used in @samp{adiw} command |
052a4b28 DC |
2031 | |
2032 | @item e | |
d7d9c429 | 2033 | Pointer register (r26--r31) |
052a4b28 DC |
2034 | |
2035 | @item b | |
d7d9c429 | 2036 | Base pointer register (r28--r31) |
052a4b28 | 2037 | |
3a69a7d5 MM |
2038 | @item q |
2039 | Stack pointer register (SPH:SPL) | |
2040 | ||
052a4b28 DC |
2041 | @item t |
2042 | Temporary register r0 | |
2043 | ||
2044 | @item x | |
2045 | Register pair X (r27:r26) | |
2046 | ||
2047 | @item y | |
2048 | Register pair Y (r29:r28) | |
2049 | ||
2050 | @item z | |
2051 | Register pair Z (r31:r30) | |
2052 | ||
2053 | @item I | |
630d3d5a | 2054 | Constant greater than @minus{}1, less than 64 |
052a4b28 DC |
2055 | |
2056 | @item J | |
630d3d5a | 2057 | Constant greater than @minus{}64, less than 1 |
052a4b28 DC |
2058 | |
2059 | @item K | |
2060 | Constant integer 2 | |
2061 | ||
2062 | @item L | |
2063 | Constant integer 0 | |
2064 | ||
2065 | @item M | |
2066 | Constant that fits in 8 bits | |
2067 | ||
2068 | @item N | |
630d3d5a | 2069 | Constant integer @minus{}1 |
052a4b28 DC |
2070 | |
2071 | @item O | |
3a69a7d5 | 2072 | Constant integer 8, 16, or 24 |
052a4b28 DC |
2073 | |
2074 | @item P | |
2075 | Constant integer 1 | |
2076 | ||
2077 | @item G | |
2078 | A floating point constant 0.0 | |
0e8eb4d8 | 2079 | |
0e8eb4d8 EW |
2080 | @item Q |
2081 | A memory address based on Y or Z pointer with displacement. | |
052a4b28 | 2082 | @end table |
53054e77 | 2083 | |
b4fbcb1b SL |
2084 | @item Blackfin family---@file{config/bfin/constraints.md} |
2085 | @table @code | |
2086 | @item a | |
2087 | P register | |
2088 | ||
2089 | @item d | |
2090 | D register | |
2091 | ||
2092 | @item z | |
2093 | A call clobbered P register. | |
2094 | ||
2095 | @item q@var{n} | |
2096 | A single register. If @var{n} is in the range 0 to 7, the corresponding D | |
2097 | register. If it is @code{A}, then the register P0. | |
2098 | ||
2099 | @item D | |
2100 | Even-numbered D register | |
2101 | ||
2102 | @item W | |
2103 | Odd-numbered D register | |
2104 | ||
2105 | @item e | |
2106 | Accumulator register. | |
2107 | ||
2108 | @item A | |
2109 | Even-numbered accumulator register. | |
2110 | ||
2111 | @item B | |
2112 | Odd-numbered accumulator register. | |
2113 | ||
2114 | @item b | |
2115 | I register | |
2116 | ||
2117 | @item v | |
2118 | B register | |
2119 | ||
2120 | @item f | |
2121 | M register | |
2122 | ||
2123 | @item c | |
630ba2fd | 2124 | Registers used for circular buffering, i.e.@: I, B, or L registers. |
b4fbcb1b SL |
2125 | |
2126 | @item C | |
2127 | The CC register. | |
2128 | ||
2129 | @item t | |
2130 | LT0 or LT1. | |
2131 | ||
2132 | @item k | |
2133 | LC0 or LC1. | |
2134 | ||
2135 | @item u | |
2136 | LB0 or LB1. | |
2137 | ||
2138 | @item x | |
2139 | Any D, P, B, M, I or L register. | |
2140 | ||
2141 | @item y | |
2142 | Additional registers typically used only in prologues and epilogues: RETS, | |
2143 | RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP. | |
2144 | ||
2145 | @item w | |
2146 | Any register except accumulators or CC. | |
2147 | ||
2148 | @item Ksh | |
2149 | Signed 16 bit integer (in the range @minus{}32768 to 32767) | |
2150 | ||
2151 | @item Kuh | |
2152 | Unsigned 16 bit integer (in the range 0 to 65535) | |
2153 | ||
2154 | @item Ks7 | |
2155 | Signed 7 bit integer (in the range @minus{}64 to 63) | |
2156 | ||
2157 | @item Ku7 | |
2158 | Unsigned 7 bit integer (in the range 0 to 127) | |
2159 | ||
2160 | @item Ku5 | |
2161 | Unsigned 5 bit integer (in the range 0 to 31) | |
2162 | ||
2163 | @item Ks4 | |
2164 | Signed 4 bit integer (in the range @minus{}8 to 7) | |
2165 | ||
2166 | @item Ks3 | |
2167 | Signed 3 bit integer (in the range @minus{}3 to 4) | |
2168 | ||
2169 | @item Ku3 | |
2170 | Unsigned 3 bit integer (in the range 0 to 7) | |
2171 | ||
2172 | @item P@var{n} | |
2173 | Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4. | |
2174 | ||
2175 | @item PA | |
2176 | An integer equal to one of the MACFLAG_XXX constants that is suitable for | |
2177 | use with either accumulator. | |
2178 | ||
2179 | @item PB | |
2180 | An integer equal to one of the MACFLAG_XXX constants that is suitable for | |
2181 | use only with accumulator A1. | |
2182 | ||
2183 | @item M1 | |
2184 | Constant 255. | |
2185 | ||
2186 | @item M2 | |
2187 | Constant 65535. | |
2188 | ||
2189 | @item J | |
2190 | An integer constant with exactly a single bit set. | |
2191 | ||
2192 | @item L | |
2193 | An integer constant with all bits set except exactly one. | |
2194 | ||
2195 | @item H | |
2196 | ||
2197 | @item Q | |
2198 | Any SYMBOL_REF. | |
2199 | @end table | |
2200 | ||
2201 | @item CR16 Architecture---@file{config/cr16/cr16.h} | |
2202 | @table @code | |
2203 | ||
2204 | @item b | |
2205 | Registers from r0 to r14 (registers without stack pointer) | |
2206 | ||
2207 | @item t | |
2208 | Register from r0 to r11 (all 16-bit registers) | |
2209 | ||
2210 | @item p | |
2211 | Register from r12 to r15 (all 32-bit registers) | |
2212 | ||
2213 | @item I | |
2214 | Signed constant that fits in 4 bits | |
2215 | ||
2216 | @item J | |
2217 | Signed constant that fits in 5 bits | |
2218 | ||
2219 | @item K | |
2220 | Signed constant that fits in 6 bits | |
2221 | ||
2222 | @item L | |
2223 | Unsigned constant that fits in 4 bits | |
2224 | ||
2225 | @item M | |
2226 | Signed constant that fits in 32 bits | |
2227 | ||
2228 | @item N | |
2229 | Check for 64 bits wide constants for add/sub instructions | |
2230 | ||
2231 | @item G | |
2232 | Floating point constant that is legal for store immediate | |
2233 | @end table | |
2234 | ||
fbceb769 SL |
2235 | @item C-SKY---@file{config/csky/constraints.md} |
2236 | @table @code | |
2237 | ||
2238 | @item a | |
2239 | The mini registers r0 - r7. | |
2240 | ||
2241 | @item b | |
2242 | The low registers r0 - r15. | |
2243 | ||
2244 | @item c | |
2245 | C register. | |
2246 | ||
2247 | @item y | |
2248 | HI and LO registers. | |
2249 | ||
2250 | @item l | |
2251 | LO register. | |
2252 | ||
2253 | @item h | |
2254 | HI register. | |
2255 | ||
2256 | @item v | |
2257 | Vector registers. | |
2258 | ||
2259 | @item z | |
2260 | Stack pointer register (SP). | |
db92bd22 GQ |
2261 | |
2262 | @item Q | |
2263 | A memory address which uses a base register with a short offset | |
2264 | or with a index register with its scale. | |
2265 | ||
2266 | @item W | |
2267 | A memory address which uses a base register with a index register | |
2268 | with its scale. | |
fbceb769 SL |
2269 | @end table |
2270 | ||
2271 | @ifset INTERNALS | |
2272 | The C-SKY back end supports a large set of additional constraints | |
2273 | that are only useful for instruction selection or splitting rather | |
2274 | than inline asm, such as constraints representing constant integer | |
2275 | ranges accepted by particular instruction encodings. | |
2276 | Refer to the source code for details. | |
2277 | @end ifset | |
2278 | ||
feeeff5c JR |
2279 | @item Epiphany---@file{config/epiphany/constraints.md} |
2280 | @table @code | |
2281 | @item U16 | |
2282 | An unsigned 16-bit constant. | |
2283 | ||
2284 | @item K | |
2285 | An unsigned 5-bit constant. | |
2286 | ||
2287 | @item L | |
2288 | A signed 11-bit constant. | |
2289 | ||
2290 | @item Cm1 | |
2291 | A signed 11-bit constant added to @minus{}1. | |
2292 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
2293 | ||
2294 | @item Cl1 | |
2295 | Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest | |
2296 | being a block of trailing zeroes. | |
2297 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
2298 | ||
2299 | @item Cr1 | |
2300 | Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the | |
2301 | rest being zeroes. Or to put it another way, one less than a power of two. | |
2302 | Can only match when the @option{-m1reg-@var{reg}} option is active. | |
2303 | ||
2304 | @item Cal | |
2305 | Constant for arithmetic/logical operations. | |
2306 | This is like @code{i}, except that for position independent code, | |
2307 | no symbols / expressions needing relocations are allowed. | |
2308 | ||
2309 | @item Csy | |
2310 | Symbolic constant for call/jump instruction. | |
2311 | ||
2312 | @item Rcs | |
2313 | The register class usable in short insns. This is a register class | |
2314 | constraint, and can thus drive register allocation. | |
2315 | This constraint won't match unless @option{-mprefer-short-insn-regs} is | |
2316 | in effect. | |
2317 | ||
2318 | @item Rsc | |
2319 | The the register class of registers that can be used to hold a | |
2320 | sibcall call address. I.e., a caller-saved register. | |
2321 | ||
2322 | @item Rct | |
2323 | Core control register class. | |
2324 | ||
2325 | @item Rgs | |
2326 | The register group usable in short insns. | |
2327 | This constraint does not use a register class, so that it only | |
2328 | passively matches suitable registers, and doesn't drive register allocation. | |
2329 | ||
2330 | @ifset INTERNALS | |
2331 | @item Car | |
2332 | Constant suitable for the addsi3_r pattern. This is a valid offset | |
2333 | For byte, halfword, or word addressing. | |
2334 | @end ifset | |
2335 | ||
2336 | @item Rra | |
2337 | Matches the return address if it can be replaced with the link register. | |
2338 | ||
2339 | @item Rcc | |
2340 | Matches the integer condition code register. | |
2341 | ||
2342 | @item Sra | |
2343 | Matches the return address if it is in a stack slot. | |
2344 | ||
2345 | @item Cfm | |
2346 | Matches control register values to switch fp mode, which are encapsulated in | |
2347 | @code{UNSPEC_FP_MODE}. | |
2348 | @end table | |
2349 | ||
b4fbcb1b | 2350 | @item FRV---@file{config/frv/frv.h} |
b25364a0 | 2351 | @table @code |
b4fbcb1b SL |
2352 | @item a |
2353 | Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}). | |
b25364a0 S |
2354 | |
2355 | @item b | |
b4fbcb1b SL |
2356 | Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}). |
2357 | ||
2358 | @item c | |
2359 | Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and | |
2360 | @code{icc0} to @code{icc3}). | |
2361 | ||
2362 | @item d | |
2363 | Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}). | |
2364 | ||
2365 | @item e | |
2366 | Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}). | |
2367 | Odd registers are excluded not in the class but through the use of a machine | |
2368 | mode larger than 4 bytes. | |
2369 | ||
2370 | @item f | |
2371 | Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}). | |
2372 | ||
2373 | @item h | |
2374 | Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}). | |
2375 | Odd registers are excluded not in the class but through the use of a machine | |
2376 | mode larger than 4 bytes. | |
2377 | ||
2378 | @item l | |
2379 | Register in the class @code{LR_REG} (the @code{lr} register). | |
2380 | ||
2381 | @item q | |
2382 | Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}). | |
2383 | Register numbers not divisible by 4 are excluded not in the class but through | |
2384 | the use of a machine mode larger than 8 bytes. | |
b25364a0 S |
2385 | |
2386 | @item t | |
b4fbcb1b | 2387 | Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}). |
b25364a0 | 2388 | |
b4fbcb1b SL |
2389 | @item u |
2390 | Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}). | |
2391 | ||
2392 | @item v | |
2393 | Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}). | |
2394 | ||
2395 | @item w | |
2396 | Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}). | |
2397 | ||
2398 | @item x | |
2399 | Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}). | |
2400 | Register numbers not divisible by 4 are excluded not in the class but through | |
2401 | the use of a machine mode larger than 8 bytes. | |
2402 | ||
2403 | @item z | |
2404 | Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}). | |
2405 | ||
2406 | @item A | |
2407 | Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}). | |
2408 | ||
2409 | @item B | |
2410 | Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}). | |
2411 | ||
2412 | @item C | |
2413 | Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}). | |
2414 | ||
2415 | @item G | |
2416 | Floating point constant zero | |
b25364a0 S |
2417 | |
2418 | @item I | |
b4fbcb1b | 2419 | 6-bit signed integer constant |
b25364a0 S |
2420 | |
2421 | @item J | |
b4fbcb1b | 2422 | 10-bit signed integer constant |
b25364a0 S |
2423 | |
2424 | @item L | |
b4fbcb1b | 2425 | 16-bit signed integer constant |
b25364a0 S |
2426 | |
2427 | @item M | |
b4fbcb1b | 2428 | 16-bit unsigned integer constant |
b25364a0 S |
2429 | |
2430 | @item N | |
b4fbcb1b SL |
2431 | 12-bit signed integer constant that is negative---i.e.@: in the |
2432 | range of @minus{}2048 to @minus{}1 | |
2433 | ||
2434 | @item O | |
2435 | Constant zero | |
2436 | ||
2437 | @item P | |
2438 | 12-bit signed integer constant that is greater than zero---i.e.@: in the | |
2439 | range of 1 to 2047. | |
b25364a0 | 2440 | |
b25364a0 S |
2441 | @end table |
2442 | ||
fef939d6 JB |
2443 | @item FT32---@file{config/ft32/constraints.md} |
2444 | @table @code | |
2445 | @item A | |
2446 | An absolute address | |
2447 | ||
2448 | @item B | |
2449 | An offset address | |
2450 | ||
2451 | @item W | |
2452 | A register indirect memory operand | |
2453 | ||
2454 | @item e | |
2455 | An offset address. | |
2456 | ||
2457 | @item f | |
2458 | An offset address. | |
2459 | ||
2460 | @item O | |
2461 | The constant zero or one | |
2462 | ||
2463 | @item I | |
2464 | A 16-bit signed constant (@minus{}32768 @dots{} 32767) | |
2465 | ||
2466 | @item w | |
2467 | A bitfield mask suitable for bext or bins | |
2468 | ||
2469 | @item x | |
2470 | An inverted bitfield mask suitable for bext or bins | |
2471 | ||
2472 | @item L | |
2473 | A 16-bit unsigned constant, multiple of 4 (0 @dots{} 65532) | |
2474 | ||
2475 | @item S | |
2476 | A 20-bit signed constant (@minus{}524288 @dots{} 524287) | |
2477 | ||
2478 | @item b | |
2479 | A constant for a bitfield width (1 @dots{} 16) | |
2480 | ||
2481 | @item KA | |
2482 | A 10-bit signed constant (@minus{}512 @dots{} 511) | |
2483 | ||
2484 | @end table | |
2485 | ||
8119b4e4 JDA |
2486 | @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h} |
2487 | @table @code | |
2488 | @item a | |
2489 | General register 1 | |
2490 | ||
2491 | @item f | |
2492 | Floating point register | |
2493 | ||
2494 | @item q | |
2495 | Shift amount register | |
2496 | ||
2497 | @item x | |
2498 | Floating point register (deprecated) | |
2499 | ||
2500 | @item y | |
2501 | Upper floating point register (32-bit), floating point register (64-bit) | |
2502 | ||
2503 | @item Z | |
2504 | Any register | |
2505 | ||
2506 | @item I | |
2507 | Signed 11-bit integer constant | |
2508 | ||
2509 | @item J | |
2510 | Signed 14-bit integer constant | |
2511 | ||
2512 | @item K | |
2513 | Integer constant that can be deposited with a @code{zdepi} instruction | |
2514 | ||
2515 | @item L | |
2516 | Signed 5-bit integer constant | |
2517 | ||
2518 | @item M | |
2519 | Integer constant 0 | |
2520 | ||
2521 | @item N | |
2522 | Integer constant that can be loaded with a @code{ldil} instruction | |
2523 | ||
2524 | @item O | |
2525 | Integer constant whose value plus one is a power of 2 | |
2526 | ||
2527 | @item P | |
2528 | Integer constant that can be used for @code{and} operations in @code{depi} | |
2529 | and @code{extru} instructions | |
2530 | ||
2531 | @item S | |
2532 | Integer constant 31 | |
2533 | ||
2534 | @item U | |
2535 | Integer constant 63 | |
2536 | ||
2537 | @item G | |
2538 | Floating-point constant 0.0 | |
2539 | ||
2540 | @item A | |
2541 | A @code{lo_sum} data-linkage-table memory operand | |
2542 | ||
2543 | @item Q | |
2544 | A memory operand that can be used as the destination operand of an | |
2545 | integer store instruction | |
2546 | ||
2547 | @item R | |
2548 | A scaled or unscaled indexed memory operand | |
2549 | ||
2550 | @item T | |
2551 | A memory operand for floating-point loads and stores | |
2552 | ||
2553 | @item W | |
2554 | A register indirect memory operand | |
2555 | @end table | |
2556 | ||
b4fbcb1b | 2557 | @item Intel IA-64---@file{config/ia64/ia64.h} |
03dda8e3 | 2558 | @table @code |
b4fbcb1b SL |
2559 | @item a |
2560 | General register @code{r0} to @code{r3} for @code{addl} instruction | |
03dda8e3 | 2561 | |
b4fbcb1b SL |
2562 | @item b |
2563 | Branch register | |
7a430e3b SC |
2564 | |
2565 | @item c | |
2566 | Predicate register (@samp{c} as in ``conditional'') | |
2567 | ||
b4fbcb1b SL |
2568 | @item d |
2569 | Application register residing in M-unit | |
0d4a78eb | 2570 | |
b4fbcb1b SL |
2571 | @item e |
2572 | Application register residing in I-unit | |
0d4a78eb | 2573 | |
b4fbcb1b SL |
2574 | @item f |
2575 | Floating-point register | |
3efd5670 | 2576 | |
b4fbcb1b SL |
2577 | @item m |
2578 | Memory operand. If used together with @samp{<} or @samp{>}, | |
2579 | the operand can have postincrement and postdecrement which | |
2580 | require printing with @samp{%Pn} on IA-64. | |
3efd5670 | 2581 | |
b4fbcb1b SL |
2582 | @item G |
2583 | Floating-point constant 0.0 or 1.0 | |
0d4a78eb | 2584 | |
b4fbcb1b SL |
2585 | @item I |
2586 | 14-bit signed integer constant | |
0d4a78eb BS |
2587 | |
2588 | @item J | |
b4fbcb1b SL |
2589 | 22-bit signed integer constant |
2590 | ||
2591 | @item K | |
2592 | 8-bit signed integer constant for logical instructions | |
0d4a78eb BS |
2593 | |
2594 | @item L | |
b4fbcb1b | 2595 | 8-bit adjusted signed integer constant for compare pseudo-ops |
0d4a78eb | 2596 | |
b4fbcb1b SL |
2597 | @item M |
2598 | 6-bit unsigned integer constant for shift counts | |
2599 | ||
2600 | @item N | |
2601 | 9-bit signed integer constant for load and store postincrements | |
2602 | ||
2603 | @item O | |
2604 | The constant zero | |
2605 | ||
2606 | @item P | |
2607 | 0 or @minus{}1 for @code{dep} instruction | |
0d4a78eb BS |
2608 | |
2609 | @item Q | |
b4fbcb1b SL |
2610 | Non-volatile memory for floating-point loads and stores |
2611 | ||
2612 | @item R | |
2613 | Integer constant in the range 1 to 4 for @code{shladd} instruction | |
2614 | ||
2615 | @item S | |
2616 | Memory operand except postincrement and postdecrement. This is | |
2617 | now roughly the same as @samp{m} when not used together with @samp{<} | |
2618 | or @samp{>}. | |
0d4a78eb BS |
2619 | @end table |
2620 | ||
e53b6e56 | 2621 | @item M32C---@file{config/m32c/m32c.cc} |
74fe790b | 2622 | @table @code |
38b2d076 DD |
2623 | @item Rsp |
2624 | @itemx Rfb | |
2625 | @itemx Rsb | |
2626 | @samp{$sp}, @samp{$fb}, @samp{$sb}. | |
2627 | ||
2628 | @item Rcr | |
2629 | Any control register, when they're 16 bits wide (nothing if control | |
2630 | registers are 24 bits wide) | |
2631 | ||
2632 | @item Rcl | |
2633 | Any control register, when they're 24 bits wide. | |
2634 | ||
2635 | @item R0w | |
2636 | @itemx R1w | |
2637 | @itemx R2w | |
2638 | @itemx R3w | |
2639 | $r0, $r1, $r2, $r3. | |
2640 | ||
2641 | @item R02 | |
2642 | $r0 or $r2, or $r2r0 for 32 bit values. | |
2643 | ||
2644 | @item R13 | |
2645 | $r1 or $r3, or $r3r1 for 32 bit values. | |
2646 | ||
2647 | @item Rdi | |
2648 | A register that can hold a 64 bit value. | |
2649 | ||
2650 | @item Rhl | |
2651 | $r0 or $r1 (registers with addressable high/low bytes) | |
2652 | ||
2653 | @item R23 | |
2654 | $r2 or $r3 | |
2655 | ||
2656 | @item Raa | |
2657 | Address registers | |
2658 | ||
2659 | @item Raw | |
2660 | Address registers when they're 16 bits wide. | |
2661 | ||
2662 | @item Ral | |
2663 | Address registers when they're 24 bits wide. | |
2664 | ||
2665 | @item Rqi | |
2666 | Registers that can hold QI values. | |
2667 | ||
2668 | @item Rad | |
2669 | Registers that can be used with displacements ($a0, $a1, $sb). | |
2670 | ||
2671 | @item Rsi | |
2672 | Registers that can hold 32 bit values. | |
2673 | ||
2674 | @item Rhi | |
2675 | Registers that can hold 16 bit values. | |
2676 | ||
2677 | @item Rhc | |
2678 | Registers chat can hold 16 bit values, including all control | |
2679 | registers. | |
2680 | ||
2681 | @item Rra | |
2682 | $r0 through R1, plus $a0 and $a1. | |
2683 | ||
2684 | @item Rfl | |
2685 | The flags register. | |
2686 | ||
2687 | @item Rmm | |
2688 | The memory-based pseudo-registers $mem0 through $mem15. | |
2689 | ||
2690 | @item Rpi | |
2691 | Registers that can hold pointers (16 bit registers for r8c, m16c; 24 | |
2692 | bit registers for m32cm, m32c). | |
2693 | ||
2694 | @item Rpa | |
2695 | Matches multiple registers in a PARALLEL to form a larger register. | |
2696 | Used to match function return values. | |
2697 | ||
2698 | @item Is3 | |
8ad1dde7 | 2699 | @minus{}8 @dots{} 7 |
38b2d076 DD |
2700 | |
2701 | @item IS1 | |
8ad1dde7 | 2702 | @minus{}128 @dots{} 127 |
38b2d076 DD |
2703 | |
2704 | @item IS2 | |
8ad1dde7 | 2705 | @minus{}32768 @dots{} 32767 |
38b2d076 DD |
2706 | |
2707 | @item IU2 | |
2708 | 0 @dots{} 65535 | |
2709 | ||
2710 | @item In4 | |
8ad1dde7 | 2711 | @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8 |
38b2d076 DD |
2712 | |
2713 | @item In5 | |
8ad1dde7 | 2714 | @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16 |
38b2d076 | 2715 | |
23fed240 | 2716 | @item In6 |
8ad1dde7 | 2717 | @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32 |
38b2d076 DD |
2718 | |
2719 | @item IM2 | |
8ad1dde7 | 2720 | @minus{}65536 @dots{} @minus{}1 |
38b2d076 DD |
2721 | |
2722 | @item Ilb | |
2723 | An 8 bit value with exactly one bit set. | |
2724 | ||
2725 | @item Ilw | |
2726 | A 16 bit value with exactly one bit set. | |
2727 | ||
2728 | @item Sd | |
2729 | The common src/dest memory addressing modes. | |
2730 | ||
2731 | @item Sa | |
2732 | Memory addressed using $a0 or $a1. | |
2733 | ||
2734 | @item Si | |
2735 | Memory addressed with immediate addresses. | |
2736 | ||
2737 | @item Ss | |
2738 | Memory addressed using the stack pointer ($sp). | |
2739 | ||
2740 | @item Sf | |
2741 | Memory addressed using the frame base register ($fb). | |
2742 | ||
2743 | @item Ss | |
2744 | Memory addressed using the small base register ($sb). | |
2745 | ||
2746 | @item S1 | |
2747 | $r1h | |
e2491744 DD |
2748 | @end table |
2749 | ||
8766689a | 2750 | @item LoongArch---@file{config/loongarch/constraints.md} |
2751 | @table @code | |
2752 | @item f | |
2753 | A floating-point register (if available). | |
2754 | @item k | |
2755 | A memory operand whose address is formed by a base register and | |
2756 | (optionally scaled) index register. | |
2757 | @item l | |
2758 | A signed 16-bit constant. | |
2759 | @item m | |
2760 | A memory operand whose address is formed by a base register and offset | |
2761 | that is suitable for use in instructions with the same addressing mode | |
2762 | as @code{st.w} and @code{ld.w}. | |
2763 | @item I | |
2764 | A signed 12-bit constant (for arithmetic instructions). | |
2765 | @item K | |
2766 | An unsigned 12-bit constant (for logic instructions). | |
2767 | @item ZB | |
2768 | An address that is held in a general-purpose register. | |
2769 | The offset is zero. | |
2770 | @item ZC | |
2771 | A memory operand whose address is formed by a base register and offset | |
2772 | that is suitable for use in instructions with the same addressing mode | |
2773 | as @code{ll.w} and @code{sc.w}. | |
2774 | @end table | |
2775 | ||
80920132 ME |
2776 | @item MicroBlaze---@file{config/microblaze/constraints.md} |
2777 | @table @code | |
2778 | @item d | |
2779 | A general register (@code{r0} to @code{r31}). | |
2780 | ||
2781 | @item z | |
2782 | A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}). | |
e2491744 | 2783 | |
74fe790b | 2784 | @end table |
38b2d076 | 2785 | |
cbbb5b6d | 2786 | @item MIPS---@file{config/mips/constraints.md} |
4226378a PK |
2787 | @table @code |
2788 | @item d | |
0cb14750 MR |
2789 | A general-purpose register. This is equivalent to @code{r} unless |
2790 | generating MIPS16 code, in which case the MIPS16 register set is used. | |
4226378a PK |
2791 | |
2792 | @item f | |
cbbb5b6d | 2793 | A floating-point register (if available). |
4226378a PK |
2794 | |
2795 | @item h | |
21dfc6dc | 2796 | Formerly the @code{hi} register. This constraint is no longer supported. |
4226378a PK |
2797 | |
2798 | @item l | |
21dfc6dc RS |
2799 | The @code{lo} register. Use this register to store values that are |
2800 | no bigger than a word. | |
4226378a PK |
2801 | |
2802 | @item x | |
21dfc6dc RS |
2803 | The concatenated @code{hi} and @code{lo} registers. Use this register |
2804 | to store doubleword values. | |
cbbb5b6d RS |
2805 | |
2806 | @item c | |
2807 | A register suitable for use in an indirect jump. This will always be | |
2808 | @code{$25} for @option{-mabicalls}. | |
4226378a | 2809 | |
2feaae20 RS |
2810 | @item v |
2811 | Register @code{$3}. Do not use this constraint in new code; | |
2812 | it is retained only for compatibility with glibc. | |
2813 | ||
4226378a | 2814 | @item y |
cbbb5b6d | 2815 | Equivalent to @code{r}; retained for backwards compatibility. |
4226378a PK |
2816 | |
2817 | @item z | |
cbbb5b6d | 2818 | A floating-point condition code register. |
4226378a PK |
2819 | |
2820 | @item I | |
cbbb5b6d | 2821 | A signed 16-bit constant (for arithmetic instructions). |
4226378a PK |
2822 | |
2823 | @item J | |
cbbb5b6d | 2824 | Integer zero. |
4226378a PK |
2825 | |
2826 | @item K | |
cbbb5b6d | 2827 | An unsigned 16-bit constant (for logic instructions). |
4226378a PK |
2828 | |
2829 | @item L | |
cbbb5b6d RS |
2830 | A signed 32-bit constant in which the lower 16 bits are zero. |
2831 | Such constants can be loaded using @code{lui}. | |
4226378a PK |
2832 | |
2833 | @item M | |
cbbb5b6d RS |
2834 | A constant that cannot be loaded using @code{lui}, @code{addiu} |
2835 | or @code{ori}. | |
4226378a PK |
2836 | |
2837 | @item N | |
8ad1dde7 | 2838 | A constant in the range @minus{}65535 to @minus{}1 (inclusive). |
4226378a PK |
2839 | |
2840 | @item O | |
cbbb5b6d | 2841 | A signed 15-bit constant. |
4226378a PK |
2842 | |
2843 | @item P | |
cbbb5b6d | 2844 | A constant in the range 1 to 65535 (inclusive). |
4226378a PK |
2845 | |
2846 | @item G | |
cbbb5b6d | 2847 | Floating-point zero. |
4226378a PK |
2848 | |
2849 | @item R | |
cbbb5b6d | 2850 | An address that can be used in a non-macro load or store. |
22c4c869 CM |
2851 | |
2852 | @item ZC | |
047b52f6 MF |
2853 | A memory operand whose address is formed by a base register and offset |
2854 | that is suitable for use in instructions with the same addressing mode | |
2855 | as @code{ll} and @code{sc}. | |
22c4c869 CM |
2856 | |
2857 | @item ZD | |
82f84ecb MF |
2858 | An address suitable for a @code{prefetch} instruction, or for any other |
2859 | instruction with the same addressing mode as @code{prefetch}. | |
4226378a PK |
2860 | @end table |
2861 | ||
c47b0cb4 | 2862 | @item Motorola 680x0---@file{config/m68k/constraints.md} |
03dda8e3 RK |
2863 | @table @code |
2864 | @item a | |
2865 | Address register | |
2866 | ||
2867 | @item d | |
2868 | Data register | |
2869 | ||
2870 | @item f | |
2871 | 68881 floating-point register, if available | |
2872 | ||
03dda8e3 RK |
2873 | @item I |
2874 | Integer in the range 1 to 8 | |
2875 | ||
2876 | @item J | |
1e5f973d | 2877 | 16-bit signed number |
03dda8e3 RK |
2878 | |
2879 | @item K | |
2880 | Signed number whose magnitude is greater than 0x80 | |
2881 | ||
2882 | @item L | |
630d3d5a | 2883 | Integer in the range @minus{}8 to @minus{}1 |
03dda8e3 RK |
2884 | |
2885 | @item M | |
2886 | Signed number whose magnitude is greater than 0x100 | |
2887 | ||
c47b0cb4 MK |
2888 | @item N |
2889 | Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate | |
2890 | ||
2891 | @item O | |
2892 | 16 (for rotate using swap) | |
2893 | ||
2894 | @item P | |
2895 | Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate | |
2896 | ||
2897 | @item R | |
2898 | Numbers that mov3q can handle | |
2899 | ||
03dda8e3 RK |
2900 | @item G |
2901 | Floating point constant that is not a 68881 constant | |
c47b0cb4 MK |
2902 | |
2903 | @item S | |
2904 | Operands that satisfy 'm' when -mpcrel is in effect | |
2905 | ||
2906 | @item T | |
2907 | Operands that satisfy 's' when -mpcrel is not in effect | |
2908 | ||
2909 | @item Q | |
2910 | Address register indirect addressing mode | |
2911 | ||
2912 | @item U | |
2913 | Register offset addressing | |
2914 | ||
2915 | @item W | |
2916 | const_call_operand | |
2917 | ||
2918 | @item Cs | |
2919 | symbol_ref or const | |
2920 | ||
2921 | @item Ci | |
2922 | const_int | |
2923 | ||
2924 | @item C0 | |
2925 | const_int 0 | |
2926 | ||
2927 | @item Cj | |
2928 | Range of signed numbers that don't fit in 16 bits | |
2929 | ||
2930 | @item Cmvq | |
2931 | Integers valid for mvq | |
2932 | ||
2933 | @item Capsw | |
2934 | Integers valid for a moveq followed by a swap | |
2935 | ||
2936 | @item Cmvz | |
2937 | Integers valid for mvz | |
2938 | ||
2939 | @item Cmvs | |
2940 | Integers valid for mvs | |
2941 | ||
2942 | @item Ap | |
2943 | push_operand | |
2944 | ||
2945 | @item Ac | |
2946 | Non-register operands allowed in clr | |
2947 | ||
03dda8e3 RK |
2948 | @end table |
2949 | ||
cceb575c AG |
2950 | @item Moxie---@file{config/moxie/constraints.md} |
2951 | @table @code | |
2952 | @item A | |
2953 | An absolute address | |
2954 | ||
2955 | @item B | |
2956 | An offset address | |
2957 | ||
2958 | @item W | |
2959 | A register indirect memory operand | |
2960 | ||
2961 | @item I | |
2962 | A constant in the range of 0 to 255. | |
2963 | ||
2964 | @item N | |
8ad1dde7 | 2965 | A constant in the range of 0 to @minus{}255. |
cceb575c AG |
2966 | |
2967 | @end table | |
2968 | ||
f6a83b4a DD |
2969 | @item MSP430--@file{config/msp430/constraints.md} |
2970 | @table @code | |
2971 | ||
2972 | @item R12 | |
2973 | Register R12. | |
2974 | ||
2975 | @item R13 | |
2976 | Register R13. | |
2977 | ||
2978 | @item K | |
2979 | Integer constant 1. | |
2980 | ||
2981 | @item L | |
2982 | Integer constant -1^20..1^19. | |
2983 | ||
2984 | @item M | |
2985 | Integer constant 1-4. | |
2986 | ||
2987 | @item Ya | |
2988 | Memory references which do not require an extended MOVX instruction. | |
2989 | ||
2990 | @item Yl | |
2991 | Memory reference, labels only. | |
2992 | ||
2993 | @item Ys | |
2994 | Memory reference, stack only. | |
2995 | ||
2996 | @end table | |
2997 | ||
9304f876 CJW |
2998 | @item NDS32---@file{config/nds32/constraints.md} |
2999 | @table @code | |
3000 | @item w | |
3001 | LOW register class $r0 to $r7 constraint for V3/V3M ISA. | |
3002 | @item l | |
3003 | LOW register class $r0 to $r7. | |
3004 | @item d | |
3005 | MIDDLE register class $r0 to $r11, $r16 to $r19. | |
3006 | @item h | |
3007 | HIGH register class $r12 to $r14, $r20 to $r31. | |
3008 | @item t | |
3009 | Temporary assist register $ta (i.e.@: $r15). | |
3010 | @item k | |
3011 | Stack register $sp. | |
3012 | @item Iu03 | |
3013 | Unsigned immediate 3-bit value. | |
3014 | @item In03 | |
3015 | Negative immediate 3-bit value in the range of @minus{}7--0. | |
3016 | @item Iu04 | |
3017 | Unsigned immediate 4-bit value. | |
3018 | @item Is05 | |
3019 | Signed immediate 5-bit value. | |
3020 | @item Iu05 | |
3021 | Unsigned immediate 5-bit value. | |
3022 | @item In05 | |
3023 | Negative immediate 5-bit value in the range of @minus{}31--0. | |
3024 | @item Ip05 | |
3025 | Unsigned immediate 5-bit value for movpi45 instruction with range 16--47. | |
3026 | @item Iu06 | |
3027 | Unsigned immediate 6-bit value constraint for addri36.sp instruction. | |
3028 | @item Iu08 | |
3029 | Unsigned immediate 8-bit value. | |
3030 | @item Iu09 | |
3031 | Unsigned immediate 9-bit value. | |
3032 | @item Is10 | |
3033 | Signed immediate 10-bit value. | |
3034 | @item Is11 | |
3035 | Signed immediate 11-bit value. | |
3036 | @item Is15 | |
3037 | Signed immediate 15-bit value. | |
3038 | @item Iu15 | |
3039 | Unsigned immediate 15-bit value. | |
3040 | @item Ic15 | |
3041 | A constant which is not in the range of imm15u but ok for bclr instruction. | |
3042 | @item Ie15 | |
3043 | A constant which is not in the range of imm15u but ok for bset instruction. | |
3044 | @item It15 | |
3045 | A constant which is not in the range of imm15u but ok for btgl instruction. | |
3046 | @item Ii15 | |
3047 | A constant whose compliment value is in the range of imm15u | |
3048 | and ok for bitci instruction. | |
3049 | @item Is16 | |
3050 | Signed immediate 16-bit value. | |
3051 | @item Is17 | |
3052 | Signed immediate 17-bit value. | |
3053 | @item Is19 | |
3054 | Signed immediate 19-bit value. | |
3055 | @item Is20 | |
3056 | Signed immediate 20-bit value. | |
3057 | @item Ihig | |
3058 | The immediate value that can be simply set high 20-bit. | |
3059 | @item Izeb | |
3060 | The immediate value 0xff. | |
3061 | @item Izeh | |
3062 | The immediate value 0xffff. | |
3063 | @item Ixls | |
3064 | The immediate value 0x01. | |
3065 | @item Ix11 | |
3066 | The immediate value 0x7ff. | |
3067 | @item Ibms | |
3068 | The immediate value with power of 2. | |
3069 | @item Ifex | |
3070 | The immediate value with power of 2 minus 1. | |
3071 | @item U33 | |
3072 | Memory constraint for 333 format. | |
3073 | @item U45 | |
3074 | Memory constraint for 45 format. | |
3075 | @item U37 | |
3076 | Memory constraint for 37 format. | |
3077 | @end table | |
3078 | ||
e430824f CLT |
3079 | @item Nios II family---@file{config/nios2/constraints.md} |
3080 | @table @code | |
3081 | ||
3082 | @item I | |
3083 | Integer that is valid as an immediate operand in an | |
3084 | instruction taking a signed 16-bit number. Range | |
3085 | @minus{}32768 to 32767. | |
3086 | ||
3087 | @item J | |
3088 | Integer that is valid as an immediate operand in an | |
3089 | instruction taking an unsigned 16-bit number. Range | |
3090 | 0 to 65535. | |
3091 | ||
3092 | @item K | |
3093 | Integer that is valid as an immediate operand in an | |
3094 | instruction taking only the upper 16-bits of a | |
3095 | 32-bit number. Range 32-bit numbers with the lower | |
3096 | 16-bits being 0. | |
3097 | ||
3098 | @item L | |
3099 | Integer that is valid as an immediate operand for a | |
3100 | shift instruction. Range 0 to 31. | |
3101 | ||
3102 | @item M | |
3103 | Integer that is valid as an immediate operand for | |
3104 | only the value 0. Can be used in conjunction with | |
3105 | the format modifier @code{z} to use @code{r0} | |
3106 | instead of @code{0} in the assembly output. | |
3107 | ||
3108 | @item N | |
3109 | Integer that is valid as an immediate operand for | |
3110 | a custom instruction opcode. Range 0 to 255. | |
3111 | ||
3bbbe009 SL |
3112 | @item P |
3113 | An immediate operand for R2 andchi/andci instructions. | |
3114 | ||
e430824f CLT |
3115 | @item S |
3116 | Matches immediates which are addresses in the small | |
3117 | data section and therefore can be added to @code{gp} | |
3118 | as a 16-bit immediate to re-create their 32-bit value. | |
3119 | ||
524d2e49 SL |
3120 | @item U |
3121 | Matches constants suitable as an operand for the rdprs and | |
3122 | cache instructions. | |
3123 | ||
3124 | @item v | |
3125 | A memory operand suitable for Nios II R2 load/store | |
3126 | exclusive instructions. | |
3127 | ||
42e6ab74 SL |
3128 | @item w |
3129 | A memory operand suitable for load/store IO and cache | |
3130 | instructions. | |
3131 | ||
e430824f CLT |
3132 | @ifset INTERNALS |
3133 | @item T | |
3134 | A @code{const} wrapped @code{UNSPEC} expression, | |
3135 | representing a supported PIC or TLS relocation. | |
3136 | @end ifset | |
3137 | ||
3138 | @end table | |
3139 | ||
3965b35f SH |
3140 | @item OpenRISC---@file{config/or1k/constraints.md} |
3141 | @table @code | |
3142 | @item I | |
3143 | Integer that is valid as an immediate operand in an | |
3144 | instruction taking a signed 16-bit number. Range | |
3145 | @minus{}32768 to 32767. | |
3146 | ||
3147 | @item K | |
3148 | Integer that is valid as an immediate operand in an | |
3149 | instruction taking an unsigned 16-bit number. Range | |
3150 | 0 to 65535. | |
3151 | ||
3152 | @item M | |
3153 | Signed 16-bit constant shifted left 16 bits. (Used with @code{l.movhi}) | |
3154 | ||
3155 | @item O | |
3156 | Zero | |
3157 | ||
3158 | @ifset INTERNALS | |
3159 | @item c | |
3160 | Register usable for sibcalls. | |
3161 | @end ifset | |
3162 | ||
3163 | @end table | |
3164 | ||
5e426dd4 PK |
3165 | @item PDP-11---@file{config/pdp11/constraints.md} |
3166 | @table @code | |
3167 | @item a | |
3168 | Floating point registers AC0 through AC3. These can be loaded from/to | |
3169 | memory with a single instruction. | |
3170 | ||
3171 | @item d | |
868e54d1 PK |
3172 | Odd numbered general registers (R1, R3, R5). These are used for |
3173 | 16-bit multiply operations. | |
5e426dd4 | 3174 | |
b4324a14 PK |
3175 | @item D |
3176 | A memory reference that is encoded within the opcode, but not | |
3177 | auto-increment or auto-decrement. | |
3178 | ||
5e426dd4 PK |
3179 | @item f |
3180 | Any of the floating point registers (AC0 through AC5). | |
3181 | ||
3182 | @item G | |
3183 | Floating point constant 0. | |
3184 | ||
b4324a14 PK |
3185 | @item h |
3186 | Floating point registers AC4 and AC5. These cannot be loaded from/to | |
3187 | memory with a single instruction. | |
3188 | ||
5e426dd4 PK |
3189 | @item I |
3190 | An integer constant that fits in 16 bits. | |
3191 | ||
b4fbcb1b SL |
3192 | @item J |
3193 | An integer constant whose low order 16 bits are zero. | |
3194 | ||
3195 | @item K | |
3196 | An integer constant that does not meet the constraints for codes | |
3197 | @samp{I} or @samp{J}. | |
3198 | ||
3199 | @item L | |
3200 | The integer constant 1. | |
3201 | ||
3202 | @item M | |
3203 | The integer constant @minus{}1. | |
3204 | ||
3205 | @item N | |
3206 | The integer constant 0. | |
3207 | ||
3208 | @item O | |
b4324a14 | 3209 | Integer constants 0 through 3; shifts by these |
b4fbcb1b SL |
3210 | amounts are handled as multiple single-bit shifts rather than a single |
3211 | variable-length shift. | |
3212 | ||
3213 | @item Q | |
3214 | A memory reference which requires an additional word (address or | |
3215 | offset) after the opcode. | |
3216 | ||
3217 | @item R | |
3218 | A memory reference that is encoded within the opcode. | |
3219 | ||
3220 | @end table | |
3221 | ||
3222 | @item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md} | |
3223 | @table @code | |
e01975f9 SB |
3224 | @item r |
3225 | A general purpose register (GPR), @code{r0}@dots{}@code{r31}. | |
b4fbcb1b | 3226 | |
e01975f9 SB |
3227 | @item b |
3228 | A base register. Like @code{r}, but @code{r0} is not allowed, so | |
3229 | @code{r1}@dots{}@code{r31}. | |
b4fbcb1b SL |
3230 | |
3231 | @item f | |
e01975f9 SB |
3232 | A floating point register (FPR), @code{f0}@dots{}@code{f31}. |
3233 | ||
3234 | @item d | |
3235 | A floating point register. This is the same as @code{f} nowadays; | |
3236 | historically @code{f} was for single-precision and @code{d} was for | |
3237 | double-precision floating point. | |
b4fbcb1b SL |
3238 | |
3239 | @item v | |
e01975f9 | 3240 | An Altivec vector register (VR), @code{v0}@dots{}@code{v31}. |
b4fbcb1b SL |
3241 | |
3242 | @item wa | |
e01975f9 SB |
3243 | A VSX register (VSR), @code{vs0}@dots{}@code{vs63}. This is either an |
3244 | FPR (@code{vs0}@dots{}@code{vs31} are @code{f0}@dots{}@code{f31}) or a VR | |
3245 | (@code{vs32}@dots{}@code{vs63} are @code{v0}@dots{}@code{v31}). | |
b4fbcb1b | 3246 | |
e01975f9 SB |
3247 | When using @code{wa}, you should use the @code{%x} output modifier, so that |
3248 | the correct register number is printed. For example: | |
6a116f14 MM |
3249 | |
3250 | @smallexample | |
dc703d70 SL |
3251 | asm ("xvadddp %x0,%x1,%x2" |
3252 | : "=wa" (v1) | |
3253 | : "wa" (v2), "wa" (v3)); | |
6a116f14 MM |
3254 | @end smallexample |
3255 | ||
e01975f9 | 3256 | You should not use @code{%x} for @code{v} operands: |
dd551aa1 MM |
3257 | |
3258 | @smallexample | |
dc703d70 SL |
3259 | asm ("xsaddqp %0,%1,%2" |
3260 | : "=v" (v1) | |
3261 | : "v" (v2), "v" (v3)); | |
dd551aa1 MM |
3262 | @end smallexample |
3263 | ||
e01975f9 SB |
3264 | @ifset INTERNALS |
3265 | @item h | |
3266 | A special register (@code{vrsave}, @code{ctr}, or @code{lr}). | |
3267 | @end ifset | |
dd551aa1 | 3268 | |
e01975f9 SB |
3269 | @item c |
3270 | The count register, @code{ctr}. | |
dd551aa1 | 3271 | |
e01975f9 SB |
3272 | @item l |
3273 | The link register, @code{lr}. | |
3274 | ||
3275 | @item x | |
3276 | Condition register field 0, @code{cr0}. | |
3277 | ||
3278 | @item y | |
3279 | Any condition register field, @code{cr0}@dots{}@code{cr7}. | |
3280 | ||
3281 | @ifset INTERNALS | |
3282 | @item z | |
3283 | The carry bit, @code{XER[CA]}. | |
dd551aa1 | 3284 | |
dd551aa1 | 3285 | @item we |
e01975f9 SB |
3286 | Like @code{wa}, if @option{-mpower9-vector} and @option{-m64} are used; |
3287 | otherwise, @code{NO_REGS}. | |
dd551aa1 | 3288 | |
b4fbcb1b | 3289 | @item wn |
e01975f9 | 3290 | No register (@code{NO_REGS}). |
b4fbcb1b SL |
3291 | |
3292 | @item wr | |
e01975f9 | 3293 | Like @code{r}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. |
b4fbcb1b | 3294 | |
b4fbcb1b | 3295 | @item wx |
e01975f9 | 3296 | Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise, @code{NO_REGS}. |
b4fbcb1b | 3297 | |
99211352 | 3298 | @item wA |
e01975f9 | 3299 | Like @code{b}, if @option{-mpowerpc64} is used; otherwise, @code{NO_REGS}. |
99211352 | 3300 | |
1a3c3ee9 | 3301 | @item wB |
e01975f9 | 3302 | Signed 5-bit constant integer that can be loaded into an Altivec register. |
1a3c3ee9 | 3303 | |
b4fbcb1b SL |
3304 | @item wD |
3305 | Int constant that is the element number of the 64-bit scalar in a vector. | |
3306 | ||
50c78b9a MM |
3307 | @item wE |
3308 | Vector constant that can be loaded with the XXSPLTIB instruction. | |
3309 | ||
dd551aa1 | 3310 | @item wF |
e01975f9 | 3311 | Memory operand suitable for power8 GPR load fusion. |
dd551aa1 MM |
3312 | |
3313 | @item wL | |
e01975f9 | 3314 | Int constant that is the element number mfvsrld accesses in a vector. |
dd551aa1 | 3315 | |
50c78b9a MM |
3316 | @item wM |
3317 | Match vector constant with all 1's if the XXLORC instruction is available. | |
3318 | ||
3fd2b007 | 3319 | @item wO |
e01975f9 | 3320 | Memory operand suitable for the ISA 3.0 vector d-form instructions. |
3fd2b007 | 3321 | |
b4fbcb1b | 3322 | @item wQ |
e01975f9 | 3323 | Memory operand suitable for the load/store quad instructions. |
b4fbcb1b | 3324 | |
50c78b9a MM |
3325 | @item wS |
3326 | Vector constant that can be loaded with XXSPLTIB & sign extension. | |
3327 | ||
e01975f9 SB |
3328 | @item wY |
3329 | A memory operand for a DS-form instruction. | |
b4fbcb1b | 3330 | |
e01975f9 SB |
3331 | @item wZ |
3332 | An indexed or indirect memory operand, ignoring the bottom 4 bits. | |
3333 | @end ifset | |
b4fbcb1b SL |
3334 | |
3335 | @item I | |
e01975f9 | 3336 | A signed 16-bit constant. |
b4fbcb1b SL |
3337 | |
3338 | @item J | |
e01975f9 SB |
3339 | An unsigned 16-bit constant shifted left 16 bits (use @code{L} instead |
3340 | for @code{SImode} constants). | |
b4fbcb1b SL |
3341 | |
3342 | @item K | |
e01975f9 | 3343 | An unsigned 16-bit constant. |
b4fbcb1b SL |
3344 | |
3345 | @item L | |
e01975f9 | 3346 | A signed 16-bit constant shifted left 16 bits. |
b4fbcb1b | 3347 | |
e01975f9 | 3348 | @ifset INTERNALS |
b4fbcb1b | 3349 | @item M |
e01975f9 | 3350 | An integer constant greater than 31. |
b4fbcb1b SL |
3351 | |
3352 | @item N | |
e01975f9 | 3353 | An exact power of 2. |
b4fbcb1b SL |
3354 | |
3355 | @item O | |
e01975f9 | 3356 | The integer constant zero. |
b4fbcb1b SL |
3357 | |
3358 | @item P | |
e01975f9 SB |
3359 | A constant whose negation is a signed 16-bit constant. |
3360 | @end ifset | |
b4fbcb1b | 3361 | |
ed383d79 | 3362 | @item eI |
e01975f9 | 3363 | A signed 34-bit integer constant if prefixed instructions are supported. |
ed383d79 | 3364 | |
d730aa8a MM |
3365 | @item eP |
3366 | A scalar floating point constant or a vector constant that can be | |
3367 | loaded to a VSX register with one prefixed instruction. | |
3368 | ||
8ccd8b12 MM |
3369 | @item eQ |
3370 | An IEEE 128-bit constant that can be loaded into a VSX register with | |
3371 | the @code{lxvkq} instruction. | |
3372 | ||
e01975f9 | 3373 | @ifset INTERNALS |
b4fbcb1b | 3374 | @item G |
e01975f9 SB |
3375 | A floating point constant that can be loaded into a register with one |
3376 | instruction per word. | |
b4fbcb1b SL |
3377 | |
3378 | @item H | |
e01975f9 SB |
3379 | A floating point constant that can be loaded into a register using |
3380 | three instructions. | |
3381 | @end ifset | |
b4fbcb1b SL |
3382 | |
3383 | @item m | |
e01975f9 | 3384 | A memory operand. |
b4fbcb1b | 3385 | Normally, @code{m} does not allow addresses that update the base register. |
e01975f9 | 3386 | If the @code{<} or @code{>} constraint is also used, they are allowed and |
b4fbcb1b | 3387 | therefore on PowerPC targets in that case it is only safe |
e01975f9 | 3388 | to use @code{m<>} in an @code{asm} statement if that @code{asm} statement |
b4fbcb1b | 3389 | accesses the operand exactly once. The @code{asm} statement must also |
e01975f9 | 3390 | use @code{%U@var{<opno>}} as a placeholder for the ``update'' flag in the |
b4fbcb1b SL |
3391 | corresponding load or store instruction. For example: |
3392 | ||
3393 | @smallexample | |
3394 | asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val)); | |
3395 | @end smallexample | |
3396 | ||
3397 | is correct but: | |
3398 | ||
3399 | @smallexample | |
3400 | asm ("st %1,%0" : "=m<>" (mem) : "r" (val)); | |
3401 | @end smallexample | |
3402 | ||
3403 | is not. | |
3404 | ||
e01975f9 | 3405 | @ifset INTERNALS |
b4fbcb1b SL |
3406 | @item es |
3407 | A ``stable'' memory operand; that is, one which does not include any | |
3408 | automodification of the base register. This used to be useful when | |
e01975f9 SB |
3409 | @code{m} allowed automodification of the base register, but as those |
3410 | are now only allowed when @code{<} or @code{>} is used, @code{es} is | |
3411 | basically the same as @code{m} without @code{<} and @code{>}. | |
3412 | @end ifset | |
b4fbcb1b SL |
3413 | |
3414 | @item Q | |
e5d3611e | 3415 | A memory operand addressed by just a base register. |
b4fbcb1b | 3416 | |
e01975f9 SB |
3417 | @ifset INTERNALS |
3418 | @item Y | |
3419 | A memory operand for a DQ-form instruction. | |
3420 | @end ifset | |
3421 | ||
b4fbcb1b | 3422 | @item Z |
e01975f9 | 3423 | A memory operand accessed with indexed or indirect addressing. |
b4fbcb1b | 3424 | |
e01975f9 | 3425 | @ifset INTERNALS |
b4fbcb1b | 3426 | @item R |
e01975f9 SB |
3427 | An AIX TOC entry. |
3428 | @end ifset | |
5e426dd4 | 3429 | |
b4fbcb1b | 3430 | @item a |
e01975f9 | 3431 | An indexed or indirect address. |
5e426dd4 | 3432 | |
e01975f9 | 3433 | @ifset INTERNALS |
b4fbcb1b | 3434 | @item U |
e01975f9 | 3435 | A V.4 small data reference. |
5e426dd4 | 3436 | |
b4fbcb1b | 3437 | @item W |
e01975f9 | 3438 | A vector constant that does not require memory. |
5e426dd4 | 3439 | |
b4fbcb1b | 3440 | @item j |
e01975f9 SB |
3441 | The zero vector constant. |
3442 | @end ifset | |
5e426dd4 PK |
3443 | |
3444 | @end table | |
3445 | ||
8d2af3a2 DD |
3446 | @item PRU---@file{config/pru/constraints.md} |
3447 | @table @code | |
3448 | @item I | |
3449 | An unsigned 8-bit integer constant. | |
3450 | ||
3451 | @item J | |
3452 | An unsigned 16-bit integer constant. | |
3453 | ||
3454 | @item L | |
3455 | An unsigned 5-bit integer constant (for shift counts). | |
3456 | ||
3457 | @item T | |
3458 | A text segment (program memory) constant label. | |
3459 | ||
3460 | @item Z | |
3461 | Integer constant zero. | |
3462 | ||
3463 | @end table | |
3464 | ||
85b8555e DD |
3465 | @item RL78---@file{config/rl78/constraints.md} |
3466 | @table @code | |
3467 | ||
3468 | @item Int3 | |
3469 | An integer constant in the range 1 @dots{} 7. | |
3470 | @item Int8 | |
3471 | An integer constant in the range 0 @dots{} 255. | |
3472 | @item J | |
3473 | An integer constant in the range @minus{}255 @dots{} 0 | |
3474 | @item K | |
3475 | The integer constant 1. | |
3476 | @item L | |
3477 | The integer constant -1. | |
3478 | @item M | |
3479 | The integer constant 0. | |
3480 | @item N | |
3481 | The integer constant 2. | |
3482 | @item O | |
3483 | The integer constant -2. | |
3484 | @item P | |
3485 | An integer constant in the range 1 @dots{} 15. | |
3486 | @item Qbi | |
3487 | The built-in compare types--eq, ne, gtu, ltu, geu, and leu. | |
3488 | @item Qsc | |
3489 | The synthetic compare types--gt, lt, ge, and le. | |
3490 | @item Wab | |
3491 | A memory reference with an absolute address. | |
3492 | @item Wbc | |
3493 | A memory reference using @code{BC} as a base register, with an optional offset. | |
3494 | @item Wca | |
3495 | A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls. | |
3496 | @item Wcv | |
3497 | A memory reference using any 16-bit register pair for the address, for calls. | |
3498 | @item Wd2 | |
3499 | A memory reference using @code{DE} as a base register, with an optional offset. | |
3500 | @item Wde | |
3501 | A memory reference using @code{DE} as a base register, without any offset. | |
3502 | @item Wfr | |
3503 | Any memory reference to an address in the far address space. | |
3504 | @item Wh1 | |
3505 | A memory reference using @code{HL} as a base register, with an optional one-byte offset. | |
3506 | @item Whb | |
3507 | A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register. | |
3508 | @item Whl | |
3509 | A memory reference using @code{HL} as a base register, without any offset. | |
3510 | @item Ws1 | |
3511 | A memory reference using @code{SP} as a base register, with an optional one-byte offset. | |
3512 | @item Y | |
3513 | Any memory reference to an address in the near address space. | |
3514 | @item A | |
3515 | The @code{AX} register. | |
3516 | @item B | |
3517 | The @code{BC} register. | |
3518 | @item D | |
3519 | The @code{DE} register. | |
3520 | @item R | |
3521 | @code{A} through @code{L} registers. | |
3522 | @item S | |
3523 | The @code{SP} register. | |
3524 | @item T | |
3525 | The @code{HL} register. | |
3526 | @item Z08W | |
3527 | The 16-bit @code{R8} register. | |
3528 | @item Z10W | |
3529 | The 16-bit @code{R10} register. | |
3530 | @item Zint | |
3531 | The registers reserved for interrupts (@code{R24} to @code{R31}). | |
3532 | @item a | |
3533 | The @code{A} register. | |
3534 | @item b | |
3535 | The @code{B} register. | |
3536 | @item c | |
3537 | The @code{C} register. | |
3538 | @item d | |
3539 | The @code{D} register. | |
3540 | @item e | |
3541 | The @code{E} register. | |
3542 | @item h | |
3543 | The @code{H} register. | |
3544 | @item l | |
3545 | The @code{L} register. | |
3546 | @item v | |
3547 | The virtual registers. | |
3548 | @item w | |
3549 | The @code{PSW} register. | |
3550 | @item x | |
3551 | The @code{X} register. | |
3552 | ||
3553 | @end table | |
09cae750 PD |
3554 | |
3555 | @item RISC-V---@file{config/riscv/constraints.md} | |
3556 | @table @code | |
3557 | ||
3558 | @item f | |
a0ab54de | 3559 | A floating-point register (if available). |
09cae750 PD |
3560 | |
3561 | @item I | |
3562 | An I-type 12-bit signed immediate. | |
3563 | ||
3564 | @item J | |
3565 | Integer zero. | |
3566 | ||
3567 | @item K | |
3568 | A 5-bit unsigned immediate for CSR access instructions. | |
3569 | ||
3570 | @item A | |
3571 | An address that is held in a general-purpose register. | |
3572 | ||
18a463bb KC |
3573 | @item S |
3574 | A constraint that matches an absolute symbolic address. | |
3575 | ||
09cae750 | 3576 | @end table |
85b8555e | 3577 | |
65a324b4 NC |
3578 | @item RX---@file{config/rx/constraints.md} |
3579 | @table @code | |
3580 | @item Q | |
3581 | An address which does not involve register indirect addressing or | |
3582 | pre/post increment/decrement addressing. | |
3583 | ||
3584 | @item Symbol | |
3585 | A symbol reference. | |
3586 | ||
3587 | @item Int08 | |
3588 | A constant in the range @minus{}256 to 255, inclusive. | |
3589 | ||
3590 | @item Sint08 | |
3591 | A constant in the range @minus{}128 to 127, inclusive. | |
3592 | ||
3593 | @item Sint16 | |
3594 | A constant in the range @minus{}32768 to 32767, inclusive. | |
3595 | ||
3596 | @item Sint24 | |
3597 | A constant in the range @minus{}8388608 to 8388607, inclusive. | |
3598 | ||
3599 | @item Uint04 | |
3600 | A constant in the range 0 to 15, inclusive. | |
3601 | ||
3602 | @end table | |
3603 | ||
b4fbcb1b SL |
3604 | @item S/390 and zSeries---@file{config/s390/s390.h} |
3605 | @table @code | |
3606 | @item a | |
3607 | Address register (general purpose register except r0) | |
3608 | ||
3609 | @item c | |
3610 | Condition code register | |
3611 | ||
3612 | @item d | |
3613 | Data register (arbitrary general purpose register) | |
3614 | ||
3615 | @item f | |
3616 | Floating-point register | |
3617 | ||
3618 | @item I | |
3619 | Unsigned 8-bit constant (0--255) | |
3620 | ||
3621 | @item J | |
3622 | Unsigned 12-bit constant (0--4095) | |
3623 | ||
3624 | @item K | |
3625 | Signed 16-bit constant (@minus{}32768--32767) | |
3626 | ||
3627 | @item L | |
3628 | Value appropriate as displacement. | |
3629 | @table @code | |
3630 | @item (0..4095) | |
3631 | for short displacement | |
3632 | @item (@minus{}524288..524287) | |
3633 | for long displacement | |
3634 | @end table | |
3635 | ||
3636 | @item M | |
3637 | Constant integer with a value of 0x7fffffff. | |
3638 | ||
3639 | @item N | |
3640 | Multiple letter constraint followed by 4 parameter letters. | |
3641 | @table @code | |
3642 | @item 0..9: | |
3643 | number of the part counting from most to least significant | |
3644 | @item H,Q: | |
3645 | mode of the part | |
3646 | @item D,S,H: | |
3647 | mode of the containing operand | |
3648 | @item 0,F: | |
3649 | value of the other parts (F---all bits set) | |
3650 | @end table | |
3651 | The constraint matches if the specified part of a constant | |
3652 | has a value different from its other parts. | |
3653 | ||
3654 | @item Q | |
3655 | Memory reference without index register and with short displacement. | |
3656 | ||
3657 | @item R | |
3658 | Memory reference with index register and short displacement. | |
3659 | ||
3660 | @item S | |
3661 | Memory reference without index register but with long displacement. | |
3662 | ||
3663 | @item T | |
3664 | Memory reference with index register and long displacement. | |
3665 | ||
3666 | @item U | |
3667 | Pointer with short displacement. | |
3668 | ||
3669 | @item W | |
3670 | Pointer with long displacement. | |
3671 | ||
3672 | @item Y | |
3673 | Shift count operand. | |
3674 | ||
3675 | @end table | |
3676 | ||
03dda8e3 | 3677 | @need 1000 |
74fe790b | 3678 | @item SPARC---@file{config/sparc/sparc.h} |
03dda8e3 RK |
3679 | @table @code |
3680 | @item f | |
53e5f173 EB |
3681 | Floating-point register on the SPARC-V8 architecture and |
3682 | lower floating-point register on the SPARC-V9 architecture. | |
03dda8e3 RK |
3683 | |
3684 | @item e | |
8a36672b | 3685 | Floating-point register. It is equivalent to @samp{f} on the |
53e5f173 EB |
3686 | SPARC-V8 architecture and contains both lower and upper |
3687 | floating-point registers on the SPARC-V9 architecture. | |
03dda8e3 | 3688 | |
8a69f99f EB |
3689 | @item c |
3690 | Floating-point condition code register. | |
3691 | ||
3692 | @item d | |
8a36672b | 3693 | Lower floating-point register. It is only valid on the SPARC-V9 |
53e5f173 | 3694 | architecture when the Visual Instruction Set is available. |
8a69f99f EB |
3695 | |
3696 | @item b | |
8a36672b | 3697 | Floating-point register. It is only valid on the SPARC-V9 architecture |
53e5f173 | 3698 | when the Visual Instruction Set is available. |
8a69f99f EB |
3699 | |
3700 | @item h | |
3701 | 64-bit global or out register for the SPARC-V8+ architecture. | |
3702 | ||
923f9ded DM |
3703 | @item C |
3704 | The constant all-ones, for floating-point. | |
3705 | ||
8b98b5fd DM |
3706 | @item A |
3707 | Signed 5-bit constant | |
3708 | ||
66e62b49 KH |
3709 | @item D |
3710 | A vector constant | |
3711 | ||
03dda8e3 | 3712 | @item I |
1e5f973d | 3713 | Signed 13-bit constant |
03dda8e3 RK |
3714 | |
3715 | @item J | |
3716 | Zero | |
3717 | ||
3718 | @item K | |
1e5f973d | 3719 | 32-bit constant with the low 12 bits clear (a constant that can be |
03dda8e3 RK |
3720 | loaded with the @code{sethi} instruction) |
3721 | ||
7d6040e8 | 3722 | @item L |
923f9ded DM |
3723 | A constant in the range supported by @code{movcc} instructions (11-bit |
3724 | signed immediate) | |
7d6040e8 AO |
3725 | |
3726 | @item M | |
923f9ded DM |
3727 | A constant in the range supported by @code{movrcc} instructions (10-bit |
3728 | signed immediate) | |
7d6040e8 AO |
3729 | |
3730 | @item N | |
3731 | Same as @samp{K}, except that it verifies that bits that are not in the | |
57694e40 | 3732 | lower 32-bit range are all zero. Must be used instead of @samp{K} for |
7d6040e8 AO |
3733 | modes wider than @code{SImode} |
3734 | ||
ef0139b1 EB |
3735 | @item O |
3736 | The constant 4096 | |
3737 | ||
03dda8e3 RK |
3738 | @item G |
3739 | Floating-point zero | |
3740 | ||
3741 | @item H | |
1e5f973d | 3742 | Signed 13-bit constant, sign-extended to 32 or 64 bits |
03dda8e3 | 3743 | |
923f9ded DM |
3744 | @item P |
3745 | The constant -1 | |
3746 | ||
03dda8e3 | 3747 | @item Q |
62190128 DM |
3748 | Floating-point constant whose integral representation can |
3749 | be moved into an integer register using a single sethi | |
3750 | instruction | |
3751 | ||
3752 | @item R | |
3753 | Floating-point constant whose integral representation can | |
3754 | be moved into an integer register using a single mov | |
3755 | instruction | |
03dda8e3 RK |
3756 | |
3757 | @item S | |
62190128 DM |
3758 | Floating-point constant whose integral representation can |
3759 | be moved into an integer register using a high/lo_sum | |
3760 | instruction sequence | |
03dda8e3 RK |
3761 | |
3762 | @item T | |
3763 | Memory address aligned to an 8-byte boundary | |
3764 | ||
aaa050aa DM |
3765 | @item U |
3766 | Even register | |
3767 | ||
7a31a340 | 3768 | @item W |
c75d6010 JM |
3769 | Memory address for @samp{e} constraint registers |
3770 | ||
923f9ded DM |
3771 | @item w |
3772 | Memory address with only a base register | |
3773 | ||
c75d6010 JM |
3774 | @item Y |
3775 | Vector zero | |
7a31a340 | 3776 | |
6ca30df6 MH |
3777 | @end table |
3778 | ||
bcead286 BS |
3779 | @item TI C6X family---@file{config/c6x/constraints.md} |
3780 | @table @code | |
3781 | @item a | |
3782 | Register file A (A0--A31). | |
3783 | ||
3784 | @item b | |
3785 | Register file B (B0--B31). | |
3786 | ||
3787 | @item A | |
3788 | Predicate registers in register file A (A0--A2 on C64X and | |
3789 | higher, A1 and A2 otherwise). | |
3790 | ||
3791 | @item B | |
3792 | Predicate registers in register file B (B0--B2). | |
3793 | ||
3794 | @item C | |
3795 | A call-used register in register file B (B0--B9, B16--B31). | |
3796 | ||
3797 | @item Da | |
3798 | Register file A, excluding predicate registers (A3--A31, | |
3799 | plus A0 if not C64X or higher). | |
3800 | ||
3801 | @item Db | |
3802 | Register file B, excluding predicate registers (B3--B31). | |
3803 | ||
3804 | @item Iu4 | |
3805 | Integer constant in the range 0 @dots{} 15. | |
3806 | ||
3807 | @item Iu5 | |
3808 | Integer constant in the range 0 @dots{} 31. | |
3809 | ||
3810 | @item In5 | |
3811 | Integer constant in the range @minus{}31 @dots{} 0. | |
3812 | ||
3813 | @item Is5 | |
3814 | Integer constant in the range @minus{}16 @dots{} 15. | |
3815 | ||
3816 | @item I5x | |
3817 | Integer constant that can be the operand of an ADDA or a SUBA insn. | |
3818 | ||
3819 | @item IuB | |
3820 | Integer constant in the range 0 @dots{} 65535. | |
3821 | ||
3822 | @item IsB | |
3823 | Integer constant in the range @minus{}32768 @dots{} 32767. | |
3824 | ||
3825 | @item IsC | |
3826 | Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}. | |
3827 | ||
3828 | @item Jc | |
3829 | Integer constant that is a valid mask for the clr instruction. | |
3830 | ||
3831 | @item Js | |
3832 | Integer constant that is a valid mask for the set instruction. | |
3833 | ||
3834 | @item Q | |
3835 | Memory location with A base register. | |
3836 | ||
3837 | @item R | |
3838 | Memory location with B base register. | |
3839 | ||
3840 | @ifset INTERNALS | |
3841 | @item S0 | |
3842 | On C64x+ targets, a GP-relative small data reference. | |
3843 | ||
3844 | @item S1 | |
3845 | Any kind of @code{SYMBOL_REF}, for use in a call address. | |
3846 | ||
3847 | @item Si | |
3848 | Any kind of immediate operand, unless it matches the S0 constraint. | |
3849 | ||
3850 | @item T | |
3851 | Memory location with B base register, but not using a long offset. | |
3852 | ||
3853 | @item W | |
fd250f0d | 3854 | A memory operand with an address that cannot be used in an unaligned access. |
bcead286 BS |
3855 | |
3856 | @end ifset | |
3857 | @item Z | |
3858 | Register B14 (aka DP). | |
3859 | ||
3860 | @end table | |
3861 | ||
0969ec7d EB |
3862 | @item Visium---@file{config/visium/constraints.md} |
3863 | @table @code | |
3864 | @item b | |
3865 | EAM register @code{mdb} | |
3866 | ||
3867 | @item c | |
3868 | EAM register @code{mdc} | |
3869 | ||
3870 | @item f | |
3871 | Floating point register | |
3872 | ||
3873 | @ifset INTERNALS | |
3874 | @item k | |
3875 | Register for sibcall optimization | |
3876 | @end ifset | |
3877 | ||
3878 | @item l | |
3879 | General register, but not @code{r29}, @code{r30} and @code{r31} | |
3880 | ||
3881 | @item t | |
3882 | Register @code{r1} | |
3883 | ||
3884 | @item u | |
3885 | Register @code{r2} | |
3886 | ||
3887 | @item v | |
3888 | Register @code{r3} | |
3889 | ||
3890 | @item G | |
3891 | Floating-point constant 0.0 | |
3892 | ||
3893 | @item J | |
3894 | Integer constant in the range 0 .. 65535 (16-bit immediate) | |
3895 | ||
3896 | @item K | |
3897 | Integer constant in the range 1 .. 31 (5-bit immediate) | |
3898 | ||
3899 | @item L | |
3900 | Integer constant in the range @minus{}65535 .. @minus{}1 (16-bit negative immediate) | |
3901 | ||
3902 | @item M | |
3903 | Integer constant @minus{}1 | |
3904 | ||
3905 | @item O | |
3906 | Integer constant 0 | |
3907 | ||
3908 | @item P | |
3909 | Integer constant 32 | |
3910 | @end table | |
3911 | ||
b4fbcb1b SL |
3912 | @item x86 family---@file{config/i386/constraints.md} |
3913 | @table @code | |
3914 | @item R | |
3915 | Legacy register---the eight integer registers available on all | |
3916 | i386 processors (@code{a}, @code{b}, @code{c}, @code{d}, | |
3917 | @code{si}, @code{di}, @code{bp}, @code{sp}). | |
3918 | ||
3919 | @item q | |
3920 | Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a}, | |
3921 | @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register. | |
3922 | ||
3923 | @item Q | |
3924 | Any register accessible as @code{@var{r}h}: @code{a}, @code{b}, | |
3925 | @code{c}, and @code{d}. | |
3926 | ||
3927 | @ifset INTERNALS | |
3928 | @item l | |
3929 | Any register that can be used as the index in a base+index memory | |
3930 | access: that is, any general register except the stack pointer. | |
3931 | @end ifset | |
3932 | ||
3933 | @item a | |
3934 | The @code{a} register. | |
3935 | ||
3936 | @item b | |
3937 | The @code{b} register. | |
3938 | ||
3939 | @item c | |
3940 | The @code{c} register. | |
3941 | ||
3942 | @item d | |
3943 | The @code{d} register. | |
3944 | ||
3945 | @item S | |
3946 | The @code{si} register. | |
3947 | ||
3948 | @item D | |
3949 | The @code{di} register. | |
3950 | ||
3951 | @item A | |
3952 | The @code{a} and @code{d} registers. This class is used for instructions | |
3953 | that return double word results in the @code{ax:dx} register pair. Single | |
3954 | word values will be allocated either in @code{ax} or @code{dx}. | |
3955 | For example on i386 the following implements @code{rdtsc}: | |
3956 | ||
3957 | @smallexample | |
3958 | unsigned long long rdtsc (void) | |
3959 | @{ | |
3960 | unsigned long long tick; | |
3961 | __asm__ __volatile__("rdtsc":"=A"(tick)); | |
3962 | return tick; | |
3963 | @} | |
3964 | @end smallexample | |
3965 | ||
3966 | This is not correct on x86-64 as it would allocate tick in either @code{ax} | |
3967 | or @code{dx}. You have to use the following variant instead: | |
3968 | ||
3969 | @smallexample | |
3970 | unsigned long long rdtsc (void) | |
3971 | @{ | |
3972 | unsigned int tickl, tickh; | |
3973 | __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh)); | |
3974 | return ((unsigned long long)tickh << 32)|tickl; | |
3975 | @} | |
3976 | @end smallexample | |
3977 | ||
de3fb1a6 SP |
3978 | @item U |
3979 | The call-clobbered integer registers. | |
b4fbcb1b SL |
3980 | |
3981 | @item f | |
3982 | Any 80387 floating-point (stack) register. | |
3983 | ||
3984 | @item t | |
3985 | Top of 80387 floating-point stack (@code{%st(0)}). | |
3986 | ||
3987 | @item u | |
3988 | Second from top of 80387 floating-point stack (@code{%st(1)}). | |
3989 | ||
de3fb1a6 SP |
3990 | @ifset INTERNALS |
3991 | @item Yk | |
630ba2fd | 3992 | Any mask register that can be used as a predicate, i.e.@: @code{k1-k7}. |
de3fb1a6 SP |
3993 | |
3994 | @item k | |
3995 | Any mask register. | |
3996 | @end ifset | |
3997 | ||
b4fbcb1b SL |
3998 | @item y |
3999 | Any MMX register. | |
4000 | ||
4001 | @item x | |
4002 | Any SSE register. | |
4003 | ||
de3fb1a6 SP |
4004 | @item v |
4005 | Any EVEX encodable SSE register (@code{%xmm0-%xmm31}). | |
4006 | ||
4007 | @ifset INTERNALS | |
4008 | @item w | |
4009 | Any bound register. | |
4010 | @end ifset | |
4011 | ||
b4fbcb1b SL |
4012 | @item Yz |
4013 | First SSE register (@code{%xmm0}). | |
4014 | ||
4015 | @ifset INTERNALS | |
b4fbcb1b SL |
4016 | @item Yi |
4017 | Any SSE register, when SSE2 and inter-unit moves are enabled. | |
4018 | ||
de3fb1a6 SP |
4019 | @item Yj |
4020 | Any SSE register, when SSE2 and inter-unit moves from vector registers are enabled. | |
4021 | ||
b4fbcb1b SL |
4022 | @item Ym |
4023 | Any MMX register, when inter-unit moves are enabled. | |
de3fb1a6 SP |
4024 | |
4025 | @item Yn | |
4026 | Any MMX register, when inter-unit moves from vector registers are enabled. | |
4027 | ||
4028 | @item Yp | |
4029 | Any integer register when @code{TARGET_PARTIAL_REG_STALL} is disabled. | |
4030 | ||
4031 | @item Ya | |
4032 | Any integer register when zero extensions with @code{AND} are disabled. | |
4033 | ||
4034 | @item Yb | |
4035 | Any register that can be used as the GOT base when calling@* | |
4036 | @code{___tls_get_addr}: that is, any general register except @code{a} | |
4037 | and @code{sp} registers, for @option{-fno-plt} if linker supports it. | |
4038 | Otherwise, @code{b} register. | |
4039 | ||
4040 | @item Yf | |
4041 | Any x87 register when 80387 floating-point arithmetic is enabled. | |
4042 | ||
4043 | @item Yr | |
4044 | Lower SSE register when avoiding REX prefix and all SSE registers otherwise. | |
4045 | ||
4046 | @item Yv | |
4047 | For AVX512VL, any EVEX-encodable SSE register (@code{%xmm0-%xmm31}), | |
4048 | otherwise any SSE register. | |
4049 | ||
4050 | @item Yh | |
4051 | Any EVEX-encodable SSE register, that has number factor of four. | |
4052 | ||
4053 | @item Bf | |
4054 | Flags register operand. | |
4055 | ||
4056 | @item Bg | |
4057 | GOT memory operand. | |
4058 | ||
4059 | @item Bm | |
4060 | Vector memory operand. | |
4061 | ||
4062 | @item Bc | |
4063 | Constant memory operand. | |
4064 | ||
4065 | @item Bn | |
4066 | Memory operand without REX prefix. | |
4067 | ||
4068 | @item Bs | |
4069 | Sibcall memory operand. | |
4070 | ||
4071 | @item Bw | |
4072 | Call memory operand. | |
4073 | ||
4074 | @item Bz | |
4075 | Constant call address operand. | |
4076 | ||
4077 | @item BC | |
4078 | SSE constant -1 operand. | |
b4fbcb1b SL |
4079 | @end ifset |
4080 | ||
4081 | @item I | |
4082 | Integer constant in the range 0 @dots{} 31, for 32-bit shifts. | |
4083 | ||
4084 | @item J | |
4085 | Integer constant in the range 0 @dots{} 63, for 64-bit shifts. | |
4086 | ||
4087 | @item K | |
4088 | Signed 8-bit integer constant. | |
4089 | ||
4090 | @item L | |
4091 | @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move. | |
4092 | ||
4093 | @item M | |
4094 | 0, 1, 2, or 3 (shifts for the @code{lea} instruction). | |
4095 | ||
4096 | @item N | |
4097 | Unsigned 8-bit integer constant (for @code{in} and @code{out} | |
4098 | instructions). | |
4099 | ||
4100 | @ifset INTERNALS | |
4101 | @item O | |
4102 | Integer constant in the range 0 @dots{} 127, for 128-bit shifts. | |
4103 | @end ifset | |
4104 | ||
4105 | @item G | |
4106 | Standard 80387 floating point constant. | |
4107 | ||
4108 | @item C | |
aec0b19e | 4109 | SSE constant zero operand. |
b4fbcb1b SL |
4110 | |
4111 | @item e | |
4112 | 32-bit signed integer constant, or a symbolic reference known | |
4113 | to fit that range (for immediate operands in sign-extending x86-64 | |
4114 | instructions). | |
4115 | ||
de3fb1a6 SP |
4116 | @item We |
4117 | 32-bit signed integer constant, or a symbolic reference known | |
4118 | to fit that range (for sign-extending conversion operations that | |
4119 | require non-@code{VOIDmode} immediate operands). | |
4120 | ||
4121 | @item Wz | |
4122 | 32-bit unsigned integer constant, or a symbolic reference known | |
4123 | to fit that range (for zero-extending conversion operations that | |
4124 | require non-@code{VOIDmode} immediate operands). | |
4125 | ||
4126 | @item Wd | |
4127 | 128-bit integer constant where both the high and low 64-bit word | |
4128 | satisfy the @code{e} constraint. | |
4129 | ||
b4fbcb1b SL |
4130 | @item Z |
4131 | 32-bit unsigned integer constant, or a symbolic reference known | |
4132 | to fit that range (for immediate operands in zero-extending x86-64 | |
4133 | instructions). | |
4134 | ||
de3fb1a6 SP |
4135 | @item Tv |
4136 | VSIB address operand. | |
4137 | ||
4138 | @item Ts | |
4139 | Address operand without segment register. | |
4140 | ||
b4fbcb1b SL |
4141 | @end table |
4142 | ||
4143 | @item Xstormy16---@file{config/stormy16/stormy16.h} | |
4144 | @table @code | |
4145 | @item a | |
4146 | Register r0. | |
4147 | ||
4148 | @item b | |
4149 | Register r1. | |
4150 | ||
4151 | @item c | |
4152 | Register r2. | |
4153 | ||
4154 | @item d | |
4155 | Register r8. | |
4156 | ||
4157 | @item e | |
4158 | Registers r0 through r7. | |
4159 | ||
4160 | @item t | |
4161 | Registers r0 and r1. | |
4162 | ||
4163 | @item y | |
4164 | The carry register. | |
4165 | ||
4166 | @item z | |
4167 | Registers r8 and r9. | |
4168 | ||
4169 | @item I | |
4170 | A constant between 0 and 3 inclusive. | |
4171 | ||
4172 | @item J | |
4173 | A constant that has exactly one bit set. | |
4174 | ||
4175 | @item K | |
4176 | A constant that has exactly one bit clear. | |
4177 | ||
4178 | @item L | |
4179 | A constant between 0 and 255 inclusive. | |
4180 | ||
4181 | @item M | |
4182 | A constant between @minus{}255 and 0 inclusive. | |
4183 | ||
4184 | @item N | |
4185 | A constant between @minus{}3 and 0 inclusive. | |
4186 | ||
4187 | @item O | |
4188 | A constant between 1 and 4 inclusive. | |
4189 | ||
4190 | @item P | |
4191 | A constant between @minus{}4 and @minus{}1 inclusive. | |
4192 | ||
4193 | @item Q | |
4194 | A memory reference that is a stack push. | |
4195 | ||
4196 | @item R | |
4197 | A memory reference that is a stack pop. | |
4198 | ||
4199 | @item S | |
4200 | A memory reference that refers to a constant address of known value. | |
4201 | ||
4202 | @item T | |
4203 | The register indicated by Rx (not implemented yet). | |
4204 | ||
4205 | @item U | |
4206 | A constant that is not between 2 and 15 inclusive. | |
4207 | ||
4208 | @item Z | |
4209 | The constant 0. | |
4210 | ||
4211 | @end table | |
4212 | ||
887af464 | 4213 | @item Xtensa---@file{config/xtensa/constraints.md} |
03984308 BW |
4214 | @table @code |
4215 | @item a | |
4216 | General-purpose 32-bit register | |
4217 | ||
4218 | @item b | |
4219 | One-bit boolean register | |
4220 | ||
4221 | @item A | |
4222 | MAC16 40-bit accumulator register | |
4223 | ||
4224 | @item I | |
4225 | Signed 12-bit integer constant, for use in MOVI instructions | |
4226 | ||
4227 | @item J | |
4228 | Signed 8-bit integer constant, for use in ADDI instructions | |
4229 | ||
4230 | @item K | |
4231 | Integer constant valid for BccI instructions | |
4232 | ||
4233 | @item L | |
4234 | Unsigned constant valid for BccUI instructions | |
4235 | ||
4236 | @end table | |
4237 | ||
03dda8e3 RK |
4238 | @end table |
4239 | ||
7ac28727 AK |
4240 | @ifset INTERNALS |
4241 | @node Disable Insn Alternatives | |
4242 | @subsection Disable insn alternatives using the @code{enabled} attribute | |
4243 | @cindex enabled | |
4244 | ||
9840b2fa RS |
4245 | There are three insn attributes that may be used to selectively disable |
4246 | instruction alternatives: | |
7ac28727 | 4247 | |
9840b2fa RS |
4248 | @table @code |
4249 | @item enabled | |
4250 | Says whether an alternative is available on the current subtarget. | |
7ac28727 | 4251 | |
9840b2fa RS |
4252 | @item preferred_for_size |
4253 | Says whether an enabled alternative should be used in code that is | |
4254 | optimized for size. | |
7ac28727 | 4255 | |
9840b2fa RS |
4256 | @item preferred_for_speed |
4257 | Says whether an enabled alternative should be used in code that is | |
4258 | optimized for speed. | |
4259 | @end table | |
4260 | ||
4261 | All these attributes should use @code{(const_int 1)} to allow an alternative | |
4262 | or @code{(const_int 0)} to disallow it. The attributes must be a static | |
4263 | property of the subtarget; they cannot for example depend on the | |
4264 | current operands, on the current optimization level, on the location | |
4265 | of the insn within the body of a loop, on whether register allocation | |
4266 | has finished, or on the current compiler pass. | |
4267 | ||
4268 | The @code{enabled} attribute is a correctness property. It tells GCC to act | |
4269 | as though the disabled alternatives were never defined in the first place. | |
4270 | This is useful when adding new instructions to an existing pattern in | |
4271 | cases where the new instructions are only available for certain cpu | |
4272 | architecture levels (typically mapped to the @code{-march=} command-line | |
4273 | option). | |
4274 | ||
4275 | In contrast, the @code{preferred_for_size} and @code{preferred_for_speed} | |
4276 | attributes are strong optimization hints rather than correctness properties. | |
4277 | @code{preferred_for_size} tells GCC which alternatives to consider when | |
4278 | adding or modifying an instruction that GCC wants to optimize for size. | |
4279 | @code{preferred_for_speed} does the same thing for speed. Note that things | |
4280 | like code motion can lead to cases where code optimized for size uses | |
4281 | alternatives that are not preferred for size, and similarly for speed. | |
4282 | ||
4283 | Although @code{define_insn}s can in principle specify the @code{enabled} | |
4284 | attribute directly, it is often clearer to have subsiduary attributes | |
4285 | for each architectural feature of interest. The @code{define_insn}s | |
4286 | can then use these subsiduary attributes to say which alternatives | |
4287 | require which features. The example below does this for @code{cpu_facility}. | |
7ac28727 AK |
4288 | |
4289 | E.g. the following two patterns could easily be merged using the @code{enabled} | |
4290 | attribute: | |
4291 | ||
4292 | @smallexample | |
4293 | ||
4294 | (define_insn "*movdi_old" | |
4295 | [(set (match_operand:DI 0 "register_operand" "=d") | |
4296 | (match_operand:DI 1 "register_operand" " d"))] | |
4297 | "!TARGET_NEW" | |
4298 | "lgr %0,%1") | |
4299 | ||
4300 | (define_insn "*movdi_new" | |
4301 | [(set (match_operand:DI 0 "register_operand" "=d,f,d") | |
4302 | (match_operand:DI 1 "register_operand" " d,d,f"))] | |
4303 | "TARGET_NEW" | |
4304 | "@@ | |
4305 | lgr %0,%1 | |
4306 | ldgr %0,%1 | |
4307 | lgdr %0,%1") | |
4308 | ||
4309 | @end smallexample | |
4310 | ||
4311 | to: | |
4312 | ||
4313 | @smallexample | |
4314 | ||
4315 | (define_insn "*movdi_combined" | |
4316 | [(set (match_operand:DI 0 "register_operand" "=d,f,d") | |
4317 | (match_operand:DI 1 "register_operand" " d,d,f"))] | |
4318 | "" | |
4319 | "@@ | |
4320 | lgr %0,%1 | |
4321 | ldgr %0,%1 | |
4322 | lgdr %0,%1" | |
4323 | [(set_attr "cpu_facility" "*,new,new")]) | |
4324 | ||
4325 | @end smallexample | |
4326 | ||
4327 | with the @code{enabled} attribute defined like this: | |
4328 | ||
4329 | @smallexample | |
4330 | ||
4331 | (define_attr "cpu_facility" "standard,new" (const_string "standard")) | |
4332 | ||
4333 | (define_attr "enabled" "" | |
4334 | (cond [(eq_attr "cpu_facility" "standard") (const_int 1) | |
4335 | (and (eq_attr "cpu_facility" "new") | |
4336 | (ne (symbol_ref "TARGET_NEW") (const_int 0))) | |
4337 | (const_int 1)] | |
4338 | (const_int 0))) | |
4339 | ||
4340 | @end smallexample | |
4341 | ||
4342 | @end ifset | |
4343 | ||
03dda8e3 | 4344 | @ifset INTERNALS |
f38840db ZW |
4345 | @node Define Constraints |
4346 | @subsection Defining Machine-Specific Constraints | |
4347 | @cindex defining constraints | |
4348 | @cindex constraints, defining | |
4349 | ||
4350 | Machine-specific constraints fall into two categories: register and | |
4351 | non-register constraints. Within the latter category, constraints | |
4352 | which allow subsets of all possible memory or address operands should | |
4353 | be specially marked, to give @code{reload} more information. | |
4354 | ||
4355 | Machine-specific constraints can be given names of arbitrary length, | |
4356 | but they must be entirely composed of letters, digits, underscores | |
4357 | (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they | |
ff2ce160 | 4358 | must begin with a letter or underscore. |
f38840db ZW |
4359 | |
4360 | In order to avoid ambiguity in operand constraint strings, no | |
4361 | constraint can have a name that begins with any other constraint's | |
4362 | name. For example, if @code{x} is defined as a constraint name, | |
4363 | @code{xy} may not be, and vice versa. As a consequence of this rule, | |
4364 | no constraint may begin with one of the generic constraint letters: | |
4365 | @samp{E F V X g i m n o p r s}. | |
4366 | ||
4367 | Register constraints correspond directly to register classes. | |
4368 | @xref{Register Classes}. There is thus not much flexibility in their | |
4369 | definitions. | |
4370 | ||
4371 | @deffn {MD Expression} define_register_constraint name regclass docstring | |
4372 | All three arguments are string constants. | |
4373 | @var{name} is the name of the constraint, as it will appear in | |
5be527d0 RG |
4374 | @code{match_operand} expressions. If @var{name} is a multi-letter |
4375 | constraint its length shall be the same for all constraints starting | |
4376 | with the same letter. @var{regclass} can be either the | |
f38840db ZW |
4377 | name of the corresponding register class (@pxref{Register Classes}), |
4378 | or a C expression which evaluates to the appropriate register class. | |
4379 | If it is an expression, it must have no side effects, and it cannot | |
4380 | look at the operand. The usual use of expressions is to map some | |
4381 | register constraints to @code{NO_REGS} when the register class | |
4382 | is not available on a given subarchitecture. | |
4383 | ||
4384 | @var{docstring} is a sentence documenting the meaning of the | |
4385 | constraint. Docstrings are explained further below. | |
4386 | @end deffn | |
4387 | ||
4388 | Non-register constraints are more like predicates: the constraint | |
527a3750 | 4389 | definition gives a boolean expression which indicates whether the |
f38840db ZW |
4390 | constraint matches. |
4391 | ||
4392 | @deffn {MD Expression} define_constraint name docstring exp | |
4393 | The @var{name} and @var{docstring} arguments are the same as for | |
4394 | @code{define_register_constraint}, but note that the docstring comes | |
4395 | immediately after the name for these expressions. @var{exp} is an RTL | |
4396 | expression, obeying the same rules as the RTL expressions in predicate | |
4397 | definitions. @xref{Defining Predicates}, for details. If it | |
4398 | evaluates true, the constraint matches; if it evaluates false, it | |
4399 | doesn't. Constraint expressions should indicate which RTL codes they | |
4400 | might match, just like predicate expressions. | |
4401 | ||
4402 | @code{match_test} C expressions have access to the | |
4403 | following variables: | |
4404 | ||
4405 | @table @var | |
4406 | @item op | |
4407 | The RTL object defining the operand. | |
4408 | @item mode | |
4409 | The machine mode of @var{op}. | |
4410 | @item ival | |
4411 | @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}. | |
4412 | @item hval | |
4413 | @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer | |
4414 | @code{const_double}. | |
4415 | @item lval | |
4416 | @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer | |
4417 | @code{const_double}. | |
4418 | @item rval | |
4419 | @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point | |
3fa1b0e5 | 4420 | @code{const_double}. |
f38840db ZW |
4421 | @end table |
4422 | ||
4423 | The @var{*val} variables should only be used once another piece of the | |
4424 | expression has verified that @var{op} is the appropriate kind of RTL | |
4425 | object. | |
4426 | @end deffn | |
4427 | ||
4428 | Most non-register constraints should be defined with | |
4429 | @code{define_constraint}. The remaining two definition expressions | |
4430 | are only appropriate for constraints that should be handled specially | |
4431 | by @code{reload} if they fail to match. | |
4432 | ||
4433 | @deffn {MD Expression} define_memory_constraint name docstring exp | |
4434 | Use this expression for constraints that match a subset of all memory | |
4435 | operands: that is, @code{reload} can make them match by converting the | |
4436 | operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a | |
4437 | base register (from the register class specified by | |
4438 | @code{BASE_REG_CLASS}, @pxref{Register Classes}). | |
4439 | ||
4440 | For example, on the S/390, some instructions do not accept arbitrary | |
4441 | memory references, but only those that do not make use of an index | |
4442 | register. The constraint letter @samp{Q} is defined to represent a | |
4443 | memory address of this type. If @samp{Q} is defined with | |
4444 | @code{define_memory_constraint}, a @samp{Q} constraint can handle any | |
4445 | memory operand, because @code{reload} knows it can simply copy the | |
4446 | memory address into a base register if required. This is analogous to | |
e4ae5e77 | 4447 | the way an @samp{o} constraint can handle any memory operand. |
f38840db ZW |
4448 | |
4449 | The syntax and semantics are otherwise identical to | |
4450 | @code{define_constraint}. | |
4451 | @end deffn | |
4452 | ||
9eb1ca69 VM |
4453 | @deffn {MD Expression} define_special_memory_constraint name docstring exp |
4454 | Use this expression for constraints that match a subset of all memory | |
67914693 | 4455 | operands: that is, @code{reload} cannot make them match by reloading |
9eb1ca69 VM |
4456 | the address as it is described for @code{define_memory_constraint} or |
4457 | such address reload is undesirable with the performance point of view. | |
4458 | ||
4459 | For example, @code{define_special_memory_constraint} can be useful if | |
4460 | specifically aligned memory is necessary or desirable for some insn | |
4461 | operand. | |
4462 | ||
4463 | The syntax and semantics are otherwise identical to | |
02f2dc44 VM |
4464 | @code{define_memory_constraint}. |
4465 | @end deffn | |
4466 | ||
4467 | @deffn {MD Expression} define_relaxed_memory_constraint name docstring exp | |
4468 | The test expression in a @code{define_memory_constraint} can assume | |
4469 | that @code{TARGET_LEGITIMATE_ADDRESS_P} holds for the address inside | |
4470 | a @code{mem} rtx and so it does not need to test this condition itself. | |
4471 | In other words, a @code{define_memory_constraint} test of the form: | |
4472 | ||
4473 | @smallexample | |
4474 | (match_test "mem") | |
4475 | @end smallexample | |
4476 | ||
4477 | is enough to test whether an rtx is a @code{mem} @emph{and} whether | |
4478 | its address satisfies @code{TARGET_MEM_CONSTRAINT} (which is usually | |
4479 | @samp{'m'}). Thus the conditions imposed by a @code{define_memory_constraint} | |
4480 | always apply on top of the conditions imposed by @code{TARGET_MEM_CONSTRAINT}. | |
4481 | ||
4482 | However, it is sometimes useful to define memory constraints that allow | |
4483 | addresses beyond those accepted by @code{TARGET_LEGITIMATE_ADDRESS_P}. | |
4484 | @code{define_relaxed_memory_constraint} exists for this case. | |
4485 | The test expression in a @code{define_relaxed_memory_constraint} is | |
4486 | applied with no preconditions, so that the expression can determine | |
4487 | ``from scratch'' exactly which addresses are valid and which are not. | |
4488 | ||
4489 | The syntax and semantics are otherwise identical to | |
4490 | @code{define_memory_constraint}. | |
9eb1ca69 VM |
4491 | @end deffn |
4492 | ||
f38840db ZW |
4493 | @deffn {MD Expression} define_address_constraint name docstring exp |
4494 | Use this expression for constraints that match a subset of all address | |
4495 | operands: that is, @code{reload} can make the constraint match by | |
4496 | converting the operand to the form @samp{@w{(reg @var{X})}}, again | |
4497 | with @var{X} a base register. | |
4498 | ||
4499 | Constraints defined with @code{define_address_constraint} can only be | |
4500 | used with the @code{address_operand} predicate, or machine-specific | |
4501 | predicates that work the same way. They are treated analogously to | |
4502 | the generic @samp{p} constraint. | |
4503 | ||
4504 | The syntax and semantics are otherwise identical to | |
4505 | @code{define_constraint}. | |
4506 | @end deffn | |
4507 | ||
4508 | For historical reasons, names beginning with the letters @samp{G H} | |
4509 | are reserved for constraints that match only @code{const_double}s, and | |
4510 | names beginning with the letters @samp{I J K L M N O P} are reserved | |
4511 | for constraints that match only @code{const_int}s. This may change in | |
4512 | the future. For the time being, constraints with these names must be | |
4513 | written in a stylized form, so that @code{genpreds} can tell you did | |
4514 | it correctly: | |
4515 | ||
4516 | @smallexample | |
4517 | @group | |
4518 | (define_constraint "[@var{GHIJKLMNOP}]@dots{}" | |
4519 | "@var{doc}@dots{}" | |
4520 | (and (match_code "const_int") ; @r{@code{const_double} for G/H} | |
4521 | @var{condition}@dots{})) ; @r{usually a @code{match_test}} | |
4522 | @end group | |
4523 | @end smallexample | |
4524 | @c the semicolons line up in the formatted manual | |
4525 | ||
4526 | It is fine to use names beginning with other letters for constraints | |
4527 | that match @code{const_double}s or @code{const_int}s. | |
4528 | ||
4529 | Each docstring in a constraint definition should be one or more complete | |
4530 | sentences, marked up in Texinfo format. @emph{They are currently unused.} | |
4531 | In the future they will be copied into the GCC manual, in @ref{Machine | |
4532 | Constraints}, replacing the hand-maintained tables currently found in | |
4533 | that section. Also, in the future the compiler may use this to give | |
4534 | more helpful diagnostics when poor choice of @code{asm} constraints | |
4535 | causes a reload failure. | |
4536 | ||
4537 | If you put the pseudo-Texinfo directive @samp{@@internal} at the | |
4538 | beginning of a docstring, then (in the future) it will appear only in | |
4539 | the internals manual's version of the machine-specific constraint tables. | |
4540 | Use this for constraints that should not appear in @code{asm} statements. | |
4541 | ||
4542 | @node C Constraint Interface | |
4543 | @subsection Testing constraints from C | |
4544 | @cindex testing constraints | |
4545 | @cindex constraints, testing | |
4546 | ||
4547 | It is occasionally useful to test a constraint from C code rather than | |
4548 | implicitly via the constraint string in a @code{match_operand}. The | |
4549 | generated file @file{tm_p.h} declares a few interfaces for working | |
8677664e RS |
4550 | with constraints. At present these are defined for all constraints |
4551 | except @code{g} (which is equivalent to @code{general_operand}). | |
f38840db ZW |
4552 | |
4553 | Some valid constraint names are not valid C identifiers, so there is a | |
4554 | mangling scheme for referring to them from C@. Constraint names that | |
4555 | do not contain angle brackets or underscores are left unchanged. | |
4556 | Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and | |
4557 | each @samp{>} with @samp{_g}. Here are some examples: | |
4558 | ||
4559 | @c the @c's prevent double blank lines in the printed manual. | |
4560 | @example | |
4561 | @multitable {Original} {Mangled} | |
cccb0908 | 4562 | @item @strong{Original} @tab @strong{Mangled} @c |
f38840db ZW |
4563 | @item @code{x} @tab @code{x} @c |
4564 | @item @code{P42x} @tab @code{P42x} @c | |
4565 | @item @code{P4_x} @tab @code{P4__x} @c | |
4566 | @item @code{P4>x} @tab @code{P4_gx} @c | |
4567 | @item @code{P4>>} @tab @code{P4_g_g} @c | |
4568 | @item @code{P4_g>} @tab @code{P4__g_g} @c | |
4569 | @end multitable | |
4570 | @end example | |
4571 | ||
4572 | Throughout this section, the variable @var{c} is either a constraint | |
4573 | in the abstract sense, or a constant from @code{enum constraint_num}; | |
4574 | the variable @var{m} is a mangled constraint name (usually as part of | |
4575 | a larger identifier). | |
4576 | ||
4577 | @deftp Enum constraint_num | |
8677664e | 4578 | For each constraint except @code{g}, there is a corresponding |
f38840db ZW |
4579 | enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the |
4580 | constraint. Functions that take an @code{enum constraint_num} as an | |
4581 | argument expect one of these constants. | |
f38840db ZW |
4582 | @end deftp |
4583 | ||
4584 | @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp}) | |
8677664e | 4585 | For each non-register constraint @var{m} except @code{g}, there is |
f38840db ZW |
4586 | one of these functions; it returns @code{true} if @var{exp} satisfies the |
4587 | constraint. These functions are only visible if @file{rtl.h} was included | |
4588 | before @file{tm_p.h}. | |
4589 | @end deftypefun | |
4590 | ||
4591 | @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c}) | |
4592 | Like the @code{satisfies_constraint_@var{m}} functions, but the | |
4593 | constraint to test is given as an argument, @var{c}. If @var{c} | |
4594 | specifies a register constraint, this function will always return | |
4595 | @code{false}. | |
4596 | @end deftypefun | |
4597 | ||
2aeedf58 | 4598 | @deftypefun {enum reg_class} reg_class_for_constraint (enum constraint_num @var{c}) |
f38840db ZW |
4599 | Returns the register class associated with @var{c}. If @var{c} is not |
4600 | a register constraint, or those registers are not available for the | |
4601 | currently selected subtarget, returns @code{NO_REGS}. | |
4602 | @end deftypefun | |
4603 | ||
4604 | Here is an example use of @code{satisfies_constraint_@var{m}}. In | |
4605 | peephole optimizations (@pxref{Peephole Definitions}), operand | |
4606 | constraint strings are ignored, so if there are relevant constraints, | |
4607 | they must be tested in the C condition. In the example, the | |
4608 | optimization is applied if operand 2 does @emph{not} satisfy the | |
4609 | @samp{K} constraint. (This is a simplified version of a peephole | |
4610 | definition from the i386 machine description.) | |
4611 | ||
4612 | @smallexample | |
4613 | (define_peephole2 | |
4614 | [(match_scratch:SI 3 "r") | |
4615 | (set (match_operand:SI 0 "register_operand" "") | |
6ccde948 RW |
4616 | (mult:SI (match_operand:SI 1 "memory_operand" "") |
4617 | (match_operand:SI 2 "immediate_operand" "")))] | |
f38840db ZW |
4618 | |
4619 | "!satisfies_constraint_K (operands[2])" | |
4620 | ||
4621 | [(set (match_dup 3) (match_dup 1)) | |
4622 | (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))] | |
4623 | ||
4624 | "") | |
4625 | @end smallexample | |
4626 | ||
03dda8e3 RK |
4627 | @node Standard Names |
4628 | @section Standard Pattern Names For Generation | |
4629 | @cindex standard pattern names | |
4630 | @cindex pattern names | |
4631 | @cindex names, pattern | |
4632 | ||
4633 | Here is a table of the instruction names that are meaningful in the RTL | |
4634 | generation pass of the compiler. Giving one of these names to an | |
4635 | instruction pattern tells the RTL generation pass that it can use the | |
556e0f21 | 4636 | pattern to accomplish a certain task. |
03dda8e3 RK |
4637 | |
4638 | @table @asis | |
4639 | @cindex @code{mov@var{m}} instruction pattern | |
4640 | @item @samp{mov@var{m}} | |
4bd0bee9 | 4641 | Here @var{m} stands for a two-letter machine mode name, in lowercase. |
03dda8e3 RK |
4642 | This instruction pattern moves data with that machine mode from operand |
4643 | 1 to operand 0. For example, @samp{movsi} moves full-word data. | |
4644 | ||
4645 | If operand 0 is a @code{subreg} with mode @var{m} of a register whose | |
4646 | own mode is wider than @var{m}, the effect of this instruction is | |
4647 | to store the specified value in the part of the register that corresponds | |
8feb4e28 JL |
4648 | to mode @var{m}. Bits outside of @var{m}, but which are within the |
4649 | same target word as the @code{subreg} are undefined. Bits which are | |
4650 | outside the target word are left unchanged. | |
03dda8e3 RK |
4651 | |
4652 | This class of patterns is special in several ways. First of all, each | |
65945ec1 HPN |
4653 | of these names up to and including full word size @emph{must} be defined, |
4654 | because there is no other way to copy a datum from one place to another. | |
4655 | If there are patterns accepting operands in larger modes, | |
4656 | @samp{mov@var{m}} must be defined for integer modes of those sizes. | |
03dda8e3 RK |
4657 | |
4658 | Second, these patterns are not used solely in the RTL generation pass. | |
4659 | Even the reload pass can generate move insns to copy values from stack | |
4660 | slots into temporary registers. When it does so, one of the operands is | |
4661 | a hard register and the other is an operand that can need to be reloaded | |
4662 | into a register. | |
4663 | ||
4664 | @findex force_reg | |
4665 | Therefore, when given such a pair of operands, the pattern must generate | |
4666 | RTL which needs no reloading and needs no temporary registers---no | |
4667 | registers other than the operands. For example, if you support the | |
4668 | pattern with a @code{define_expand}, then in such a case the | |
4669 | @code{define_expand} mustn't call @code{force_reg} or any other such | |
4670 | function which might generate new pseudo registers. | |
4671 | ||
4672 | This requirement exists even for subword modes on a RISC machine where | |
4673 | fetching those modes from memory normally requires several insns and | |
39ed8974 | 4674 | some temporary registers. |
03dda8e3 RK |
4675 | |
4676 | @findex change_address | |
4677 | During reload a memory reference with an invalid address may be passed | |
4678 | as an operand. Such an address will be replaced with a valid address | |
4679 | later in the reload pass. In this case, nothing may be done with the | |
4680 | address except to use it as it stands. If it is copied, it will not be | |
4681 | replaced with a valid address. No attempt should be made to make such | |
4682 | an address into a valid address and no routine (such as | |
4683 | @code{change_address}) that will do so may be called. Note that | |
4684 | @code{general_operand} will fail when applied to such an address. | |
4685 | ||
4686 | @findex reload_in_progress | |
4687 | The global variable @code{reload_in_progress} (which must be explicitly | |
4688 | declared if required) can be used to determine whether such special | |
4689 | handling is required. | |
4690 | ||
4691 | The variety of operands that have reloads depends on the rest of the | |
4692 | machine description, but typically on a RISC machine these can only be | |
4693 | pseudo registers that did not get hard registers, while on other | |
4694 | machines explicit memory references will get optional reloads. | |
4695 | ||
4696 | If a scratch register is required to move an object to or from memory, | |
f1db3576 JL |
4697 | it can be allocated using @code{gen_reg_rtx} prior to life analysis. |
4698 | ||
9c34dbbf | 4699 | If there are cases which need scratch registers during or after reload, |
8a99f6f9 | 4700 | you must provide an appropriate secondary_reload target hook. |
03dda8e3 | 4701 | |
ef4375b2 KZ |
4702 | @findex can_create_pseudo_p |
4703 | The macro @code{can_create_pseudo_p} can be used to determine if it | |
f1db3576 JL |
4704 | is unsafe to create new pseudo registers. If this variable is nonzero, then |
4705 | it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo. | |
4706 | ||
956d6950 | 4707 | The constraints on a @samp{mov@var{m}} must permit moving any hard |
03dda8e3 | 4708 | register to any other hard register provided that |
f939c3e6 | 4709 | @code{TARGET_HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and |
de8f4b07 AS |
4710 | @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value |
4711 | of 2. | |
03dda8e3 | 4712 | |
956d6950 | 4713 | It is obligatory to support floating point @samp{mov@var{m}} |
03dda8e3 RK |
4714 | instructions into and out of any registers that can hold fixed point |
4715 | values, because unions and structures (which have modes @code{SImode} or | |
4716 | @code{DImode}) can be in those registers and they may have floating | |
4717 | point members. | |
4718 | ||
956d6950 | 4719 | There may also be a need to support fixed point @samp{mov@var{m}} |
03dda8e3 RK |
4720 | instructions in and out of floating point registers. Unfortunately, I |
4721 | have forgotten why this was so, and I don't know whether it is still | |
f939c3e6 | 4722 | true. If @code{TARGET_HARD_REGNO_MODE_OK} rejects fixed point values in |
03dda8e3 | 4723 | floating point registers, then the constraints of the fixed point |
956d6950 | 4724 | @samp{mov@var{m}} instructions must be designed to avoid ever trying to |
03dda8e3 RK |
4725 | reload into a floating point register. |
4726 | ||
4727 | @cindex @code{reload_in} instruction pattern | |
4728 | @cindex @code{reload_out} instruction pattern | |
4729 | @item @samp{reload_in@var{m}} | |
4730 | @itemx @samp{reload_out@var{m}} | |
8a99f6f9 R |
4731 | These named patterns have been obsoleted by the target hook |
4732 | @code{secondary_reload}. | |
4733 | ||
03dda8e3 RK |
4734 | Like @samp{mov@var{m}}, but used when a scratch register is required to |
4735 | move between operand 0 and operand 1. Operand 2 describes the scratch | |
4736 | register. See the discussion of the @code{SECONDARY_RELOAD_CLASS} | |
4737 | macro in @pxref{Register Classes}. | |
4738 | ||
d989f648 | 4739 | There are special restrictions on the form of the @code{match_operand}s |
f282ffb3 | 4740 | used in these patterns. First, only the predicate for the reload |
560dbedd RH |
4741 | operand is examined, i.e., @code{reload_in} examines operand 1, but not |
4742 | the predicates for operand 0 or 2. Second, there may be only one | |
d989f648 RH |
4743 | alternative in the constraints. Third, only a single register class |
4744 | letter may be used for the constraint; subsequent constraint letters | |
4745 | are ignored. As a special exception, an empty constraint string | |
4746 | matches the @code{ALL_REGS} register class. This may relieve ports | |
4747 | of the burden of defining an @code{ALL_REGS} constraint letter just | |
4748 | for these patterns. | |
4749 | ||
03dda8e3 RK |
4750 | @cindex @code{movstrict@var{m}} instruction pattern |
4751 | @item @samp{movstrict@var{m}} | |
4752 | Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg} | |
4753 | with mode @var{m} of a register whose natural mode is wider, | |
4754 | the @samp{movstrict@var{m}} instruction is guaranteed not to alter | |
4755 | any of the register except the part which belongs to mode @var{m}. | |
4756 | ||
1e0598e2 RH |
4757 | @cindex @code{movmisalign@var{m}} instruction pattern |
4758 | @item @samp{movmisalign@var{m}} | |
4759 | This variant of a move pattern is designed to load or store a value | |
4760 | from a memory address that is not naturally aligned for its mode. | |
4761 | For a store, the memory will be in operand 0; for a load, the memory | |
4762 | will be in operand 1. The other operand is guaranteed not to be a | |
4763 | memory, so that it's easy to tell whether this is a load or store. | |
4764 | ||
4765 | This pattern is used by the autovectorizer, and when expanding a | |
4766 | @code{MISALIGNED_INDIRECT_REF} expression. | |
4767 | ||
03dda8e3 RK |
4768 | @cindex @code{load_multiple} instruction pattern |
4769 | @item @samp{load_multiple} | |
4770 | Load several consecutive memory locations into consecutive registers. | |
4771 | Operand 0 is the first of the consecutive registers, operand 1 | |
4772 | is the first memory location, and operand 2 is a constant: the | |
4773 | number of consecutive registers. | |
4774 | ||
4775 | Define this only if the target machine really has such an instruction; | |
4776 | do not define this if the most efficient way of loading consecutive | |
4777 | registers from memory is to do them one at a time. | |
4778 | ||
4779 | On some machines, there are restrictions as to which consecutive | |
4780 | registers can be stored into memory, such as particular starting or | |
4781 | ending register numbers or only a range of valid counts. For those | |
4782 | machines, use a @code{define_expand} (@pxref{Expander Definitions}) | |
4783 | and make the pattern fail if the restrictions are not met. | |
4784 | ||
4785 | Write the generated insn as a @code{parallel} with elements being a | |
4786 | @code{set} of one register from the appropriate memory location (you may | |
4787 | also need @code{use} or @code{clobber} elements). Use a | |
4788 | @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See | |
c9693e96 | 4789 | @file{rs6000.md} for examples of the use of this insn pattern. |
03dda8e3 RK |
4790 | |
4791 | @cindex @samp{store_multiple} instruction pattern | |
4792 | @item @samp{store_multiple} | |
4793 | Similar to @samp{load_multiple}, but store several consecutive registers | |
4794 | into consecutive memory locations. Operand 0 is the first of the | |
4795 | consecutive memory locations, operand 1 is the first register, and | |
4796 | operand 2 is a constant: the number of consecutive registers. | |
4797 | ||
272c6793 RS |
4798 | @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern |
4799 | @item @samp{vec_load_lanes@var{m}@var{n}} | |
4800 | Perform an interleaved load of several vectors from memory operand 1 | |
4801 | into register operand 0. Both operands have mode @var{m}. The register | |
4802 | operand is viewed as holding consecutive vectors of mode @var{n}, | |
4803 | while the memory operand is a flat array that contains the same number | |
4804 | of elements. The operation is equivalent to: | |
4805 | ||
4806 | @smallexample | |
4807 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4808 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4809 | for (i = 0; i < c; i++) | |
4810 | operand0[i][j] = operand1[j * c + i]; | |
4811 | @end smallexample | |
4812 | ||
4813 | For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values | |
4814 | from memory into a register of mode @samp{TI}@. The register | |
4815 | contains two consecutive vectors of mode @samp{V4HI}@. | |
4816 | ||
4817 | This pattern can only be used if: | |
4818 | @smallexample | |
4819 | TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c}) | |
4820 | @end smallexample | |
4821 | is true. GCC assumes that, if a target supports this kind of | |
4822 | instruction for some mode @var{n}, it also supports unaligned | |
4823 | loads for vectors of mode @var{n}. | |
4824 | ||
a54a5997 RS |
4825 | This pattern is not allowed to @code{FAIL}. |
4826 | ||
7e11fc7f RS |
4827 | @cindex @code{vec_mask_load_lanes@var{m}@var{n}} instruction pattern |
4828 | @item @samp{vec_mask_load_lanes@var{m}@var{n}} | |
4829 | Like @samp{vec_load_lanes@var{m}@var{n}}, but takes an additional | |
4830 | mask operand (operand 2) that specifies which elements of the destination | |
4831 | vectors should be loaded. Other elements of the destination | |
4832 | vectors are set to zero. The operation is equivalent to: | |
4833 | ||
4834 | @smallexample | |
4835 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4836 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4837 | if (operand2[j]) | |
4838 | for (i = 0; i < c; i++) | |
4839 | operand0[i][j] = operand1[j * c + i]; | |
4840 | else | |
4841 | for (i = 0; i < c; i++) | |
4842 | operand0[i][j] = 0; | |
4843 | @end smallexample | |
4844 | ||
4845 | This pattern is not allowed to @code{FAIL}. | |
4846 | ||
272c6793 RS |
4847 | @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern |
4848 | @item @samp{vec_store_lanes@var{m}@var{n}} | |
4849 | Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory | |
4850 | and register operands reversed. That is, the instruction is | |
4851 | equivalent to: | |
4852 | ||
4853 | @smallexample | |
4854 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4855 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4856 | for (i = 0; i < c; i++) | |
4857 | operand0[j * c + i] = operand1[i][j]; | |
4858 | @end smallexample | |
4859 | ||
4860 | for a memory operand 0 and register operand 1. | |
4861 | ||
a54a5997 RS |
4862 | This pattern is not allowed to @code{FAIL}. |
4863 | ||
7e11fc7f RS |
4864 | @cindex @code{vec_mask_store_lanes@var{m}@var{n}} instruction pattern |
4865 | @item @samp{vec_mask_store_lanes@var{m}@var{n}} | |
4866 | Like @samp{vec_store_lanes@var{m}@var{n}}, but takes an additional | |
4867 | mask operand (operand 2) that specifies which elements of the source | |
4868 | vectors should be stored. The operation is equivalent to: | |
4869 | ||
4870 | @smallexample | |
4871 | int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n}); | |
4872 | for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++) | |
4873 | if (operand2[j]) | |
4874 | for (i = 0; i < c; i++) | |
4875 | operand0[j * c + i] = operand1[i][j]; | |
4876 | @end smallexample | |
4877 | ||
4878 | This pattern is not allowed to @code{FAIL}. | |
4879 | ||
09eb042a RS |
4880 | @cindex @code{gather_load@var{m}@var{n}} instruction pattern |
4881 | @item @samp{gather_load@var{m}@var{n}} | |
bfaa08b7 | 4882 | Load several separate memory locations into a vector of mode @var{m}. |
09eb042a RS |
4883 | Operand 1 is a scalar base address and operand 2 is a vector of mode @var{n} |
4884 | containing offsets from that base. Operand 0 is a destination vector with | |
4885 | the same number of elements as @var{n}. For each element index @var{i}: | |
bfaa08b7 RS |
4886 | |
4887 | @itemize @bullet | |
4888 | @item | |
4889 | extend the offset element @var{i} to address width, using zero | |
4890 | extension if operand 3 is 1 and sign extension if operand 3 is zero; | |
4891 | @item | |
4892 | multiply the extended offset by operand 4; | |
4893 | @item | |
4894 | add the result to the base; and | |
4895 | @item | |
4896 | load the value at that address into element @var{i} of operand 0. | |
4897 | @end itemize | |
4898 | ||
4899 | The value of operand 3 does not matter if the offsets are already | |
4900 | address width. | |
4901 | ||
09eb042a RS |
4902 | @cindex @code{mask_gather_load@var{m}@var{n}} instruction pattern |
4903 | @item @samp{mask_gather_load@var{m}@var{n}} | |
4904 | Like @samp{gather_load@var{m}@var{n}}, but takes an extra mask operand as | |
bfaa08b7 RS |
4905 | operand 5. Bit @var{i} of the mask is set if element @var{i} |
4906 | of the result should be loaded from memory and clear if element @var{i} | |
4907 | of the result should be set to zero. | |
4908 | ||
09eb042a RS |
4909 | @cindex @code{scatter_store@var{m}@var{n}} instruction pattern |
4910 | @item @samp{scatter_store@var{m}@var{n}} | |
f307441a | 4911 | Store a vector of mode @var{m} into several distinct memory locations. |
09eb042a RS |
4912 | Operand 0 is a scalar base address and operand 1 is a vector of mode |
4913 | @var{n} containing offsets from that base. Operand 4 is the vector of | |
4914 | values that should be stored, which has the same number of elements as | |
4915 | @var{n}. For each element index @var{i}: | |
f307441a RS |
4916 | |
4917 | @itemize @bullet | |
4918 | @item | |
4919 | extend the offset element @var{i} to address width, using zero | |
4920 | extension if operand 2 is 1 and sign extension if operand 2 is zero; | |
4921 | @item | |
4922 | multiply the extended offset by operand 3; | |
4923 | @item | |
4924 | add the result to the base; and | |
4925 | @item | |
4926 | store element @var{i} of operand 4 to that address. | |
4927 | @end itemize | |
4928 | ||
4929 | The value of operand 2 does not matter if the offsets are already | |
4930 | address width. | |
4931 | ||
09eb042a RS |
4932 | @cindex @code{mask_scatter_store@var{m}@var{n}} instruction pattern |
4933 | @item @samp{mask_scatter_store@var{m}@var{n}} | |
4934 | Like @samp{scatter_store@var{m}@var{n}}, but takes an extra mask operand as | |
f307441a RS |
4935 | operand 5. Bit @var{i} of the mask is set if element @var{i} |
4936 | of the result should be stored to memory. | |
4937 | ||
ef1140a9 JH |
4938 | @cindex @code{vec_set@var{m}} instruction pattern |
4939 | @item @samp{vec_set@var{m}} | |
4940 | Set given field in the vector value. Operand 0 is the vector to modify, | |
4941 | operand 1 is new value of field and operand 2 specify the field index. | |
4942 | ||
ff03930a JJ |
4943 | @cindex @code{vec_extract@var{m}@var{n}} instruction pattern |
4944 | @item @samp{vec_extract@var{m}@var{n}} | |
ef1140a9 | 4945 | Extract given field from the vector value. Operand 1 is the vector, operand 2 |
ff03930a JJ |
4946 | specify field index and operand 0 place to store value into. The |
4947 | @var{n} mode is the mode of the field or vector of fields that should be | |
4948 | extracted, should be either element mode of the vector mode @var{m}, or | |
4949 | a vector mode with the same element mode and smaller number of elements. | |
4950 | If @var{n} is a vector mode, the index is counted in units of that mode. | |
4951 | ||
4952 | @cindex @code{vec_init@var{m}@var{n}} instruction pattern | |
4953 | @item @samp{vec_init@var{m}@var{n}} | |
425a2bde | 4954 | Initialize the vector to given values. Operand 0 is the vector to initialize |
ff03930a JJ |
4955 | and operand 1 is parallel containing values for individual fields. The |
4956 | @var{n} mode is the mode of the elements, should be either element mode of | |
4957 | the vector mode @var{m}, or a vector mode with the same element mode and | |
4958 | smaller number of elements. | |
ef1140a9 | 4959 | |
be4c1d4a RS |
4960 | @cindex @code{vec_duplicate@var{m}} instruction pattern |
4961 | @item @samp{vec_duplicate@var{m}} | |
4962 | Initialize vector output operand 0 so that each element has the value given | |
4963 | by scalar input operand 1. The vector has mode @var{m} and the scalar has | |
4964 | the mode appropriate for one element of @var{m}. | |
4965 | ||
4966 | This pattern only handles duplicates of non-constant inputs. Constant | |
4967 | vectors go through the @code{mov@var{m}} pattern instead. | |
4968 | ||
4969 | This pattern is not allowed to @code{FAIL}. | |
4970 | ||
9adab579 RS |
4971 | @cindex @code{vec_series@var{m}} instruction pattern |
4972 | @item @samp{vec_series@var{m}} | |
4973 | Initialize vector output operand 0 so that element @var{i} is equal to | |
4974 | operand 1 plus @var{i} times operand 2. In other words, create a linear | |
4975 | series whose base value is operand 1 and whose step is operand 2. | |
4976 | ||
4977 | The vector output has mode @var{m} and the scalar inputs have the mode | |
4978 | appropriate for one element of @var{m}. This pattern is not used for | |
4979 | floating-point vectors, in order to avoid having to specify the | |
4980 | rounding behavior for @var{i} > 1. | |
4981 | ||
4982 | This pattern is not allowed to @code{FAIL}. | |
4983 | ||
7cfb4d93 RS |
4984 | @cindex @code{while_ult@var{m}@var{n}} instruction pattern |
4985 | @item @code{while_ult@var{m}@var{n}} | |
4986 | Set operand 0 to a mask that is true while incrementing operand 1 | |
4987 | gives a value that is less than operand 2. Operand 0 has mode @var{n} | |
4988 | and operands 1 and 2 are scalar integers of mode @var{m}. | |
4989 | The operation is equivalent to: | |
4990 | ||
4991 | @smallexample | |
4992 | operand0[0] = operand1 < operand2; | |
4993 | for (i = 1; i < GET_MODE_NUNITS (@var{n}); i++) | |
4994 | operand0[i] = operand0[i - 1] && (operand1 + i < operand2); | |
4995 | @end smallexample | |
58c036c8 RS |
4996 | |
4997 | @cindex @code{check_raw_ptrs@var{m}} instruction pattern | |
4998 | @item @samp{check_raw_ptrs@var{m}} | |
4999 | Check whether, given two pointers @var{a} and @var{b} and a length @var{len}, | |
5000 | a write of @var{len} bytes at @var{a} followed by a read of @var{len} bytes | |
5001 | at @var{b} can be split into interleaved byte accesses | |
5002 | @samp{@var{a}[0], @var{b}[0], @var{a}[1], @var{b}[1], @dots{}} | |
5003 | without affecting the dependencies between the bytes. Set operand 0 | |
5004 | to true if the split is possible and false otherwise. | |
5005 | ||
5006 | Operands 1, 2 and 3 provide the values of @var{a}, @var{b} and @var{len} | |
5007 | respectively. Operand 4 is a constant integer that provides the known | |
5008 | common alignment of @var{a} and @var{b}. All inputs have mode @var{m}. | |
5009 | ||
5010 | This split is possible if: | |
5011 | ||
5012 | @smallexample | |
5013 | @var{a} == @var{b} || @var{a} + @var{len} <= @var{b} || @var{b} + @var{len} <= @var{a} | |
5014 | @end smallexample | |
5015 | ||
5016 | You should only define this pattern if the target has a way of accelerating | |
5017 | the test without having to do the individual comparisons. | |
5018 | ||
5019 | @cindex @code{check_war_ptrs@var{m}} instruction pattern | |
5020 | @item @samp{check_war_ptrs@var{m}} | |
5021 | Like @samp{check_raw_ptrs@var{m}}, but with the read and write swapped round. | |
5022 | The split is possible in this case if: | |
5023 | ||
5024 | @smallexample | |
5025 | @var{b} <= @var{a} || @var{a} + @var{len} <= @var{b} | |
5026 | @end smallexample | |
7cfb4d93 | 5027 | |
12fb875f IE |
5028 | @cindex @code{vec_cmp@var{m}@var{n}} instruction pattern |
5029 | @item @samp{vec_cmp@var{m}@var{n}} | |
5030 | Output a vector comparison. Operand 0 of mode @var{n} is the destination for | |
5031 | predicate in operand 1 which is a signed vector comparison with operands of | |
5032 | mode @var{m} in operands 2 and 3. Predicate is computed by element-wise | |
5033 | evaluation of the vector comparison with a truth value of all-ones and a false | |
5034 | value of all-zeros. | |
5035 | ||
5036 | @cindex @code{vec_cmpu@var{m}@var{n}} instruction pattern | |
5037 | @item @samp{vec_cmpu@var{m}@var{n}} | |
5038 | Similar to @code{vec_cmp@var{m}@var{n}} but perform unsigned vector comparison. | |
5039 | ||
96592eed JJ |
5040 | @cindex @code{vec_cmpeq@var{m}@var{n}} instruction pattern |
5041 | @item @samp{vec_cmpeq@var{m}@var{n}} | |
5042 | Similar to @code{vec_cmp@var{m}@var{n}} but perform equality or non-equality | |
5043 | vector comparison only. If @code{vec_cmp@var{m}@var{n}} | |
5044 | or @code{vec_cmpu@var{m}@var{n}} instruction pattern is supported, | |
5045 | it will be preferred over @code{vec_cmpeq@var{m}@var{n}}, so there is | |
5046 | no need to define this instruction pattern if the others are supported. | |
5047 | ||
e9e1d143 RG |
5048 | @cindex @code{vcond@var{m}@var{n}} instruction pattern |
5049 | @item @samp{vcond@var{m}@var{n}} | |
5050 | Output a conditional vector move. Operand 0 is the destination to | |
5051 | receive a combination of operand 1 and operand 2, which are of mode @var{m}, | |
12fb875f | 5052 | dependent on the outcome of the predicate in operand 3 which is a signed |
e9e1d143 RG |
5053 | vector comparison with operands of mode @var{n} in operands 4 and 5. The |
5054 | modes @var{m} and @var{n} should have the same size. Operand 0 | |
5055 | will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} | |
5056 | where @var{msk} is computed by element-wise evaluation of the vector | |
5057 | comparison with a truth value of all-ones and a false value of all-zeros. | |
5058 | ||
12fb875f IE |
5059 | @cindex @code{vcondu@var{m}@var{n}} instruction pattern |
5060 | @item @samp{vcondu@var{m}@var{n}} | |
5061 | Similar to @code{vcond@var{m}@var{n}} but performs unsigned vector | |
5062 | comparison. | |
5063 | ||
96592eed JJ |
5064 | @cindex @code{vcondeq@var{m}@var{n}} instruction pattern |
5065 | @item @samp{vcondeq@var{m}@var{n}} | |
5066 | Similar to @code{vcond@var{m}@var{n}} but performs equality or | |
5067 | non-equality vector comparison only. If @code{vcond@var{m}@var{n}} | |
5068 | or @code{vcondu@var{m}@var{n}} instruction pattern is supported, | |
5069 | it will be preferred over @code{vcondeq@var{m}@var{n}}, so there is | |
5070 | no need to define this instruction pattern if the others are supported. | |
5071 | ||
12fb875f IE |
5072 | @cindex @code{vcond_mask_@var{m}@var{n}} instruction pattern |
5073 | @item @samp{vcond_mask_@var{m}@var{n}} | |
5074 | Similar to @code{vcond@var{m}@var{n}} but operand 3 holds a pre-computed | |
5075 | result of vector comparison. | |
5076 | ||
5077 | @cindex @code{maskload@var{m}@var{n}} instruction pattern | |
5078 | @item @samp{maskload@var{m}@var{n}} | |
5079 | Perform a masked load of vector from memory operand 1 of mode @var{m} | |
5080 | into register operand 0. Mask is provided in register operand 2 of | |
5081 | mode @var{n}. | |
5082 | ||
a54a5997 RS |
5083 | This pattern is not allowed to @code{FAIL}. |
5084 | ||
12fb875f | 5085 | @cindex @code{maskstore@var{m}@var{n}} instruction pattern |
a54a5997 | 5086 | @item @samp{maskstore@var{m}@var{n}} |
12fb875f IE |
5087 | Perform a masked store of vector from register operand 1 of mode @var{m} |
5088 | into memory operand 0. Mask is provided in register operand 2 of | |
5089 | mode @var{n}. | |
5090 | ||
a54a5997 | 5091 | This pattern is not allowed to @code{FAIL}. |
d496134a KL |
5092 | |
5093 | @cindex @code{len_load_@var{m}} instruction pattern | |
5094 | @item @samp{len_load_@var{m}} | |
b0e51639 RD |
5095 | Load (operand 2 - operand 3) elements from vector memory operand 1 |
5096 | into vector register operand 0, setting the other elements of | |
d496134a KL |
5097 | operand 0 to undefined values. Operands 0 and 1 have mode @var{m}, |
5098 | which must be a vector mode. Operand 2 has whichever integer mode the | |
b0e51639 RD |
5099 | target prefers. Operand 3 conceptually has mode @code{QI}. |
5100 | ||
5101 | Operand 2 can be a variable or a constant amount. Operand 3 specifies a | |
5102 | constant bias: it is either a constant 0 or a constant -1. The predicate on | |
5103 | operand 3 must only accept the bias values that the target actually supports. | |
5104 | GCC handles a bias of 0 more efficiently than a bias of -1. | |
5105 | ||
5106 | If (operand 2 - operand 3) exceeds the number of elements in mode | |
5107 | @var{m}, the behavior is undefined. | |
5108 | ||
5109 | If the target prefers the length to be measured in bytes rather than | |
5110 | elements, it should only implement this pattern for vectors of @code{QI} | |
5111 | elements. | |
d496134a KL |
5112 | |
5113 | This pattern is not allowed to @code{FAIL}. | |
5114 | ||
5115 | @cindex @code{len_store_@var{m}} instruction pattern | |
5116 | @item @samp{len_store_@var{m}} | |
b0e51639 RD |
5117 | Store (operand 2 - operand 3) vector elements from vector register operand 1 |
5118 | into memory operand 0, leaving the other elements of | |
d496134a KL |
5119 | operand 0 unchanged. Operands 0 and 1 have mode @var{m}, which must be |
5120 | a vector mode. Operand 2 has whichever integer mode the target prefers. | |
b0e51639 RD |
5121 | Operand 3 conceptually has mode @code{QI}. |
5122 | ||
5123 | Operand 2 can be a variable or a constant amount. Operand 3 specifies a | |
5124 | constant bias: it is either a constant 0 or a constant -1. The predicate on | |
5125 | operand 3 must only accept the bias values that the target actually supports. | |
5126 | GCC handles a bias of 0 more efficiently than a bias of -1. | |
5127 | ||
5128 | If (operand 2 - operand 3) exceeds the number of elements in mode | |
5129 | @var{m}, the behavior is undefined. | |
5130 | ||
5131 | If the target prefers the length to be measured in bytes | |
d496134a KL |
5132 | rather than elements, it should only implement this pattern for vectors |
5133 | of @code{QI} elements. | |
5134 | ||
5135 | This pattern is not allowed to @code{FAIL}. | |
a54a5997 | 5136 | |
2205ed25 RH |
5137 | @cindex @code{vec_perm@var{m}} instruction pattern |
5138 | @item @samp{vec_perm@var{m}} | |
5139 | Output a (variable) vector permutation. Operand 0 is the destination | |
5140 | to receive elements from operand 1 and operand 2, which are of mode | |
5141 | @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode | |
5142 | vector of the same width and number of elements as mode @var{m}. | |
5143 | ||
5144 | The input elements are numbered from 0 in operand 1 through | |
5145 | @math{2*@var{N}-1} in operand 2. The elements of the selector must | |
5146 | be computed modulo @math{2*@var{N}}. Note that if | |
5147 | @code{rtx_equal_p(operand1, operand2)}, this can be implemented | |
5148 | with just operand 1 and selector elements modulo @var{N}. | |
5149 | ||
d7943c8b RH |
5150 | In order to make things easy for a number of targets, if there is no |
5151 | @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q} | |
5152 | where @var{q} is a vector of @code{QImode} of the same width as @var{m}, | |
5153 | the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to | |
5154 | mode @var{q}. | |
5155 | ||
f151c9e1 RS |
5156 | See also @code{TARGET_VECTORIZER_VEC_PERM_CONST}, which performs |
5157 | the analogous operation for constant selectors. | |
2205ed25 | 5158 | |
759915ca EC |
5159 | @cindex @code{push@var{m}1} instruction pattern |
5160 | @item @samp{push@var{m}1} | |
299c5111 | 5161 | Output a push instruction. Operand 0 is value to push. Used only when |
38f4324c JH |
5162 | @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be |
5163 | missing and in such case an @code{mov} expander is used instead, with a | |
6e9aac46 | 5164 | @code{MEM} expression forming the push operation. The @code{mov} expander |
38f4324c JH |
5165 | method is deprecated. |
5166 | ||
03dda8e3 RK |
5167 | @cindex @code{add@var{m}3} instruction pattern |
5168 | @item @samp{add@var{m}3} | |
5169 | Add operand 2 and operand 1, storing the result in operand 0. All operands | |
5170 | must have mode @var{m}. This can be used even on two-address machines, by | |
5171 | means of constraints requiring operands 1 and 0 to be the same location. | |
5172 | ||
0f996086 CF |
5173 | @cindex @code{ssadd@var{m}3} instruction pattern |
5174 | @cindex @code{usadd@var{m}3} instruction pattern | |
03dda8e3 | 5175 | @cindex @code{sub@var{m}3} instruction pattern |
0f996086 CF |
5176 | @cindex @code{sssub@var{m}3} instruction pattern |
5177 | @cindex @code{ussub@var{m}3} instruction pattern | |
03dda8e3 | 5178 | @cindex @code{mul@var{m}3} instruction pattern |
0f996086 CF |
5179 | @cindex @code{ssmul@var{m}3} instruction pattern |
5180 | @cindex @code{usmul@var{m}3} instruction pattern | |
03dda8e3 | 5181 | @cindex @code{div@var{m}3} instruction pattern |
0f996086 | 5182 | @cindex @code{ssdiv@var{m}3} instruction pattern |
03dda8e3 | 5183 | @cindex @code{udiv@var{m}3} instruction pattern |
0f996086 | 5184 | @cindex @code{usdiv@var{m}3} instruction pattern |
03dda8e3 RK |
5185 | @cindex @code{mod@var{m}3} instruction pattern |
5186 | @cindex @code{umod@var{m}3} instruction pattern | |
03dda8e3 RK |
5187 | @cindex @code{umin@var{m}3} instruction pattern |
5188 | @cindex @code{umax@var{m}3} instruction pattern | |
5189 | @cindex @code{and@var{m}3} instruction pattern | |
5190 | @cindex @code{ior@var{m}3} instruction pattern | |
5191 | @cindex @code{xor@var{m}3} instruction pattern | |
0f996086 | 5192 | @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3} |
f457c50c AS |
5193 | @itemx @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3} |
5194 | @itemx @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3} | |
0f996086 CF |
5195 | @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3} |
5196 | @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3} | |
7ae4d8d4 RH |
5197 | @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3} |
5198 | @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3} | |
03dda8e3 RK |
5199 | @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3} |
5200 | Similar, for other arithmetic operations. | |
7ae4d8d4 | 5201 | |
481efdd9 EB |
5202 | @cindex @code{addv@var{m}4} instruction pattern |
5203 | @item @samp{addv@var{m}4} | |
5204 | Like @code{add@var{m}3} but takes a @code{code_label} as operand 3 and | |
5205 | emits code to jump to it if signed overflow occurs during the addition. | |
5206 | This pattern is used to implement the built-in functions performing | |
5207 | signed integer addition with overflow checking. | |
5208 | ||
5209 | @cindex @code{subv@var{m}4} instruction pattern | |
5210 | @cindex @code{mulv@var{m}4} instruction pattern | |
5211 | @item @samp{subv@var{m}4}, @samp{mulv@var{m}4} | |
5212 | Similar, for other signed arithmetic operations. | |
5213 | ||
cde9d596 RH |
5214 | @cindex @code{uaddv@var{m}4} instruction pattern |
5215 | @item @samp{uaddv@var{m}4} | |
5216 | Like @code{addv@var{m}4} but for unsigned addition. That is to | |
5217 | say, the operation is the same as signed addition but the jump | |
481efdd9 EB |
5218 | is taken only on unsigned overflow. |
5219 | ||
cde9d596 RH |
5220 | @cindex @code{usubv@var{m}4} instruction pattern |
5221 | @cindex @code{umulv@var{m}4} instruction pattern | |
5222 | @item @samp{usubv@var{m}4}, @samp{umulv@var{m}4} | |
5223 | Similar, for other unsigned arithmetic operations. | |
5224 | ||
481efdd9 EB |
5225 | @cindex @code{addptr@var{m}3} instruction pattern |
5226 | @item @samp{addptr@var{m}3} | |
5227 | Like @code{add@var{m}3} but is guaranteed to only be used for address | |
5228 | calculations. The expanded code is not allowed to clobber the | |
5229 | condition code. It only needs to be defined if @code{add@var{m}3} | |
5230 | sets the condition code. If adds used for address calculations and | |
5231 | normal adds are not compatible it is required to expand a distinct | |
630ba2fd | 5232 | pattern (e.g.@: using an unspec). The pattern is used by LRA to emit |
481efdd9 EB |
5233 | address calculations. @code{add@var{m}3} is used if |
5234 | @code{addptr@var{m}3} is not defined. | |
5235 | ||
1b1562a5 MM |
5236 | @cindex @code{fma@var{m}4} instruction pattern |
5237 | @item @samp{fma@var{m}4} | |
5238 | Multiply operand 2 and operand 1, then add operand 3, storing the | |
d6373302 KZ |
5239 | result in operand 0 without doing an intermediate rounding step. All |
5240 | operands must have mode @var{m}. This pattern is used to implement | |
5241 | the @code{fma}, @code{fmaf}, and @code{fmal} builtin functions from | |
5242 | the ISO C99 standard. | |
1b1562a5 | 5243 | |
16949072 RG |
5244 | @cindex @code{fms@var{m}4} instruction pattern |
5245 | @item @samp{fms@var{m}4} | |
5246 | Like @code{fma@var{m}4}, except operand 3 subtracted from the | |
5247 | product instead of added to the product. This is represented | |
5248 | in the rtl as | |
5249 | ||
5250 | @smallexample | |
5251 | (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3})) | |
5252 | @end smallexample | |
5253 | ||
5254 | @cindex @code{fnma@var{m}4} instruction pattern | |
5255 | @item @samp{fnma@var{m}4} | |
5256 | Like @code{fma@var{m}4} except that the intermediate product | |
5257 | is negated before being added to operand 3. This is represented | |
5258 | in the rtl as | |
5259 | ||
5260 | @smallexample | |
5261 | (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3}) | |
5262 | @end smallexample | |
5263 | ||
5264 | @cindex @code{fnms@var{m}4} instruction pattern | |
5265 | @item @samp{fnms@var{m}4} | |
5266 | Like @code{fms@var{m}4} except that the intermediate product | |
5267 | is negated before subtracting operand 3. This is represented | |
5268 | in the rtl as | |
5269 | ||
5270 | @smallexample | |
5271 | (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3})) | |
5272 | @end smallexample | |
5273 | ||
b71b019a JH |
5274 | @cindex @code{min@var{m}3} instruction pattern |
5275 | @cindex @code{max@var{m}3} instruction pattern | |
7ae4d8d4 RH |
5276 | @item @samp{smin@var{m}3}, @samp{smax@var{m}3} |
5277 | Signed minimum and maximum operations. When used with floating point, | |
5278 | if both operands are zeros, or if either operand is @code{NaN}, then | |
5279 | it is unspecified which of the two operands is returned as the result. | |
03dda8e3 | 5280 | |
ccb57bb0 DS |
5281 | @cindex @code{fmin@var{m}3} instruction pattern |
5282 | @cindex @code{fmax@var{m}3} instruction pattern | |
5283 | @item @samp{fmin@var{m}3}, @samp{fmax@var{m}3} | |
5284 | IEEE-conformant minimum and maximum operations. If one operand is a quiet | |
5285 | @code{NaN}, then the other operand is returned. If both operands are quiet | |
5286 | @code{NaN}, then a quiet @code{NaN} is returned. In the case when gcc supports | |
18ea359a | 5287 | signaling @code{NaN} (-fsignaling-nans) an invalid floating point exception is |
ccb57bb0 DS |
5288 | raised and a quiet @code{NaN} is returned. |
5289 | ||
a54a5997 RS |
5290 | All operands have mode @var{m}, which is a scalar or vector |
5291 | floating-point mode. These patterns are not allowed to @code{FAIL}. | |
5292 | ||
d43a252e AL |
5293 | @cindex @code{reduc_smin_scal_@var{m}} instruction pattern |
5294 | @cindex @code{reduc_smax_scal_@var{m}} instruction pattern | |
5295 | @item @samp{reduc_smin_scal_@var{m}}, @samp{reduc_smax_scal_@var{m}} | |
5296 | Find the signed minimum/maximum of the elements of a vector. The vector is | |
5297 | operand 1, and operand 0 is the scalar result, with mode equal to the mode of | |
5298 | the elements of the input vector. | |
5299 | ||
5300 | @cindex @code{reduc_umin_scal_@var{m}} instruction pattern | |
5301 | @cindex @code{reduc_umax_scal_@var{m}} instruction pattern | |
5302 | @item @samp{reduc_umin_scal_@var{m}}, @samp{reduc_umax_scal_@var{m}} | |
5303 | Find the unsigned minimum/maximum of the elements of a vector. The vector is | |
5304 | operand 1, and operand 0 is the scalar result, with mode equal to the mode of | |
5305 | the elements of the input vector. | |
5306 | ||
e32b9eb3 RS |
5307 | @cindex @code{reduc_fmin_scal_@var{m}} instruction pattern |
5308 | @cindex @code{reduc_fmax_scal_@var{m}} instruction pattern | |
5309 | @item @samp{reduc_fmin_scal_@var{m}}, @samp{reduc_fmax_scal_@var{m}} | |
5310 | Find the floating-point minimum/maximum of the elements of a vector, | |
5311 | using the same rules as @code{fmin@var{m}3} and @code{fmax@var{m}3}. | |
5312 | Operand 1 is a vector of mode @var{m} and operand 0 is the scalar | |
5313 | result, which has mode @code{GET_MODE_INNER (@var{m})}. | |
5314 | ||
d43a252e AL |
5315 | @cindex @code{reduc_plus_scal_@var{m}} instruction pattern |
5316 | @item @samp{reduc_plus_scal_@var{m}} | |
5317 | Compute the sum of the elements of a vector. The vector is operand 1, and | |
5318 | operand 0 is the scalar result, with mode equal to the mode of the elements of | |
5319 | the input vector. | |
61abee65 | 5320 | |
898f07b0 RS |
5321 | @cindex @code{reduc_and_scal_@var{m}} instruction pattern |
5322 | @item @samp{reduc_and_scal_@var{m}} | |
5323 | @cindex @code{reduc_ior_scal_@var{m}} instruction pattern | |
5324 | @itemx @samp{reduc_ior_scal_@var{m}} | |
5325 | @cindex @code{reduc_xor_scal_@var{m}} instruction pattern | |
5326 | @itemx @samp{reduc_xor_scal_@var{m}} | |
5327 | Compute the bitwise @code{AND}/@code{IOR}/@code{XOR} reduction of the elements | |
5328 | of a vector of mode @var{m}. Operand 1 is the vector input and operand 0 | |
5329 | is the scalar result. The mode of the scalar result is the same as one | |
5330 | element of @var{m}. | |
5331 | ||
bfe1bb57 RS |
5332 | @cindex @code{extract_last_@var{m}} instruction pattern |
5333 | @item @code{extract_last_@var{m}} | |
5334 | Find the last set bit in mask operand 1 and extract the associated element | |
5335 | of vector operand 2. Store the result in scalar operand 0. Operand 2 | |
5336 | has vector mode @var{m} while operand 0 has the mode appropriate for one | |
5337 | element of @var{m}. Operand 1 has the usual mask mode for vectors of mode | |
5338 | @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
5339 | ||
bb6c2b68 RS |
5340 | @cindex @code{fold_extract_last_@var{m}} instruction pattern |
5341 | @item @code{fold_extract_last_@var{m}} | |
5342 | If any bits of mask operand 2 are set, find the last set bit, extract | |
5343 | the associated element from vector operand 3, and store the result | |
5344 | in operand 0. Store operand 1 in operand 0 otherwise. Operand 3 | |
5345 | has mode @var{m} and operands 0 and 1 have the mode appropriate for | |
5346 | one element of @var{m}. Operand 2 has the usual mask mode for vectors | |
5347 | of mode @var{m}; see @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
5348 | ||
b781a135 RS |
5349 | @cindex @code{fold_left_plus_@var{m}} instruction pattern |
5350 | @item @code{fold_left_plus_@var{m}} | |
5351 | Take scalar operand 1 and successively add each element from vector | |
5352 | operand 2. Store the result in scalar operand 0. The vector has | |
5353 | mode @var{m} and the scalars have the mode appropriate for one | |
5354 | element of @var{m}. The operation is strictly in-order: there is | |
5355 | no reassociation. | |
5356 | ||
bce29d65 AM |
5357 | @cindex @code{mask_fold_left_plus_@var{m}} instruction pattern |
5358 | @item @code{mask_fold_left_plus_@var{m}} | |
5359 | Like @samp{fold_left_plus_@var{m}}, but takes an additional mask operand | |
5360 | (operand 3) that specifies which elements of the source vector should be added. | |
5361 | ||
20f06221 DN |
5362 | @cindex @code{sdot_prod@var{m}} instruction pattern |
5363 | @item @samp{sdot_prod@var{m}} | |
ab0a6b21 TC |
5364 | |
5365 | Compute the sum of the products of two signed elements. | |
5366 | Operand 1 and operand 2 are of the same mode. Their | |
5367 | product, which is of a wider mode, is computed and added to operand 3. | |
5368 | Operand 3 is of a mode equal or wider than the mode of the product. The | |
5369 | result is placed in operand 0, which is of the same mode as operand 3. | |
5370 | ||
5371 | Semantically the expressions perform the multiplication in the following signs | |
5372 | ||
5373 | @smallexample | |
5374 | sdot<signed op0, signed op1, signed op2, signed op3> == | |
5375 | op0 = sign-ext (op1) * sign-ext (op2) + op3 | |
5376 | @dots{} | |
5377 | @end smallexample | |
5378 | ||
20f06221 | 5379 | @cindex @code{udot_prod@var{m}} instruction pattern |
ab0a6b21 TC |
5380 | @item @samp{udot_prod@var{m}} |
5381 | ||
5382 | Compute the sum of the products of two unsigned elements. | |
5383 | Operand 1 and operand 2 are of the same mode. Their | |
5384 | product, which is of a wider mode, is computed and added to operand 3. | |
5385 | Operand 3 is of a mode equal or wider than the mode of the product. The | |
5386 | result is placed in operand 0, which is of the same mode as operand 3. | |
5387 | ||
5388 | Semantically the expressions perform the multiplication in the following signs | |
5389 | ||
5390 | @smallexample | |
5391 | udot<unsigned op0, unsigned op1, unsigned op2, unsigned op3> == | |
5392 | op0 = zero-ext (op1) * zero-ext (op2) + op3 | |
5393 | @dots{} | |
5394 | @end smallexample | |
5395 | ||
5396 | @cindex @code{usdot_prod@var{m}} instruction pattern | |
5397 | @item @samp{usdot_prod@var{m}} | |
5398 | Compute the sum of the products of elements of different signs. | |
5399 | Operand 1 must be unsigned and operand 2 signed. Their | |
5400 | product, which is of a wider mode, is computed and added to operand 3. | |
5401 | Operand 3 is of a mode equal or wider than the mode of the product. The | |
5402 | result is placed in operand 0, which is of the same mode as operand 3. | |
5403 | ||
5404 | Semantically the expressions perform the multiplication in the following signs | |
5405 | ||
5406 | @smallexample | |
5407 | usdot<signed op0, unsigned op1, signed op2, signed op3> == | |
5408 | op0 = ((signed-conv) zero-ext (op1)) * sign-ext (op2) + op3 | |
5409 | @dots{} | |
5410 | @end smallexample | |
20f06221 | 5411 | |
79d652a5 CH |
5412 | @cindex @code{ssad@var{m}} instruction pattern |
5413 | @item @samp{ssad@var{m}} | |
5414 | @cindex @code{usad@var{m}} instruction pattern | |
5415 | @item @samp{usad@var{m}} | |
5416 | Compute the sum of absolute differences of two signed/unsigned elements. | |
5417 | Operand 1 and operand 2 are of the same mode. Their absolute difference, which | |
5418 | is of a wider mode, is computed and added to operand 3. Operand 3 is of a mode | |
5419 | equal or wider than the mode of the absolute difference. The result is placed | |
5420 | in operand 0, which is of the same mode as operand 3. | |
5421 | ||
97532d1a MC |
5422 | @cindex @code{widen_ssum@var{m3}} instruction pattern |
5423 | @item @samp{widen_ssum@var{m3}} | |
5424 | @cindex @code{widen_usum@var{m3}} instruction pattern | |
5425 | @itemx @samp{widen_usum@var{m3}} | |
ff2ce160 | 5426 | Operands 0 and 2 are of the same mode, which is wider than the mode of |
20f06221 DN |
5427 | operand 1. Add operand 1 to operand 2 and place the widened result in |
5428 | operand 0. (This is used express accumulation of elements into an accumulator | |
5429 | of a wider mode.) | |
5430 | ||
58cc9876 YW |
5431 | @cindex @code{smulhs@var{m3}} instruction pattern |
5432 | @item @samp{smulhs@var{m3}} | |
5433 | @cindex @code{umulhs@var{m3}} instruction pattern | |
5434 | @itemx @samp{umulhs@var{m3}} | |
5435 | Signed/unsigned multiply high with scale. This is equivalent to the C code: | |
5436 | @smallexample | |
5437 | narrow op0, op1, op2; | |
5438 | @dots{} | |
5439 | op0 = (narrow) (((wide) op1 * (wide) op2) >> (N / 2 - 1)); | |
5440 | @end smallexample | |
5441 | where the sign of @samp{narrow} determines whether this is a signed | |
5442 | or unsigned operation, and @var{N} is the size of @samp{wide} in bits. | |
5443 | ||
5444 | @cindex @code{smulhrs@var{m3}} instruction pattern | |
5445 | @item @samp{smulhrs@var{m3}} | |
5446 | @cindex @code{umulhrs@var{m3}} instruction pattern | |
5447 | @itemx @samp{umulhrs@var{m3}} | |
5448 | Signed/unsigned multiply high with round and scale. This is | |
5449 | equivalent to the C code: | |
5450 | @smallexample | |
5451 | narrow op0, op1, op2; | |
5452 | @dots{} | |
5453 | op0 = (narrow) (((((wide) op1 * (wide) op2) >> (N / 2 - 2)) + 1) >> 1); | |
5454 | @end smallexample | |
5455 | where the sign of @samp{narrow} determines whether this is a signed | |
5456 | or unsigned operation, and @var{N} is the size of @samp{wide} in bits. | |
5457 | ||
c0c2f013 YW |
5458 | @cindex @code{sdiv_pow2@var{m3}} instruction pattern |
5459 | @item @samp{sdiv_pow2@var{m3}} | |
5460 | @cindex @code{sdiv_pow2@var{m3}} instruction pattern | |
5461 | @itemx @samp{sdiv_pow2@var{m3}} | |
5462 | Signed division by power-of-2 immediate. Equivalent to: | |
5463 | @smallexample | |
5464 | signed op0, op1; | |
5465 | @dots{} | |
5466 | op0 = op1 / (1 << imm); | |
5467 | @end smallexample | |
5468 | ||
f1739b48 RS |
5469 | @cindex @code{vec_shl_insert_@var{m}} instruction pattern |
5470 | @item @samp{vec_shl_insert_@var{m}} | |
630ba2fd | 5471 | Shift the elements in vector input operand 1 left one element (i.e.@: |
f1739b48 RS |
5472 | away from element 0) and fill the vacated element 0 with the scalar |
5473 | in operand 2. Store the result in vector output operand 0. Operands | |
5474 | 0 and 1 have mode @var{m} and operand 2 has the mode appropriate for | |
5475 | one element of @var{m}. | |
5476 | ||
2e83f583 JJ |
5477 | @cindex @code{vec_shl_@var{m}} instruction pattern |
5478 | @item @samp{vec_shl_@var{m}} | |
5479 | Whole vector left shift in bits, i.e.@: away from element 0. | |
5480 | Operand 1 is a vector to be shifted. | |
5481 | Operand 2 is an integer shift amount in bits. | |
5482 | Operand 0 is where the resulting shifted vector is stored. | |
5483 | The output and input vectors should have the same modes. | |
5484 | ||
61abee65 | 5485 | @cindex @code{vec_shr_@var{m}} instruction pattern |
e29dfbf0 | 5486 | @item @samp{vec_shr_@var{m}} |
630ba2fd | 5487 | Whole vector right shift in bits, i.e.@: towards element 0. |
61abee65 | 5488 | Operand 1 is a vector to be shifted. |
759915ca | 5489 | Operand 2 is an integer shift amount in bits. |
61abee65 DN |
5490 | Operand 0 is where the resulting shifted vector is stored. |
5491 | The output and input vectors should have the same modes. | |
5492 | ||
8115817b UB |
5493 | @cindex @code{vec_pack_trunc_@var{m}} instruction pattern |
5494 | @item @samp{vec_pack_trunc_@var{m}} | |
5495 | Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 | |
5496 | are vectors of the same mode having N integral or floating point elements | |
0ee2ea09 | 5497 | of size S@. Operand 0 is the resulting vector in which 2*N elements of |
bd2d1b3d | 5498 | size S/2 are concatenated after narrowing them down using truncation. |
8115817b | 5499 | |
4714942e JJ |
5500 | @cindex @code{vec_pack_sbool_trunc_@var{m}} instruction pattern |
5501 | @item @samp{vec_pack_sbool_trunc_@var{m}} | |
5502 | Narrow and merge the elements of two vectors. Operands 1 and 2 are vectors | |
5503 | of the same type having N boolean elements. Operand 0 is the resulting | |
5504 | vector in which 2*N elements are concatenated. The last operand (operand 3) | |
5505 | is the number of elements in the output vector 2*N as a @code{CONST_INT}. | |
5506 | This instruction pattern is used when all the vector input and output | |
5507 | operands have the same scalar mode @var{m} and thus using | |
5508 | @code{vec_pack_trunc_@var{m}} would be ambiguous. | |
5509 | ||
89d67cca DN |
5510 | @cindex @code{vec_pack_ssat_@var{m}} instruction pattern |
5511 | @cindex @code{vec_pack_usat_@var{m}} instruction pattern | |
8115817b UB |
5512 | @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}} |
5513 | Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 | |
5514 | are vectors of the same mode having N integral elements of size S. | |
89d67cca | 5515 | Operand 0 is the resulting vector in which the elements of the two input |
8115817b UB |
5516 | vectors are concatenated after narrowing them down using signed/unsigned |
5517 | saturating arithmetic. | |
89d67cca | 5518 | |
d9987fb4 UB |
5519 | @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern |
5520 | @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern | |
5521 | @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}} | |
5522 | Narrow, convert to signed/unsigned integral type and merge the elements | |
5523 | of two vectors. Operands 1 and 2 are vectors of the same mode having N | |
0ee2ea09 | 5524 | floating point elements of size S@. Operand 0 is the resulting vector |
bd2d1b3d | 5525 | in which 2*N elements of size S/2 are concatenated. |
d9987fb4 | 5526 | |
1bda738b JJ |
5527 | @cindex @code{vec_packs_float_@var{m}} instruction pattern |
5528 | @cindex @code{vec_packu_float_@var{m}} instruction pattern | |
5529 | @item @samp{vec_packs_float_@var{m}}, @samp{vec_packu_float_@var{m}} | |
5530 | Narrow, convert to floating point type and merge the elements | |
5531 | of two vectors. Operands 1 and 2 are vectors of the same mode having N | |
5532 | signed/unsigned integral elements of size S@. Operand 0 is the resulting vector | |
bd2d1b3d | 5533 | in which 2*N elements of size S/2 are concatenated. |
1bda738b | 5534 | |
89d67cca DN |
5535 | @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern |
5536 | @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern | |
8115817b UB |
5537 | @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}} |
5538 | Extract and widen (promote) the high/low part of a vector of signed | |
5539 | integral or floating point elements. The input vector (operand 1) has N | |
0ee2ea09 | 5540 | elements of size S@. Widen (promote) the high/low elements of the vector |
8115817b UB |
5541 | using signed or floating point extension and place the resulting N/2 |
5542 | values of size 2*S in the output vector (operand 0). | |
5543 | ||
89d67cca DN |
5544 | @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern |
5545 | @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern | |
8115817b UB |
5546 | @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}} |
5547 | Extract and widen (promote) the high/low part of a vector of unsigned | |
5548 | integral elements. The input vector (operand 1) has N elements of size S. | |
5549 | Widen (promote) the high/low elements of the vector using zero extension and | |
5550 | place the resulting N/2 values of size 2*S in the output vector (operand 0). | |
89d67cca | 5551 | |
4714942e JJ |
5552 | @cindex @code{vec_unpacks_sbool_hi_@var{m}} instruction pattern |
5553 | @cindex @code{vec_unpacks_sbool_lo_@var{m}} instruction pattern | |
5554 | @item @samp{vec_unpacks_sbool_hi_@var{m}}, @samp{vec_unpacks_sbool_lo_@var{m}} | |
5555 | Extract the high/low part of a vector of boolean elements that have scalar | |
5556 | mode @var{m}. The input vector (operand 1) has N elements, the output | |
5557 | vector (operand 0) has N/2 elements. The last operand (operand 2) is the | |
5558 | number of elements of the input vector N as a @code{CONST_INT}. These | |
5559 | patterns are used if both the input and output vectors have the same scalar | |
5560 | mode @var{m} and thus using @code{vec_unpacks_hi_@var{m}} or | |
5561 | @code{vec_unpacks_lo_@var{m}} would be ambiguous. | |
5562 | ||
d9987fb4 UB |
5563 | @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern |
5564 | @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern | |
5565 | @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern | |
5566 | @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern | |
5567 | @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}} | |
5568 | @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}} | |
5569 | Extract, convert to floating point type and widen the high/low part of a | |
5570 | vector of signed/unsigned integral elements. The input vector (operand 1) | |
0ee2ea09 | 5571 | has N elements of size S@. Convert the high/low elements of the vector using |
d9987fb4 UB |
5572 | floating point conversion and place the resulting N/2 values of size 2*S in |
5573 | the output vector (operand 0). | |
5574 | ||
1bda738b JJ |
5575 | @cindex @code{vec_unpack_sfix_trunc_hi_@var{m}} instruction pattern |
5576 | @cindex @code{vec_unpack_sfix_trunc_lo_@var{m}} instruction pattern | |
5577 | @cindex @code{vec_unpack_ufix_trunc_hi_@var{m}} instruction pattern | |
5578 | @cindex @code{vec_unpack_ufix_trunc_lo_@var{m}} instruction pattern | |
5579 | @item @samp{vec_unpack_sfix_trunc_hi_@var{m}}, | |
5580 | @itemx @samp{vec_unpack_sfix_trunc_lo_@var{m}} | |
5581 | @itemx @samp{vec_unpack_ufix_trunc_hi_@var{m}} | |
5582 | @itemx @samp{vec_unpack_ufix_trunc_lo_@var{m}} | |
5583 | Extract, convert to signed/unsigned integer type and widen the high/low part of a | |
5584 | vector of floating point elements. The input vector (operand 1) | |
5585 | has N elements of size S@. Convert the high/low elements of the vector | |
5586 | to integers and place the resulting N/2 values of size 2*S in | |
5587 | the output vector (operand 0). | |
5588 | ||
89d67cca | 5589 | @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern |
3f30a9a6 | 5590 | @cindex @code{vec_widen_umult_lo_@var{m}} instruction pattern |
89d67cca DN |
5591 | @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern |
5592 | @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern | |
3f30a9a6 RH |
5593 | @cindex @code{vec_widen_umult_even_@var{m}} instruction pattern |
5594 | @cindex @code{vec_widen_umult_odd_@var{m}} instruction pattern | |
5595 | @cindex @code{vec_widen_smult_even_@var{m}} instruction pattern | |
5596 | @cindex @code{vec_widen_smult_odd_@var{m}} instruction pattern | |
d9987fb4 UB |
5597 | @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}} |
5598 | @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}} | |
3f30a9a6 RH |
5599 | @itemx @samp{vec_widen_umult_even_@var{m}}, @samp{vec_widen_umult_odd_@var{m}} |
5600 | @itemx @samp{vec_widen_smult_even_@var{m}}, @samp{vec_widen_smult_odd_@var{m}} | |
8115817b | 5601 | Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2) |
0ee2ea09 | 5602 | are vectors with N signed/unsigned elements of size S@. Multiply the high/low |
3f30a9a6 | 5603 | or even/odd elements of the two vectors, and put the N/2 products of size 2*S |
4a271b7e BM |
5604 | in the output vector (operand 0). A target shouldn't implement even/odd pattern |
5605 | pair if it is less efficient than lo/hi one. | |
89d67cca | 5606 | |
36ba4aae IR |
5607 | @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern |
5608 | @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern | |
5609 | @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern | |
5610 | @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern | |
5611 | @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}} | |
5612 | @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}} | |
5613 | Signed/Unsigned widening shift left. The first input (operand 1) is a vector | |
5614 | with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift | |
5615 | the high/low elements of operand 1, and put the N/2 results of size 2*S in the | |
5616 | output vector (operand 0). | |
5617 | ||
9fc9573f JH |
5618 | @cindex @code{vec_widen_saddl_hi_@var{m}} instruction pattern |
5619 | @cindex @code{vec_widen_saddl_lo_@var{m}} instruction pattern | |
5620 | @cindex @code{vec_widen_uaddl_hi_@var{m}} instruction pattern | |
5621 | @cindex @code{vec_widen_uaddl_lo_@var{m}} instruction pattern | |
5622 | @item @samp{vec_widen_uaddl_hi_@var{m}}, @samp{vec_widen_uaddl_lo_@var{m}} | |
5623 | @itemx @samp{vec_widen_saddl_hi_@var{m}}, @samp{vec_widen_saddl_lo_@var{m}} | |
5624 | Signed/Unsigned widening add long. Operands 1 and 2 are vectors with N | |
5625 | signed/unsigned elements of size S@. Add the high/low elements of 1 and 2 | |
5626 | together, widen the resulting elements and put the N/2 results of size 2*S in | |
5627 | the output vector (operand 0). | |
5628 | ||
5629 | @cindex @code{vec_widen_ssubl_hi_@var{m}} instruction pattern | |
5630 | @cindex @code{vec_widen_ssubl_lo_@var{m}} instruction pattern | |
5631 | @cindex @code{vec_widen_usubl_hi_@var{m}} instruction pattern | |
5632 | @cindex @code{vec_widen_usubl_lo_@var{m}} instruction pattern | |
5633 | @item @samp{vec_widen_usubl_hi_@var{m}}, @samp{vec_widen_usubl_lo_@var{m}} | |
5634 | @itemx @samp{vec_widen_ssubl_hi_@var{m}}, @samp{vec_widen_ssubl_lo_@var{m}} | |
5635 | Signed/Unsigned widening subtract long. Operands 1 and 2 are vectors with N | |
5636 | signed/unsigned elements of size S@. Subtract the high/low elements of 2 from | |
5637 | 1 and widen the resulting elements. Put the N/2 results of size 2*S in the | |
5638 | output vector (operand 0). | |
5639 | ||
7a6c31f0 RB |
5640 | @cindex @code{vec_addsub@var{m}3} instruction pattern |
5641 | @item @samp{vec_addsub@var{m}3} | |
5642 | Alternating subtract, add with even lanes doing subtract and odd | |
5643 | lanes doing addition. Operands 1 and 2 and the outout operand are vectors | |
5644 | with mode @var{m}. | |
5645 | ||
7d810646 RB |
5646 | @cindex @code{vec_fmaddsub@var{m}4} instruction pattern |
5647 | @item @samp{vec_fmaddsub@var{m}4} | |
5648 | Alternating multiply subtract, add with even lanes doing subtract and odd | |
5649 | lanes doing addition of the third operand to the multiplication result | |
5650 | of the first two operands. Operands 1, 2 and 3 and the outout operand are vectors | |
5651 | with mode @var{m}. | |
5652 | ||
5653 | @cindex @code{vec_fmsubadd@var{m}4} instruction pattern | |
5654 | @item @samp{vec_fmsubadd@var{m}4} | |
5655 | Alternating multiply add, subtract with even lanes doing addition and odd | |
5656 | lanes doing subtraction of the third operand to the multiplication result | |
5657 | of the first two operands. Operands 1, 2 and 3 and the outout operand are vectors | |
5658 | with mode @var{m}. | |
5659 | ||
7a6c31f0 RB |
5660 | These instructions are not allowed to @code{FAIL}. |
5661 | ||
03dda8e3 RK |
5662 | @cindex @code{mulhisi3} instruction pattern |
5663 | @item @samp{mulhisi3} | |
5664 | Multiply operands 1 and 2, which have mode @code{HImode}, and store | |
5665 | a @code{SImode} product in operand 0. | |
5666 | ||
5667 | @cindex @code{mulqihi3} instruction pattern | |
5668 | @cindex @code{mulsidi3} instruction pattern | |
5669 | @item @samp{mulqihi3}, @samp{mulsidi3} | |
5670 | Similar widening-multiplication instructions of other widths. | |
5671 | ||
5672 | @cindex @code{umulqihi3} instruction pattern | |
5673 | @cindex @code{umulhisi3} instruction pattern | |
5674 | @cindex @code{umulsidi3} instruction pattern | |
5675 | @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3} | |
5676 | Similar widening-multiplication instructions that do unsigned | |
5677 | multiplication. | |
5678 | ||
8b44057d BS |
5679 | @cindex @code{usmulqihi3} instruction pattern |
5680 | @cindex @code{usmulhisi3} instruction pattern | |
5681 | @cindex @code{usmulsidi3} instruction pattern | |
5682 | @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3} | |
5683 | Similar widening-multiplication instructions that interpret the first | |
5684 | operand as unsigned and the second operand as signed, then do a signed | |
5685 | multiplication. | |
5686 | ||
03dda8e3 | 5687 | @cindex @code{smul@var{m}3_highpart} instruction pattern |
759c58af | 5688 | @item @samp{smul@var{m}3_highpart} |
03dda8e3 RK |
5689 | Perform a signed multiplication of operands 1 and 2, which have mode |
5690 | @var{m}, and store the most significant half of the product in operand 0. | |
555fa354 RS |
5691 | The least significant half of the product is discarded. This may be |
5692 | represented in RTL using a @code{smul_highpart} RTX expression. | |
03dda8e3 RK |
5693 | |
5694 | @cindex @code{umul@var{m}3_highpart} instruction pattern | |
5695 | @item @samp{umul@var{m}3_highpart} | |
555fa354 RS |
5696 | Similar, but the multiplication is unsigned. This may be represented |
5697 | in RTL using an @code{umul_highpart} RTX expression. | |
03dda8e3 | 5698 | |
7f9844ca RS |
5699 | @cindex @code{madd@var{m}@var{n}4} instruction pattern |
5700 | @item @samp{madd@var{m}@var{n}4} | |
5701 | Multiply operands 1 and 2, sign-extend them to mode @var{n}, add | |
5702 | operand 3, and store the result in operand 0. Operands 1 and 2 | |
5703 | have mode @var{m} and operands 0 and 3 have mode @var{n}. | |
0f996086 | 5704 | Both modes must be integer or fixed-point modes and @var{n} must be twice |
7f9844ca RS |
5705 | the size of @var{m}. |
5706 | ||
5707 | In other words, @code{madd@var{m}@var{n}4} is like | |
5708 | @code{mul@var{m}@var{n}3} except that it also adds operand 3. | |
5709 | ||
5710 | These instructions are not allowed to @code{FAIL}. | |
5711 | ||
5712 | @cindex @code{umadd@var{m}@var{n}4} instruction pattern | |
5713 | @item @samp{umadd@var{m}@var{n}4} | |
5714 | Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication | |
5715 | operands instead of sign-extending them. | |
5716 | ||
0f996086 CF |
5717 | @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern |
5718 | @item @samp{ssmadd@var{m}@var{n}4} | |
5719 | Like @code{madd@var{m}@var{n}4}, but all involved operations must be | |
5720 | signed-saturating. | |
5721 | ||
5722 | @cindex @code{usmadd@var{m}@var{n}4} instruction pattern | |
5723 | @item @samp{usmadd@var{m}@var{n}4} | |
5724 | Like @code{umadd@var{m}@var{n}4}, but all involved operations must be | |
5725 | unsigned-saturating. | |
5726 | ||
14661f36 CF |
5727 | @cindex @code{msub@var{m}@var{n}4} instruction pattern |
5728 | @item @samp{msub@var{m}@var{n}4} | |
5729 | Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the | |
5730 | result from operand 3, and store the result in operand 0. Operands 1 and 2 | |
5731 | have mode @var{m} and operands 0 and 3 have mode @var{n}. | |
0f996086 | 5732 | Both modes must be integer or fixed-point modes and @var{n} must be twice |
14661f36 CF |
5733 | the size of @var{m}. |
5734 | ||
5735 | In other words, @code{msub@var{m}@var{n}4} is like | |
5736 | @code{mul@var{m}@var{n}3} except that it also subtracts the result | |
5737 | from operand 3. | |
5738 | ||
5739 | These instructions are not allowed to @code{FAIL}. | |
5740 | ||
5741 | @cindex @code{umsub@var{m}@var{n}4} instruction pattern | |
5742 | @item @samp{umsub@var{m}@var{n}4} | |
5743 | Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication | |
5744 | operands instead of sign-extending them. | |
5745 | ||
0f996086 CF |
5746 | @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern |
5747 | @item @samp{ssmsub@var{m}@var{n}4} | |
5748 | Like @code{msub@var{m}@var{n}4}, but all involved operations must be | |
5749 | signed-saturating. | |
5750 | ||
5751 | @cindex @code{usmsub@var{m}@var{n}4} instruction pattern | |
5752 | @item @samp{usmsub@var{m}@var{n}4} | |
5753 | Like @code{umsub@var{m}@var{n}4}, but all involved operations must be | |
5754 | unsigned-saturating. | |
5755 | ||
03dda8e3 RK |
5756 | @cindex @code{divmod@var{m}4} instruction pattern |
5757 | @item @samp{divmod@var{m}4} | |
5758 | Signed division that produces both a quotient and a remainder. | |
5759 | Operand 1 is divided by operand 2 to produce a quotient stored | |
5760 | in operand 0 and a remainder stored in operand 3. | |
5761 | ||
5762 | For machines with an instruction that produces both a quotient and a | |
5763 | remainder, provide a pattern for @samp{divmod@var{m}4} but do not | |
5764 | provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This | |
5765 | allows optimization in the relatively common case when both the quotient | |
5766 | and remainder are computed. | |
5767 | ||
5768 | If an instruction that just produces a quotient or just a remainder | |
5769 | exists and is more efficient than the instruction that produces both, | |
5770 | write the output routine of @samp{divmod@var{m}4} to call | |
5771 | @code{find_reg_note} and look for a @code{REG_UNUSED} note on the | |
5772 | quotient or remainder and generate the appropriate instruction. | |
5773 | ||
5774 | @cindex @code{udivmod@var{m}4} instruction pattern | |
5775 | @item @samp{udivmod@var{m}4} | |
5776 | Similar, but does unsigned division. | |
5777 | ||
273a2526 | 5778 | @anchor{shift patterns} |
03dda8e3 | 5779 | @cindex @code{ashl@var{m}3} instruction pattern |
0f996086 CF |
5780 | @cindex @code{ssashl@var{m}3} instruction pattern |
5781 | @cindex @code{usashl@var{m}3} instruction pattern | |
5782 | @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3} | |
03dda8e3 RK |
5783 | Arithmetic-shift operand 1 left by a number of bits specified by operand |
5784 | 2, and store the result in operand 0. Here @var{m} is the mode of | |
5785 | operand 0 and operand 1; operand 2's mode is specified by the | |
5786 | instruction pattern, and the compiler will convert the operand to that | |
78250306 JJ |
5787 | mode before generating the instruction. The shift or rotate expander |
5788 | or instruction pattern should explicitly specify the mode of the operand 2, | |
5789 | it should never be @code{VOIDmode}. The meaning of out-of-range shift | |
273a2526 | 5790 | counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}. |
71d46ca5 | 5791 | @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type. |
03dda8e3 RK |
5792 | |
5793 | @cindex @code{ashr@var{m}3} instruction pattern | |
5794 | @cindex @code{lshr@var{m}3} instruction pattern | |
5795 | @cindex @code{rotl@var{m}3} instruction pattern | |
5796 | @cindex @code{rotr@var{m}3} instruction pattern | |
5797 | @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3} | |
5798 | Other shift and rotate instructions, analogous to the | |
71d46ca5 MM |
5799 | @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type. |
5800 | ||
5801 | @cindex @code{vashl@var{m}3} instruction pattern | |
5802 | @cindex @code{vashr@var{m}3} instruction pattern | |
5803 | @cindex @code{vlshr@var{m}3} instruction pattern | |
5804 | @cindex @code{vrotl@var{m}3} instruction pattern | |
5805 | @cindex @code{vrotr@var{m}3} instruction pattern | |
5806 | @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3} | |
5807 | Vector shift and rotate instructions that take vectors as operand 2 | |
5808 | instead of a scalar type. | |
03dda8e3 | 5809 | |
0267732b RS |
5810 | @cindex @code{avg@var{m}3_floor} instruction pattern |
5811 | @cindex @code{uavg@var{m}3_floor} instruction pattern | |
5812 | @item @samp{avg@var{m}3_floor} | |
5813 | @itemx @samp{uavg@var{m}3_floor} | |
5814 | Signed and unsigned average instructions. These instructions add | |
5815 | operands 1 and 2 without truncation, divide the result by 2, | |
5816 | round towards -Inf, and store the result in operand 0. This is | |
5817 | equivalent to the C code: | |
5818 | @smallexample | |
5819 | narrow op0, op1, op2; | |
5820 | @dots{} | |
5821 | op0 = (narrow) (((wide) op1 + (wide) op2) >> 1); | |
5822 | @end smallexample | |
5823 | where the sign of @samp{narrow} determines whether this is a signed | |
5824 | or unsigned operation. | |
5825 | ||
5826 | @cindex @code{avg@var{m}3_ceil} instruction pattern | |
5827 | @cindex @code{uavg@var{m}3_ceil} instruction pattern | |
5828 | @item @samp{avg@var{m}3_ceil} | |
5829 | @itemx @samp{uavg@var{m}3_ceil} | |
5830 | Like @samp{avg@var{m}3_floor} and @samp{uavg@var{m}3_floor}, but round | |
5831 | towards +Inf. This is equivalent to the C code: | |
5832 | @smallexample | |
5833 | narrow op0, op1, op2; | |
5834 | @dots{} | |
5835 | op0 = (narrow) (((wide) op1 + (wide) op2 + 1) >> 1); | |
5836 | @end smallexample | |
5837 | ||
ac868f29 EB |
5838 | @cindex @code{bswap@var{m}2} instruction pattern |
5839 | @item @samp{bswap@var{m}2} | |
5840 | Reverse the order of bytes of operand 1 and store the result in operand 0. | |
5841 | ||
03dda8e3 | 5842 | @cindex @code{neg@var{m}2} instruction pattern |
0f996086 CF |
5843 | @cindex @code{ssneg@var{m}2} instruction pattern |
5844 | @cindex @code{usneg@var{m}2} instruction pattern | |
5845 | @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2} | |
03dda8e3 RK |
5846 | Negate operand 1 and store the result in operand 0. |
5847 | ||
481efdd9 EB |
5848 | @cindex @code{negv@var{m}3} instruction pattern |
5849 | @item @samp{negv@var{m}3} | |
5850 | Like @code{neg@var{m}2} but takes a @code{code_label} as operand 2 and | |
5851 | emits code to jump to it if signed overflow occurs during the negation. | |
5852 | ||
03dda8e3 RK |
5853 | @cindex @code{abs@var{m}2} instruction pattern |
5854 | @item @samp{abs@var{m}2} | |
5855 | Store the absolute value of operand 1 into operand 0. | |
5856 | ||
5857 | @cindex @code{sqrt@var{m}2} instruction pattern | |
5858 | @item @samp{sqrt@var{m}2} | |
a54a5997 RS |
5859 | Store the square root of operand 1 into operand 0. Both operands have |
5860 | mode @var{m}, which is a scalar or vector floating-point mode. | |
03dda8e3 | 5861 | |
a54a5997 | 5862 | This pattern is not allowed to @code{FAIL}. |
e7b489c8 | 5863 | |
ee62a5a6 RS |
5864 | @cindex @code{rsqrt@var{m}2} instruction pattern |
5865 | @item @samp{rsqrt@var{m}2} | |
5866 | Store the reciprocal of the square root of operand 1 into operand 0. | |
a54a5997 RS |
5867 | Both operands have mode @var{m}, which is a scalar or vector |
5868 | floating-point mode. | |
5869 | ||
ee62a5a6 RS |
5870 | On most architectures this pattern is only approximate, so either |
5871 | its C condition or the @code{TARGET_OPTAB_SUPPORTED_P} hook should | |
5872 | check for the appropriate math flags. (Using the C condition is | |
5873 | more direct, but using @code{TARGET_OPTAB_SUPPORTED_P} can be useful | |
5874 | if a target-specific built-in also uses the @samp{rsqrt@var{m}2} | |
5875 | pattern.) | |
5876 | ||
5877 | This pattern is not allowed to @code{FAIL}. | |
5878 | ||
17b98269 UB |
5879 | @cindex @code{fmod@var{m}3} instruction pattern |
5880 | @item @samp{fmod@var{m}3} | |
5881 | Store the remainder of dividing operand 1 by operand 2 into | |
a54a5997 RS |
5882 | operand 0, rounded towards zero to an integer. All operands have |
5883 | mode @var{m}, which is a scalar or vector floating-point mode. | |
17b98269 | 5884 | |
a54a5997 | 5885 | This pattern is not allowed to @code{FAIL}. |
17b98269 UB |
5886 | |
5887 | @cindex @code{remainder@var{m}3} instruction pattern | |
5888 | @item @samp{remainder@var{m}3} | |
5889 | Store the remainder of dividing operand 1 by operand 2 into | |
a54a5997 RS |
5890 | operand 0, rounded to the nearest integer. All operands have |
5891 | mode @var{m}, which is a scalar or vector floating-point mode. | |
5892 | ||
5893 | This pattern is not allowed to @code{FAIL}. | |
5894 | ||
5895 | @cindex @code{scalb@var{m}3} instruction pattern | |
5896 | @item @samp{scalb@var{m}3} | |
5897 | Raise @code{FLT_RADIX} to the power of operand 2, multiply it by | |
5898 | operand 1, and store the result in operand 0. All operands have | |
5899 | mode @var{m}, which is a scalar or vector floating-point mode. | |
17b98269 | 5900 | |
a54a5997 RS |
5901 | This pattern is not allowed to @code{FAIL}. |
5902 | ||
5903 | @cindex @code{ldexp@var{m}3} instruction pattern | |
5904 | @item @samp{ldexp@var{m}3} | |
5905 | Raise 2 to the power of operand 2, multiply it by operand 1, and store | |
5906 | the result in operand 0. Operands 0 and 1 have mode @var{m}, which is | |
5907 | a scalar or vector floating-point mode. Operand 2's mode has | |
5908 | the same number of elements as @var{m} and each element is wide | |
5909 | enough to store an @code{int}. The integers are signed. | |
5910 | ||
5911 | This pattern is not allowed to @code{FAIL}. | |
17b98269 | 5912 | |
e7b489c8 RS |
5913 | @cindex @code{cos@var{m}2} instruction pattern |
5914 | @item @samp{cos@var{m}2} | |
a54a5997 RS |
5915 | Store the cosine of operand 1 into operand 0. Both operands have |
5916 | mode @var{m}, which is a scalar or vector floating-point mode. | |
e7b489c8 | 5917 | |
a54a5997 | 5918 | This pattern is not allowed to @code{FAIL}. |
e7b489c8 RS |
5919 | |
5920 | @cindex @code{sin@var{m}2} instruction pattern | |
5921 | @item @samp{sin@var{m}2} | |
a54a5997 RS |
5922 | Store the sine of operand 1 into operand 0. Both operands have |
5923 | mode @var{m}, which is a scalar or vector floating-point mode. | |
e7b489c8 | 5924 | |
a54a5997 | 5925 | This pattern is not allowed to @code{FAIL}. |
e7b489c8 | 5926 | |
6d1f6aff OE |
5927 | @cindex @code{sincos@var{m}3} instruction pattern |
5928 | @item @samp{sincos@var{m}3} | |
6ba9e401 | 5929 | Store the cosine of operand 2 into operand 0 and the sine of |
a54a5997 RS |
5930 | operand 2 into operand 1. All operands have mode @var{m}, |
5931 | which is a scalar or vector floating-point mode. | |
6d1f6aff | 5932 | |
6d1f6aff OE |
5933 | Targets that can calculate the sine and cosine simultaneously can |
5934 | implement this pattern as opposed to implementing individual | |
5935 | @code{sin@var{m}2} and @code{cos@var{m}2} patterns. The @code{sin} | |
5936 | and @code{cos} built-in functions will then be expanded to the | |
5937 | @code{sincos@var{m}3} pattern, with one of the output values | |
5938 | left unused. | |
5939 | ||
a54a5997 RS |
5940 | @cindex @code{tan@var{m}2} instruction pattern |
5941 | @item @samp{tan@var{m}2} | |
5942 | Store the tangent of operand 1 into operand 0. Both operands have | |
5943 | mode @var{m}, which is a scalar or vector floating-point mode. | |
5944 | ||
5945 | This pattern is not allowed to @code{FAIL}. | |
5946 | ||
5947 | @cindex @code{asin@var{m}2} instruction pattern | |
5948 | @item @samp{asin@var{m}2} | |
5949 | Store the arc sine of operand 1 into operand 0. Both operands have | |
5950 | mode @var{m}, which is a scalar or vector floating-point mode. | |
5951 | ||
5952 | This pattern is not allowed to @code{FAIL}. | |
5953 | ||
5954 | @cindex @code{acos@var{m}2} instruction pattern | |
5955 | @item @samp{acos@var{m}2} | |
5956 | Store the arc cosine of operand 1 into operand 0. Both operands have | |
5957 | mode @var{m}, which is a scalar or vector floating-point mode. | |
5958 | ||
5959 | This pattern is not allowed to @code{FAIL}. | |
5960 | ||
5961 | @cindex @code{atan@var{m}2} instruction pattern | |
5962 | @item @samp{atan@var{m}2} | |
5963 | Store the arc tangent of operand 1 into operand 0. Both operands have | |
5964 | mode @var{m}, which is a scalar or vector floating-point mode. | |
5965 | ||
5966 | This pattern is not allowed to @code{FAIL}. | |
5967 | ||
4343f5e2 RFF |
5968 | @cindex @code{fegetround@var{m}} instruction pattern |
5969 | @item @samp{fegetround@var{m}} | |
5970 | Store the current machine floating-point rounding mode into operand 0. | |
5971 | Operand 0 has mode @var{m}, which is scalar. This pattern is used to | |
5972 | implement the @code{fegetround} function from the ISO C99 standard. | |
5973 | ||
5974 | @cindex @code{feclearexcept@var{m}} instruction pattern | |
5975 | @cindex @code{feraiseexcept@var{m}} instruction pattern | |
5976 | @item @samp{feclearexcept@var{m}} | |
5977 | @item @samp{feraiseexcept@var{m}} | |
5978 | Clears or raises the supported machine floating-point exceptions | |
5979 | represented by the bits in operand 1. Error status is stored as | |
5980 | nonzero value in operand 0. Both operands have mode @var{m}, which is | |
5981 | a scalar. These patterns are used to implement the | |
5982 | @code{feclearexcept} and @code{feraiseexcept} functions from the ISO | |
5983 | C99 standard. | |
5984 | ||
e7b489c8 RS |
5985 | @cindex @code{exp@var{m}2} instruction pattern |
5986 | @item @samp{exp@var{m}2} | |
a54a5997 RS |
5987 | Raise e (the base of natural logarithms) to the power of operand 1 |
5988 | and store the result in operand 0. Both operands have mode @var{m}, | |
5989 | which is a scalar or vector floating-point mode. | |
5990 | ||
5991 | This pattern is not allowed to @code{FAIL}. | |
5992 | ||
5993 | @cindex @code{expm1@var{m}2} instruction pattern | |
5994 | @item @samp{expm1@var{m}2} | |
5995 | Raise e (the base of natural logarithms) to the power of operand 1, | |
5996 | subtract 1, and store the result in operand 0. Both operands have | |
5997 | mode @var{m}, which is a scalar or vector floating-point mode. | |
5998 | ||
5999 | For inputs close to zero, the pattern is expected to be more | |
6000 | accurate than a separate @code{exp@var{m}2} and @code{sub@var{m}3} | |
6001 | would be. | |
6002 | ||
6003 | This pattern is not allowed to @code{FAIL}. | |
6004 | ||
6005 | @cindex @code{exp10@var{m}2} instruction pattern | |
6006 | @item @samp{exp10@var{m}2} | |
6007 | Raise 10 to the power of operand 1 and store the result in operand 0. | |
6008 | Both operands have mode @var{m}, which is a scalar or vector | |
6009 | floating-point mode. | |
6010 | ||
6011 | This pattern is not allowed to @code{FAIL}. | |
6012 | ||
6013 | @cindex @code{exp2@var{m}2} instruction pattern | |
6014 | @item @samp{exp2@var{m}2} | |
6015 | Raise 2 to the power of operand 1 and store the result in operand 0. | |
6016 | Both operands have mode @var{m}, which is a scalar or vector | |
6017 | floating-point mode. | |
e7b489c8 | 6018 | |
a54a5997 | 6019 | This pattern is not allowed to @code{FAIL}. |
e7b489c8 RS |
6020 | |
6021 | @cindex @code{log@var{m}2} instruction pattern | |
6022 | @item @samp{log@var{m}2} | |
a54a5997 RS |
6023 | Store the natural logarithm of operand 1 into operand 0. Both operands |
6024 | have mode @var{m}, which is a scalar or vector floating-point mode. | |
6025 | ||
6026 | This pattern is not allowed to @code{FAIL}. | |
6027 | ||
6028 | @cindex @code{log1p@var{m}2} instruction pattern | |
6029 | @item @samp{log1p@var{m}2} | |
6030 | Add 1 to operand 1, compute the natural logarithm, and store | |
6031 | the result in operand 0. Both operands have mode @var{m}, which is | |
6032 | a scalar or vector floating-point mode. | |
6033 | ||
6034 | For inputs close to zero, the pattern is expected to be more | |
6035 | accurate than a separate @code{add@var{m}3} and @code{log@var{m}2} | |
6036 | would be. | |
6037 | ||
6038 | This pattern is not allowed to @code{FAIL}. | |
6039 | ||
6040 | @cindex @code{log10@var{m}2} instruction pattern | |
6041 | @item @samp{log10@var{m}2} | |
6042 | Store the base-10 logarithm of operand 1 into operand 0. Both operands | |
6043 | have mode @var{m}, which is a scalar or vector floating-point mode. | |
6044 | ||
6045 | This pattern is not allowed to @code{FAIL}. | |
6046 | ||
6047 | @cindex @code{log2@var{m}2} instruction pattern | |
6048 | @item @samp{log2@var{m}2} | |
6049 | Store the base-2 logarithm of operand 1 into operand 0. Both operands | |
6050 | have mode @var{m}, which is a scalar or vector floating-point mode. | |
e7b489c8 | 6051 | |
a54a5997 RS |
6052 | This pattern is not allowed to @code{FAIL}. |
6053 | ||
6054 | @cindex @code{logb@var{m}2} instruction pattern | |
6055 | @item @samp{logb@var{m}2} | |
6056 | Store the base-@code{FLT_RADIX} logarithm of operand 1 into operand 0. | |
6057 | Both operands have mode @var{m}, which is a scalar or vector | |
6058 | floating-point mode. | |
6059 | ||
6060 | This pattern is not allowed to @code{FAIL}. | |
6061 | ||
6062 | @cindex @code{significand@var{m}2} instruction pattern | |
6063 | @item @samp{significand@var{m}2} | |
6064 | Store the significand of floating-point operand 1 in operand 0. | |
6065 | Both operands have mode @var{m}, which is a scalar or vector | |
6066 | floating-point mode. | |
6067 | ||
6068 | This pattern is not allowed to @code{FAIL}. | |
03dda8e3 | 6069 | |
b5e01d4b RS |
6070 | @cindex @code{pow@var{m}3} instruction pattern |
6071 | @item @samp{pow@var{m}3} | |
6072 | Store the value of operand 1 raised to the exponent operand 2 | |
a54a5997 RS |
6073 | into operand 0. All operands have mode @var{m}, which is a scalar |
6074 | or vector floating-point mode. | |
b5e01d4b | 6075 | |
a54a5997 | 6076 | This pattern is not allowed to @code{FAIL}. |
b5e01d4b RS |
6077 | |
6078 | @cindex @code{atan2@var{m}3} instruction pattern | |
6079 | @item @samp{atan2@var{m}3} | |
6080 | Store the arc tangent (inverse tangent) of operand 1 divided by | |
6081 | operand 2 into operand 0, using the signs of both arguments to | |
a54a5997 RS |
6082 | determine the quadrant of the result. All operands have mode |
6083 | @var{m}, which is a scalar or vector floating-point mode. | |
b5e01d4b | 6084 | |
a54a5997 | 6085 | This pattern is not allowed to @code{FAIL}. |
b5e01d4b | 6086 | |
4977bab6 ZW |
6087 | @cindex @code{floor@var{m}2} instruction pattern |
6088 | @item @samp{floor@var{m}2} | |
a54a5997 RS |
6089 | Store the largest integral value not greater than operand 1 in operand 0. |
6090 | Both operands have mode @var{m}, which is a scalar or vector | |
0d2f700f JM |
6091 | floating-point mode. If @option{-ffp-int-builtin-inexact} is in |
6092 | effect, the ``inexact'' exception may be raised for noninteger | |
6093 | operands; otherwise, it may not. | |
4977bab6 | 6094 | |
a54a5997 | 6095 | This pattern is not allowed to @code{FAIL}. |
4977bab6 | 6096 | |
10553f10 UB |
6097 | @cindex @code{btrunc@var{m}2} instruction pattern |
6098 | @item @samp{btrunc@var{m}2} | |
a54a5997 RS |
6099 | Round operand 1 to an integer, towards zero, and store the result in |
6100 | operand 0. Both operands have mode @var{m}, which is a scalar or | |
0d2f700f JM |
6101 | vector floating-point mode. If @option{-ffp-int-builtin-inexact} is |
6102 | in effect, the ``inexact'' exception may be raised for noninteger | |
6103 | operands; otherwise, it may not. | |
4977bab6 | 6104 | |
a54a5997 | 6105 | This pattern is not allowed to @code{FAIL}. |
4977bab6 ZW |
6106 | |
6107 | @cindex @code{round@var{m}2} instruction pattern | |
6108 | @item @samp{round@var{m}2} | |
a54a5997 RS |
6109 | Round operand 1 to the nearest integer, rounding away from zero in the |
6110 | event of a tie, and store the result in operand 0. Both operands have | |
0d2f700f JM |
6111 | mode @var{m}, which is a scalar or vector floating-point mode. If |
6112 | @option{-ffp-int-builtin-inexact} is in effect, the ``inexact'' | |
6113 | exception may be raised for noninteger operands; otherwise, it may | |
6114 | not. | |
4977bab6 | 6115 | |
a54a5997 | 6116 | This pattern is not allowed to @code{FAIL}. |
4977bab6 ZW |
6117 | |
6118 | @cindex @code{ceil@var{m}2} instruction pattern | |
6119 | @item @samp{ceil@var{m}2} | |
a54a5997 RS |
6120 | Store the smallest integral value not less than operand 1 in operand 0. |
6121 | Both operands have mode @var{m}, which is a scalar or vector | |
0d2f700f JM |
6122 | floating-point mode. If @option{-ffp-int-builtin-inexact} is in |
6123 | effect, the ``inexact'' exception may be raised for noninteger | |
6124 | operands; otherwise, it may not. | |
4977bab6 | 6125 | |
a54a5997 | 6126 | This pattern is not allowed to @code{FAIL}. |
4977bab6 ZW |
6127 | |
6128 | @cindex @code{nearbyint@var{m}2} instruction pattern | |
6129 | @item @samp{nearbyint@var{m}2} | |
a54a5997 RS |
6130 | Round operand 1 to an integer, using the current rounding mode, and |
6131 | store the result in operand 0. Do not raise an inexact condition when | |
6132 | the result is different from the argument. Both operands have mode | |
6133 | @var{m}, which is a scalar or vector floating-point mode. | |
4977bab6 | 6134 | |
a54a5997 | 6135 | This pattern is not allowed to @code{FAIL}. |
4977bab6 | 6136 | |
10553f10 UB |
6137 | @cindex @code{rint@var{m}2} instruction pattern |
6138 | @item @samp{rint@var{m}2} | |
a54a5997 RS |
6139 | Round operand 1 to an integer, using the current rounding mode, and |
6140 | store the result in operand 0. Raise an inexact condition when | |
6141 | the result is different from the argument. Both operands have mode | |
6142 | @var{m}, which is a scalar or vector floating-point mode. | |
10553f10 | 6143 | |
a54a5997 | 6144 | This pattern is not allowed to @code{FAIL}. |
10553f10 | 6145 | |
bb7f0423 RG |
6146 | @cindex @code{lrint@var{m}@var{n}2} |
6147 | @item @samp{lrint@var{m}@var{n}2} | |
6148 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6149 | point mode @var{n} as a signed number according to the current | |
6150 | rounding mode and store in operand 0 (which has mode @var{n}). | |
6151 | ||
4d81bf84 | 6152 | @cindex @code{lround@var{m}@var{n}2} |
e0d4c0b3 | 6153 | @item @samp{lround@var{m}@var{n}2} |
4d81bf84 RG |
6154 | Convert operand 1 (valid for floating point mode @var{m}) to fixed |
6155 | point mode @var{n} as a signed number rounding to nearest and away | |
6156 | from zero and store in operand 0 (which has mode @var{n}). | |
6157 | ||
c3a4177f | 6158 | @cindex @code{lfloor@var{m}@var{n}2} |
e0d4c0b3 | 6159 | @item @samp{lfloor@var{m}@var{n}2} |
c3a4177f RG |
6160 | Convert operand 1 (valid for floating point mode @var{m}) to fixed |
6161 | point mode @var{n} as a signed number rounding down and store in | |
6162 | operand 0 (which has mode @var{n}). | |
6163 | ||
6164 | @cindex @code{lceil@var{m}@var{n}2} | |
e0d4c0b3 | 6165 | @item @samp{lceil@var{m}@var{n}2} |
c3a4177f RG |
6166 | Convert operand 1 (valid for floating point mode @var{m}) to fixed |
6167 | point mode @var{n} as a signed number rounding up and store in | |
6168 | operand 0 (which has mode @var{n}). | |
6169 | ||
d35a40fc DE |
6170 | @cindex @code{copysign@var{m}3} instruction pattern |
6171 | @item @samp{copysign@var{m}3} | |
6172 | Store a value with the magnitude of operand 1 and the sign of operand | |
a54a5997 RS |
6173 | 2 into operand 0. All operands have mode @var{m}, which is a scalar or |
6174 | vector floating-point mode. | |
d35a40fc | 6175 | |
a54a5997 | 6176 | This pattern is not allowed to @code{FAIL}. |
d35a40fc | 6177 | |
cb369975 TC |
6178 | @cindex @code{xorsign@var{m}3} instruction pattern |
6179 | @item @samp{xorsign@var{m}3} | |
6180 | Equivalent to @samp{op0 = op1 * copysign (1.0, op2)}: store a value with | |
6181 | the magnitude of operand 1 and the sign of operand 2 into operand 0. | |
6182 | All operands have mode @var{m}, which is a scalar or vector | |
6183 | floating-point mode. | |
6184 | ||
6185 | This pattern is not allowed to @code{FAIL}. | |
6186 | ||
3ed472af TC |
6187 | @cindex @code{cadd90@var{m}3} instruction pattern |
6188 | @item @samp{cadd90@var{m}3} | |
6189 | Perform vector add and subtract on even/odd number pairs. The operation being | |
6190 | matched is semantically described as | |
6191 | ||
6192 | @smallexample | |
6193 | for (int i = 0; i < N; i += 2) | |
6194 | @{ | |
6195 | c[i] = a[i] - b[i+1]; | |
6196 | c[i+1] = a[i+1] + b[i]; | |
6197 | @} | |
6198 | @end smallexample | |
6199 | ||
6200 | This operation is semantically equivalent to performing a vector addition of | |
6201 | complex numbers in operand 1 with operand 2 rotated by 90 degrees around | |
6202 | the argand plane and storing the result in operand 0. | |
6203 | ||
6204 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6205 | the imaginary part in the odd lanes. | |
6206 | ||
6207 | The operation is only supported for vector modes @var{m}. | |
6208 | ||
6209 | This pattern is not allowed to @code{FAIL}. | |
6210 | ||
6211 | @cindex @code{cadd270@var{m}3} instruction pattern | |
6212 | @item @samp{cadd270@var{m}3} | |
6213 | Perform vector add and subtract on even/odd number pairs. The operation being | |
6214 | matched is semantically described as | |
6215 | ||
6216 | @smallexample | |
6217 | for (int i = 0; i < N; i += 2) | |
6218 | @{ | |
6219 | c[i] = a[i] + b[i+1]; | |
6220 | c[i+1] = a[i+1] - b[i]; | |
6221 | @} | |
6222 | @end smallexample | |
6223 | ||
6224 | This operation is semantically equivalent to performing a vector addition of | |
6225 | complex numbers in operand 1 with operand 2 rotated by 270 degrees around | |
6226 | the argand plane and storing the result in operand 0. | |
6227 | ||
6228 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6229 | the imaginary part in the odd lanes. | |
6230 | ||
6231 | The operation is only supported for vector modes @var{m}. | |
6232 | ||
6233 | This pattern is not allowed to @code{FAIL}. | |
6234 | ||
31fac318 TC |
6235 | @cindex @code{cmla@var{m}4} instruction pattern |
6236 | @item @samp{cmla@var{m}4} | |
6237 | Perform a vector multiply and accumulate that is semantically the same as | |
6238 | a multiply and accumulate of complex numbers. | |
6239 | ||
6240 | @smallexample | |
55d83cdf TC |
6241 | complex TYPE op0[N]; |
6242 | complex TYPE op1[N]; | |
6243 | complex TYPE op2[N]; | |
6244 | complex TYPE op3[N]; | |
31fac318 TC |
6245 | for (int i = 0; i < N; i += 1) |
6246 | @{ | |
55d83cdf | 6247 | op0[i] = op1[i] * op2[i] + op3[i]; |
31fac318 TC |
6248 | @} |
6249 | @end smallexample | |
6250 | ||
6251 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6252 | the imaginary part in the odd lanes. | |
6253 | ||
6254 | The operation is only supported for vector modes @var{m}. | |
6255 | ||
6256 | This pattern is not allowed to @code{FAIL}. | |
6257 | ||
6258 | @cindex @code{cmla_conj@var{m}4} instruction pattern | |
6259 | @item @samp{cmla_conj@var{m}4} | |
6260 | Perform a vector multiply by conjugate and accumulate that is semantically | |
6261 | the same as a multiply and accumulate of complex numbers where the second | |
6262 | multiply arguments is conjugated. | |
6263 | ||
6264 | @smallexample | |
55d83cdf TC |
6265 | complex TYPE op0[N]; |
6266 | complex TYPE op1[N]; | |
6267 | complex TYPE op2[N]; | |
6268 | complex TYPE op3[N]; | |
31fac318 TC |
6269 | for (int i = 0; i < N; i += 1) |
6270 | @{ | |
55d83cdf | 6271 | op0[i] = op1[i] * conj (op2[i]) + op3[i]; |
31fac318 TC |
6272 | @} |
6273 | @end smallexample | |
6274 | ||
6275 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6276 | the imaginary part in the odd lanes. | |
6277 | ||
6278 | The operation is only supported for vector modes @var{m}. | |
6279 | ||
6280 | This pattern is not allowed to @code{FAIL}. | |
6281 | ||
478e571a TC |
6282 | @cindex @code{cmls@var{m}4} instruction pattern |
6283 | @item @samp{cmls@var{m}4} | |
6284 | Perform a vector multiply and subtract that is semantically the same as | |
6285 | a multiply and subtract of complex numbers. | |
6286 | ||
6287 | @smallexample | |
55d83cdf TC |
6288 | complex TYPE op0[N]; |
6289 | complex TYPE op1[N]; | |
6290 | complex TYPE op2[N]; | |
6291 | complex TYPE op3[N]; | |
478e571a TC |
6292 | for (int i = 0; i < N; i += 1) |
6293 | @{ | |
55d83cdf | 6294 | op0[i] = op1[i] * op2[i] - op3[i]; |
478e571a TC |
6295 | @} |
6296 | @end smallexample | |
6297 | ||
6298 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6299 | the imaginary part in the odd lanes. | |
6300 | ||
6301 | The operation is only supported for vector modes @var{m}. | |
6302 | ||
6303 | This pattern is not allowed to @code{FAIL}. | |
6304 | ||
6305 | @cindex @code{cmls_conj@var{m}4} instruction pattern | |
6306 | @item @samp{cmls_conj@var{m}4} | |
6307 | Perform a vector multiply by conjugate and subtract that is semantically | |
6308 | the same as a multiply and subtract of complex numbers where the second | |
6309 | multiply arguments is conjugated. | |
6310 | ||
6311 | @smallexample | |
55d83cdf TC |
6312 | complex TYPE op0[N]; |
6313 | complex TYPE op1[N]; | |
6314 | complex TYPE op2[N]; | |
6315 | complex TYPE op3[N]; | |
478e571a TC |
6316 | for (int i = 0; i < N; i += 1) |
6317 | @{ | |
55d83cdf | 6318 | op0[i] = op1[i] * conj (op2[i]) - op3[i]; |
478e571a TC |
6319 | @} |
6320 | @end smallexample | |
6321 | ||
6322 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6323 | the imaginary part in the odd lanes. | |
6324 | ||
6325 | The operation is only supported for vector modes @var{m}. | |
6326 | ||
6327 | This pattern is not allowed to @code{FAIL}. | |
6328 | ||
e09173d8 TC |
6329 | @cindex @code{cmul@var{m}4} instruction pattern |
6330 | @item @samp{cmul@var{m}4} | |
6331 | Perform a vector multiply that is semantically the same as multiply of | |
6332 | complex numbers. | |
6333 | ||
6334 | @smallexample | |
55d83cdf TC |
6335 | complex TYPE op0[N]; |
6336 | complex TYPE op1[N]; | |
6337 | complex TYPE op2[N]; | |
e09173d8 TC |
6338 | for (int i = 0; i < N; i += 1) |
6339 | @{ | |
55d83cdf | 6340 | op0[i] = op1[i] * op2[i]; |
e09173d8 TC |
6341 | @} |
6342 | @end smallexample | |
6343 | ||
6344 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6345 | the imaginary part in the odd lanes. | |
6346 | ||
6347 | The operation is only supported for vector modes @var{m}. | |
6348 | ||
6349 | This pattern is not allowed to @code{FAIL}. | |
6350 | ||
6351 | @cindex @code{cmul_conj@var{m}4} instruction pattern | |
6352 | @item @samp{cmul_conj@var{m}4} | |
6353 | Perform a vector multiply by conjugate that is semantically the same as a | |
6354 | multiply of complex numbers where the second multiply arguments is conjugated. | |
6355 | ||
6356 | @smallexample | |
55d83cdf TC |
6357 | complex TYPE op0[N]; |
6358 | complex TYPE op1[N]; | |
6359 | complex TYPE op2[N]; | |
e09173d8 TC |
6360 | for (int i = 0; i < N; i += 1) |
6361 | @{ | |
55d83cdf | 6362 | op0[i] = op1[i] * conj (op2[i]); |
e09173d8 TC |
6363 | @} |
6364 | @end smallexample | |
6365 | ||
6366 | In GCC lane ordering the real part of the number must be in the even lanes with | |
6367 | the imaginary part in the odd lanes. | |
6368 | ||
6369 | The operation is only supported for vector modes @var{m}. | |
6370 | ||
6371 | This pattern is not allowed to @code{FAIL}. | |
6372 | ||
03dda8e3 RK |
6373 | @cindex @code{ffs@var{m}2} instruction pattern |
6374 | @item @samp{ffs@var{m}2} | |
6375 | Store into operand 0 one plus the index of the least significant 1-bit | |
a54a5997 | 6376 | of operand 1. If operand 1 is zero, store zero. |
03dda8e3 | 6377 | |
a54a5997 RS |
6378 | @var{m} is either a scalar or vector integer mode. When it is a scalar, |
6379 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6380 | integer mode is suitable for the target. The compiler will insert | |
6381 | conversion instructions as necessary (typically to convert the result | |
6382 | to the same width as @code{int}). When @var{m} is a vector, both | |
6383 | operands must have mode @var{m}. | |
6384 | ||
6385 | This pattern is not allowed to @code{FAIL}. | |
03dda8e3 | 6386 | |
e7a45277 KT |
6387 | @cindex @code{clrsb@var{m}2} instruction pattern |
6388 | @item @samp{clrsb@var{m}2} | |
6389 | Count leading redundant sign bits. | |
6390 | Store into operand 0 the number of redundant sign bits in operand 1, starting | |
6391 | at the most significant bit position. | |
6392 | A redundant sign bit is defined as any sign bit after the first. As such, | |
6393 | this count will be one less than the count of leading sign bits. | |
6394 | ||
a54a5997 RS |
6395 | @var{m} is either a scalar or vector integer mode. When it is a scalar, |
6396 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6397 | integer mode is suitable for the target. The compiler will insert | |
6398 | conversion instructions as necessary (typically to convert the result | |
6399 | to the same width as @code{int}). When @var{m} is a vector, both | |
6400 | operands must have mode @var{m}. | |
6401 | ||
6402 | This pattern is not allowed to @code{FAIL}. | |
6403 | ||
2928cd7a RH |
6404 | @cindex @code{clz@var{m}2} instruction pattern |
6405 | @item @samp{clz@var{m}2} | |
e7a45277 KT |
6406 | Store into operand 0 the number of leading 0-bits in operand 1, starting |
6407 | at the most significant bit position. If operand 1 is 0, the | |
2a6627c2 JN |
6408 | @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if |
6409 | the result is undefined or has a useful value. | |
a54a5997 RS |
6410 | |
6411 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6412 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6413 | integer mode is suitable for the target. The compiler will insert | |
6414 | conversion instructions as necessary (typically to convert the result | |
6415 | to the same width as @code{int}). When @var{m} is a vector, both | |
6416 | operands must have mode @var{m}. | |
6417 | ||
6418 | This pattern is not allowed to @code{FAIL}. | |
2928cd7a RH |
6419 | |
6420 | @cindex @code{ctz@var{m}2} instruction pattern | |
6421 | @item @samp{ctz@var{m}2} | |
e7a45277 KT |
6422 | Store into operand 0 the number of trailing 0-bits in operand 1, starting |
6423 | at the least significant bit position. If operand 1 is 0, the | |
2a6627c2 JN |
6424 | @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if |
6425 | the result is undefined or has a useful value. | |
a54a5997 RS |
6426 | |
6427 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6428 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6429 | integer mode is suitable for the target. The compiler will insert | |
6430 | conversion instructions as necessary (typically to convert the result | |
6431 | to the same width as @code{int}). When @var{m} is a vector, both | |
6432 | operands must have mode @var{m}. | |
6433 | ||
6434 | This pattern is not allowed to @code{FAIL}. | |
2928cd7a RH |
6435 | |
6436 | @cindex @code{popcount@var{m}2} instruction pattern | |
6437 | @item @samp{popcount@var{m}2} | |
a54a5997 RS |
6438 | Store into operand 0 the number of 1-bits in operand 1. |
6439 | ||
6440 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6441 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6442 | integer mode is suitable for the target. The compiler will insert | |
6443 | conversion instructions as necessary (typically to convert the result | |
6444 | to the same width as @code{int}). When @var{m} is a vector, both | |
6445 | operands must have mode @var{m}. | |
6446 | ||
6447 | This pattern is not allowed to @code{FAIL}. | |
2928cd7a RH |
6448 | |
6449 | @cindex @code{parity@var{m}2} instruction pattern | |
6450 | @item @samp{parity@var{m}2} | |
e7a45277 | 6451 | Store into operand 0 the parity of operand 1, i.e.@: the number of 1-bits |
a54a5997 RS |
6452 | in operand 1 modulo 2. |
6453 | ||
6454 | @var{m} is either a scalar or vector integer mode. When it is a scalar, | |
6455 | operand 1 has mode @var{m} but operand 0 can have whatever scalar | |
6456 | integer mode is suitable for the target. The compiler will insert | |
6457 | conversion instructions as necessary (typically to convert the result | |
6458 | to the same width as @code{int}). When @var{m} is a vector, both | |
6459 | operands must have mode @var{m}. | |
6460 | ||
6461 | This pattern is not allowed to @code{FAIL}. | |
2928cd7a | 6462 | |
03dda8e3 RK |
6463 | @cindex @code{one_cmpl@var{m}2} instruction pattern |
6464 | @item @samp{one_cmpl@var{m}2} | |
6465 | Store the bitwise-complement of operand 1 into operand 0. | |
6466 | ||
76715c32 AS |
6467 | @cindex @code{cpymem@var{m}} instruction pattern |
6468 | @item @samp{cpymem@var{m}} | |
6469 | Block copy instruction. The destination and source blocks of memory | |
beed8fc0 AO |
6470 | are the first two operands, and both are @code{mem:BLK}s with an |
6471 | address in mode @code{Pmode}. | |
e5e809f4 | 6472 | |
76715c32 | 6473 | The number of bytes to copy is the third operand, in mode @var{m}. |
5689294c | 6474 | Usually, you specify @code{Pmode} for @var{m}. However, if you can |
e5e809f4 | 6475 | generate better code knowing the range of valid lengths is smaller than |
5689294c L |
6476 | those representable in a full Pmode pointer, you should provide |
6477 | a pattern with a | |
e5e809f4 JL |
6478 | mode corresponding to the range of values you can handle efficiently |
6479 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
5689294c | 6480 | that appear negative) and also a pattern with @code{Pmode}. |
03dda8e3 RK |
6481 | |
6482 | The fourth operand is the known shared alignment of the source and | |
6483 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
6484 | compiler knows that both source and destination are word-aligned, | |
6485 | it may provide the value 4 for this operand. | |
6486 | ||
079a182e JH |
6487 | Optional operands 5 and 6 specify expected alignment and size of block |
6488 | respectively. The expected alignment differs from alignment in operand 4 | |
6489 | in a way that the blocks are not required to be aligned according to it in | |
9946ca2d RA |
6490 | all cases. This expected alignment is also in bytes, just like operand 4. |
6491 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
079a182e | 6492 | |
76715c32 | 6493 | Descriptions of multiple @code{cpymem@var{m}} patterns can only be |
4693911f | 6494 | beneficial if the patterns for smaller modes have fewer restrictions |
8c01d9b6 | 6495 | on their first, second and fourth operands. Note that the mode @var{m} |
76715c32 AS |
6496 | in @code{cpymem@var{m}} does not impose any restriction on the mode of |
6497 | individually copied data units in the block. | |
8c01d9b6 | 6498 | |
76715c32 AS |
6499 | The @code{cpymem@var{m}} patterns need not give special consideration |
6500 | to the possibility that the source and destination strings might | |
6501 | overlap. These patterns are used to do inline expansion of | |
6502 | @code{__builtin_memcpy}. | |
03dda8e3 | 6503 | |
02e3025e AS |
6504 | @cindex @code{movmem@var{m}} instruction pattern |
6505 | @item @samp{movmem@var{m}} | |
6506 | Block move instruction. The destination and source blocks of memory | |
6507 | are the first two operands, and both are @code{mem:BLK}s with an | |
6508 | address in mode @code{Pmode}. | |
6509 | ||
6510 | The number of bytes to copy is the third operand, in mode @var{m}. | |
6511 | Usually, you specify @code{Pmode} for @var{m}. However, if you can | |
6512 | generate better code knowing the range of valid lengths is smaller than | |
6513 | those representable in a full Pmode pointer, you should provide | |
6514 | a pattern with a | |
6515 | mode corresponding to the range of values you can handle efficiently | |
6516 | (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers | |
6517 | that appear negative) and also a pattern with @code{Pmode}. | |
6518 | ||
6519 | The fourth operand is the known shared alignment of the source and | |
6520 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
6521 | compiler knows that both source and destination are word-aligned, | |
6522 | it may provide the value 4 for this operand. | |
6523 | ||
6524 | Optional operands 5 and 6 specify expected alignment and size of block | |
6525 | respectively. The expected alignment differs from alignment in operand 4 | |
6526 | in a way that the blocks are not required to be aligned according to it in | |
6527 | all cases. This expected alignment is also in bytes, just like operand 4. | |
6528 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
6529 | ||
6530 | Descriptions of multiple @code{movmem@var{m}} patterns can only be | |
6531 | beneficial if the patterns for smaller modes have fewer restrictions | |
6532 | on their first, second and fourth operands. Note that the mode @var{m} | |
6533 | in @code{movmem@var{m}} does not impose any restriction on the mode of | |
6534 | individually copied data units in the block. | |
6535 | ||
6536 | The @code{movmem@var{m}} patterns must correctly handle the case where | |
6537 | the source and destination strings overlap. These patterns are used to | |
6538 | do inline expansion of @code{__builtin_memmove}. | |
6539 | ||
beed8fc0 AO |
6540 | @cindex @code{movstr} instruction pattern |
6541 | @item @samp{movstr} | |
6542 | String copy instruction, with @code{stpcpy} semantics. Operand 0 is | |
6543 | an output operand in mode @code{Pmode}. The addresses of the | |
6544 | destination and source strings are operands 1 and 2, and both are | |
6545 | @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of | |
6546 | the expansion of this pattern should store in operand 0 the address in | |
6547 | which the @code{NUL} terminator was stored in the destination string. | |
6548 | ||
2b4f0b89 | 6549 | This pattern has also several optional operands that are same as in |
3918b108 JH |
6550 | @code{setmem}. |
6551 | ||
57e84f18 AS |
6552 | @cindex @code{setmem@var{m}} instruction pattern |
6553 | @item @samp{setmem@var{m}} | |
6554 | Block set instruction. The destination string is the first operand, | |
beed8fc0 | 6555 | given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The |
57e84f18 AS |
6556 | number of bytes to set is the second operand, in mode @var{m}. The value to |
6557 | initialize the memory with is the third operand. Targets that only support the | |
6558 | clearing of memory should reject any value that is not the constant 0. See | |
76715c32 | 6559 | @samp{cpymem@var{m}} for a discussion of the choice of mode. |
03dda8e3 | 6560 | |
57e84f18 | 6561 | The fourth operand is the known alignment of the destination, in the form |
03dda8e3 RK |
6562 | of a @code{const_int} rtx. Thus, if the compiler knows that the |
6563 | destination is word-aligned, it may provide the value 4 for this | |
6564 | operand. | |
6565 | ||
079a182e JH |
6566 | Optional operands 5 and 6 specify expected alignment and size of block |
6567 | respectively. The expected alignment differs from alignment in operand 4 | |
6568 | in a way that the blocks are not required to be aligned according to it in | |
9946ca2d RA |
6569 | all cases. This expected alignment is also in bytes, just like operand 4. |
6570 | Expected size, when unknown, is set to @code{(const_int -1)}. | |
3918b108 | 6571 | Operand 7 is the minimal size of the block and operand 8 is the |
67914693 SL |
6572 | maximal size of the block (NULL if it cannot be represented as CONST_INT). |
6573 | Operand 9 is the probable maximal size (i.e.@: we cannot rely on it for | |
630ba2fd SB |
6574 | correctness, but it can be used for choosing proper code sequence for a |
6575 | given size). | |
079a182e | 6576 | |
76715c32 | 6577 | The use for multiple @code{setmem@var{m}} is as for @code{cpymem@var{m}}. |
8c01d9b6 | 6578 | |
40c1d5f8 AS |
6579 | @cindex @code{cmpstrn@var{m}} instruction pattern |
6580 | @item @samp{cmpstrn@var{m}} | |
358b8f01 | 6581 | String compare instruction, with five operands. Operand 0 is the output; |
03dda8e3 | 6582 | it has mode @var{m}. The remaining four operands are like the operands |
76715c32 | 6583 | of @samp{cpymem@var{m}}. The two memory blocks specified are compared |
5cc2f4f3 KG |
6584 | byte by byte in lexicographic order starting at the beginning of each |
6585 | string. The instruction is not allowed to prefetch more than one byte | |
6586 | at a time since either string may end in the first byte and reading past | |
6587 | that may access an invalid page or segment and cause a fault. The | |
9b0f6f5e NC |
6588 | comparison terminates early if the fetched bytes are different or if |
6589 | they are equal to zero. The effect of the instruction is to store a | |
6590 | value in operand 0 whose sign indicates the result of the comparison. | |
03dda8e3 | 6591 | |
40c1d5f8 AS |
6592 | @cindex @code{cmpstr@var{m}} instruction pattern |
6593 | @item @samp{cmpstr@var{m}} | |
6594 | String compare instruction, without known maximum length. Operand 0 is the | |
6595 | output; it has mode @var{m}. The second and third operand are the blocks of | |
6596 | memory to be compared; both are @code{mem:BLK} with an address in mode | |
6597 | @code{Pmode}. | |
6598 | ||
6599 | The fourth operand is the known shared alignment of the source and | |
6600 | destination, in the form of a @code{const_int} rtx. Thus, if the | |
6601 | compiler knows that both source and destination are word-aligned, | |
6602 | it may provide the value 4 for this operand. | |
6603 | ||
6604 | The two memory blocks specified are compared byte by byte in lexicographic | |
6605 | order starting at the beginning of each string. The instruction is not allowed | |
6606 | to prefetch more than one byte at a time since either string may end in the | |
6607 | first byte and reading past that may access an invalid page or segment and | |
9b0f6f5e NC |
6608 | cause a fault. The comparison will terminate when the fetched bytes |
6609 | are different or if they are equal to zero. The effect of the | |
6610 | instruction is to store a value in operand 0 whose sign indicates the | |
6611 | result of the comparison. | |
40c1d5f8 | 6612 | |
358b8f01 JJ |
6613 | @cindex @code{cmpmem@var{m}} instruction pattern |
6614 | @item @samp{cmpmem@var{m}} | |
6615 | Block compare instruction, with five operands like the operands | |
6616 | of @samp{cmpstr@var{m}}. The two memory blocks specified are compared | |
6617 | byte by byte in lexicographic order starting at the beginning of each | |
6618 | block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch | |
9b0f6f5e NC |
6619 | any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}} |
6620 | the comparison will not stop if both bytes are zero. The effect of | |
6621 | the instruction is to store a value in operand 0 whose sign indicates | |
6622 | the result of the comparison. | |
358b8f01 | 6623 | |
03dda8e3 RK |
6624 | @cindex @code{strlen@var{m}} instruction pattern |
6625 | @item @samp{strlen@var{m}} | |
6626 | Compute the length of a string, with three operands. | |
6627 | Operand 0 is the result (of mode @var{m}), operand 1 is | |
6628 | a @code{mem} referring to the first character of the string, | |
6629 | operand 2 is the character to search for (normally zero), | |
6630 | and operand 3 is a constant describing the known alignment | |
6631 | of the beginning of the string. | |
6632 | ||
6f966f06 SSF |
6633 | @cindex @code{rawmemchr@var{m}} instruction pattern |
6634 | @item @samp{rawmemchr@var{m}} | |
6635 | Scan memory referred to by operand 1 for the first occurrence of operand 2. | |
6636 | Operand 1 is a @code{mem} and operand 2 a @code{const_int} of mode @var{m}. | |
6637 | Operand 0 is the result, i.e., a pointer to the first occurrence of operand 2 | |
6638 | in the memory block given by operand 1. | |
6639 | ||
e0d4c0b3 | 6640 | @cindex @code{float@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6641 | @item @samp{float@var{m}@var{n}2} |
6642 | Convert signed integer operand 1 (valid for fixed point mode @var{m}) to | |
6643 | floating point mode @var{n} and store in operand 0 (which has mode | |
6644 | @var{n}). | |
6645 | ||
e0d4c0b3 | 6646 | @cindex @code{floatuns@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6647 | @item @samp{floatuns@var{m}@var{n}2} |
6648 | Convert unsigned integer operand 1 (valid for fixed point mode @var{m}) | |
6649 | to floating point mode @var{n} and store in operand 0 (which has mode | |
6650 | @var{n}). | |
6651 | ||
e0d4c0b3 | 6652 | @cindex @code{fix@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6653 | @item @samp{fix@var{m}@var{n}2} |
6654 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6655 | point mode @var{n} as a signed number and store in operand 0 (which | |
6656 | has mode @var{n}). This instruction's result is defined only when | |
6657 | the value of operand 1 is an integer. | |
6658 | ||
0e1d7f32 AH |
6659 | If the machine description defines this pattern, it also needs to |
6660 | define the @code{ftrunc} pattern. | |
6661 | ||
e0d4c0b3 | 6662 | @cindex @code{fixuns@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6663 | @item @samp{fixuns@var{m}@var{n}2} |
6664 | Convert operand 1 (valid for floating point mode @var{m}) to fixed | |
6665 | point mode @var{n} as an unsigned number and store in operand 0 (which | |
6666 | has mode @var{n}). This instruction's result is defined only when the | |
6667 | value of operand 1 is an integer. | |
6668 | ||
6669 | @cindex @code{ftrunc@var{m}2} instruction pattern | |
6670 | @item @samp{ftrunc@var{m}2} | |
6671 | Convert operand 1 (valid for floating point mode @var{m}) to an | |
6672 | integer value, still represented in floating point mode @var{m}, and | |
6673 | store it in operand 0 (valid for floating point mode @var{m}). | |
6674 | ||
e0d4c0b3 | 6675 | @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6676 | @item @samp{fix_trunc@var{m}@var{n}2} |
6677 | Like @samp{fix@var{m}@var{n}2} but works for any floating point value | |
6678 | of mode @var{m} by converting the value to an integer. | |
6679 | ||
e0d4c0b3 | 6680 | @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6681 | @item @samp{fixuns_trunc@var{m}@var{n}2} |
6682 | Like @samp{fixuns@var{m}@var{n}2} but works for any floating point | |
6683 | value of mode @var{m} by converting the value to an integer. | |
6684 | ||
e0d4c0b3 | 6685 | @cindex @code{trunc@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6686 | @item @samp{trunc@var{m}@var{n}2} |
6687 | Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and | |
6688 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
6689 | point or both floating point. | |
6690 | ||
e0d4c0b3 | 6691 | @cindex @code{extend@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6692 | @item @samp{extend@var{m}@var{n}2} |
6693 | Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
6694 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
6695 | point or both floating point. | |
6696 | ||
e0d4c0b3 | 6697 | @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern |
03dda8e3 RK |
6698 | @item @samp{zero_extend@var{m}@var{n}2} |
6699 | Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and | |
6700 | store in operand 0 (which has mode @var{n}). Both modes must be fixed | |
6701 | point. | |
6702 | ||
e0d4c0b3 | 6703 | @cindex @code{fract@var{m}@var{n}2} instruction pattern |
0f996086 CF |
6704 | @item @samp{fract@var{m}@var{n}2} |
6705 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
6706 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
6707 | could be fixed-point to fixed-point, signed integer to fixed-point, | |
6708 | fixed-point to signed integer, floating-point to fixed-point, | |
6709 | or fixed-point to floating-point. | |
6710 | When overflows or underflows happen, the results are undefined. | |
6711 | ||
e0d4c0b3 | 6712 | @cindex @code{satfract@var{m}@var{n}2} instruction pattern |
0f996086 CF |
6713 | @item @samp{satfract@var{m}@var{n}2} |
6714 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
6715 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
6716 | could be fixed-point to fixed-point, signed integer to fixed-point, | |
6717 | or floating-point to fixed-point. | |
6718 | When overflows or underflows happen, the instruction saturates the | |
6719 | results to the maximum or the minimum. | |
6720 | ||
e0d4c0b3 | 6721 | @cindex @code{fractuns@var{m}@var{n}2} instruction pattern |
0f996086 CF |
6722 | @item @samp{fractuns@var{m}@var{n}2} |
6723 | Convert operand 1 of mode @var{m} to mode @var{n} and store in | |
6724 | operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n} | |
6725 | could be unsigned integer to fixed-point, or | |
6726 | fixed-point to unsigned integer. | |
6727 | When overflows or underflows happen, the results are undefined. | |
6728 | ||
e0d4c0b3 | 6729 | @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern |
0f996086 CF |
6730 | @item @samp{satfractuns@var{m}@var{n}2} |
6731 | Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode | |
6732 | @var{n} and store in operand 0 (which has mode @var{n}). | |
6733 | When overflows or underflows happen, the instruction saturates the | |
6734 | results to the maximum or the minimum. | |
6735 | ||
d2eeb2d1 RS |
6736 | @cindex @code{extv@var{m}} instruction pattern |
6737 | @item @samp{extv@var{m}} | |
6738 | Extract a bit-field from register operand 1, sign-extend it, and store | |
6739 | it in operand 0. Operand 2 specifies the width of the field in bits | |
6740 | and operand 3 the starting bit, which counts from the most significant | |
6741 | bit if @samp{BITS_BIG_ENDIAN} is true and from the least significant bit | |
6742 | otherwise. | |
6743 | ||
6744 | Operands 0 and 1 both have mode @var{m}. Operands 2 and 3 have a | |
6745 | target-specific mode. | |
6746 | ||
6747 | @cindex @code{extvmisalign@var{m}} instruction pattern | |
6748 | @item @samp{extvmisalign@var{m}} | |
6749 | Extract a bit-field from memory operand 1, sign extend it, and store | |
6750 | it in operand 0. Operand 2 specifies the width in bits and operand 3 | |
6751 | the starting bit. The starting bit is always somewhere in the first byte of | |
6752 | operand 1; it counts from the most significant bit if @samp{BITS_BIG_ENDIAN} | |
6753 | is true and from the least significant bit otherwise. | |
6754 | ||
6755 | Operand 0 has mode @var{m} while operand 1 has @code{BLK} mode. | |
6756 | Operands 2 and 3 have a target-specific mode. | |
6757 | ||
6758 | The instruction must not read beyond the last byte of the bit-field. | |
6759 | ||
6760 | @cindex @code{extzv@var{m}} instruction pattern | |
6761 | @item @samp{extzv@var{m}} | |
6762 | Like @samp{extv@var{m}} except that the bit-field value is zero-extended. | |
6763 | ||
6764 | @cindex @code{extzvmisalign@var{m}} instruction pattern | |
6765 | @item @samp{extzvmisalign@var{m}} | |
6766 | Like @samp{extvmisalign@var{m}} except that the bit-field value is | |
6767 | zero-extended. | |
6768 | ||
6769 | @cindex @code{insv@var{m}} instruction pattern | |
6770 | @item @samp{insv@var{m}} | |
6771 | Insert operand 3 into a bit-field of register operand 0. Operand 1 | |
6772 | specifies the width of the field in bits and operand 2 the starting bit, | |
6773 | which counts from the most significant bit if @samp{BITS_BIG_ENDIAN} | |
6774 | is true and from the least significant bit otherwise. | |
6775 | ||
6776 | Operands 0 and 3 both have mode @var{m}. Operands 1 and 2 have a | |
6777 | target-specific mode. | |
6778 | ||
6779 | @cindex @code{insvmisalign@var{m}} instruction pattern | |
6780 | @item @samp{insvmisalign@var{m}} | |
6781 | Insert operand 3 into a bit-field of memory operand 0. Operand 1 | |
6782 | specifies the width of the field in bits and operand 2 the starting bit. | |
6783 | The starting bit is always somewhere in the first byte of operand 0; | |
6784 | it counts from the most significant bit if @samp{BITS_BIG_ENDIAN} | |
6785 | is true and from the least significant bit otherwise. | |
6786 | ||
6787 | Operand 3 has mode @var{m} while operand 0 has @code{BLK} mode. | |
6788 | Operands 1 and 2 have a target-specific mode. | |
6789 | ||
6790 | The instruction must not read or write beyond the last byte of the bit-field. | |
6791 | ||
03dda8e3 RK |
6792 | @cindex @code{extv} instruction pattern |
6793 | @item @samp{extv} | |
c771326b | 6794 | Extract a bit-field from operand 1 (a register or memory operand), where |
03dda8e3 RK |
6795 | operand 2 specifies the width in bits and operand 3 the starting bit, |
6796 | and store it in operand 0. Operand 0 must have mode @code{word_mode}. | |
6797 | Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often | |
6798 | @code{word_mode} is allowed only for registers. Operands 2 and 3 must | |
6799 | be valid for @code{word_mode}. | |
6800 | ||
6801 | The RTL generation pass generates this instruction only with constants | |
3ab997e8 | 6802 | for operands 2 and 3 and the constant is never zero for operand 2. |
03dda8e3 RK |
6803 | |
6804 | The bit-field value is sign-extended to a full word integer | |
6805 | before it is stored in operand 0. | |
6806 | ||
d2eeb2d1 RS |
6807 | This pattern is deprecated; please use @samp{extv@var{m}} and |
6808 | @code{extvmisalign@var{m}} instead. | |
6809 | ||
03dda8e3 RK |
6810 | @cindex @code{extzv} instruction pattern |
6811 | @item @samp{extzv} | |
6812 | Like @samp{extv} except that the bit-field value is zero-extended. | |
6813 | ||
d2eeb2d1 RS |
6814 | This pattern is deprecated; please use @samp{extzv@var{m}} and |
6815 | @code{extzvmisalign@var{m}} instead. | |
6816 | ||
03dda8e3 RK |
6817 | @cindex @code{insv} instruction pattern |
6818 | @item @samp{insv} | |
c771326b JM |
6819 | Store operand 3 (which must be valid for @code{word_mode}) into a |
6820 | bit-field in operand 0, where operand 1 specifies the width in bits and | |
03dda8e3 RK |
6821 | operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or |
6822 | @code{word_mode}; often @code{word_mode} is allowed only for registers. | |
6823 | Operands 1 and 2 must be valid for @code{word_mode}. | |
6824 | ||
6825 | The RTL generation pass generates this instruction only with constants | |
3ab997e8 | 6826 | for operands 1 and 2 and the constant is never zero for operand 1. |
03dda8e3 | 6827 | |
d2eeb2d1 RS |
6828 | This pattern is deprecated; please use @samp{insv@var{m}} and |
6829 | @code{insvmisalign@var{m}} instead. | |
6830 | ||
03dda8e3 RK |
6831 | @cindex @code{mov@var{mode}cc} instruction pattern |
6832 | @item @samp{mov@var{mode}cc} | |
6833 | Conditionally move operand 2 or operand 3 into operand 0 according to the | |
6834 | comparison in operand 1. If the comparison is true, operand 2 is moved | |
6835 | into operand 0, otherwise operand 3 is moved. | |
6836 | ||
6837 | The mode of the operands being compared need not be the same as the operands | |
6838 | being moved. Some machines, sparc64 for example, have instructions that | |
6839 | conditionally move an integer value based on the floating point condition | |
6840 | codes and vice versa. | |
6841 | ||
6842 | If the machine does not have conditional move instructions, do not | |
6843 | define these patterns. | |
6844 | ||
068f5dea | 6845 | @cindex @code{add@var{mode}cc} instruction pattern |
4b5cc2b3 | 6846 | @item @samp{add@var{mode}cc} |
068f5dea JH |
6847 | Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally |
6848 | move operand 2 or (operands 2 + operand 3) into operand 0 according to the | |
5285c21c | 6849 | comparison in operand 1. If the comparison is false, operand 2 is moved into |
4b5cc2b3 | 6850 | operand 0, otherwise (operand 2 + operand 3) is moved. |
068f5dea | 6851 | |
0972596e RS |
6852 | @cindex @code{cond_add@var{mode}} instruction pattern |
6853 | @cindex @code{cond_sub@var{mode}} instruction pattern | |
6c4fd4a9 RS |
6854 | @cindex @code{cond_mul@var{mode}} instruction pattern |
6855 | @cindex @code{cond_div@var{mode}} instruction pattern | |
6856 | @cindex @code{cond_udiv@var{mode}} instruction pattern | |
6857 | @cindex @code{cond_mod@var{mode}} instruction pattern | |
6858 | @cindex @code{cond_umod@var{mode}} instruction pattern | |
0972596e RS |
6859 | @cindex @code{cond_and@var{mode}} instruction pattern |
6860 | @cindex @code{cond_ior@var{mode}} instruction pattern | |
6861 | @cindex @code{cond_xor@var{mode}} instruction pattern | |
6862 | @cindex @code{cond_smin@var{mode}} instruction pattern | |
6863 | @cindex @code{cond_smax@var{mode}} instruction pattern | |
6864 | @cindex @code{cond_umin@var{mode}} instruction pattern | |
6865 | @cindex @code{cond_umax@var{mode}} instruction pattern | |
70613000 RS |
6866 | @cindex @code{cond_fmin@var{mode}} instruction pattern |
6867 | @cindex @code{cond_fmax@var{mode}} instruction pattern | |
c04bb6d9 RS |
6868 | @cindex @code{cond_ashl@var{mode}} instruction pattern |
6869 | @cindex @code{cond_ashr@var{mode}} instruction pattern | |
6870 | @cindex @code{cond_lshr@var{mode}} instruction pattern | |
0972596e RS |
6871 | @item @samp{cond_add@var{mode}} |
6872 | @itemx @samp{cond_sub@var{mode}} | |
6c4fd4a9 RS |
6873 | @itemx @samp{cond_mul@var{mode}} |
6874 | @itemx @samp{cond_div@var{mode}} | |
6875 | @itemx @samp{cond_udiv@var{mode}} | |
6876 | @itemx @samp{cond_mod@var{mode}} | |
6877 | @itemx @samp{cond_umod@var{mode}} | |
0972596e RS |
6878 | @itemx @samp{cond_and@var{mode}} |
6879 | @itemx @samp{cond_ior@var{mode}} | |
6880 | @itemx @samp{cond_xor@var{mode}} | |
6881 | @itemx @samp{cond_smin@var{mode}} | |
6882 | @itemx @samp{cond_smax@var{mode}} | |
6883 | @itemx @samp{cond_umin@var{mode}} | |
6884 | @itemx @samp{cond_umax@var{mode}} | |
70613000 RS |
6885 | @itemx @samp{cond_fmin@var{mode}} |
6886 | @itemx @samp{cond_fmax@var{mode}} | |
c04bb6d9 RS |
6887 | @itemx @samp{cond_ashl@var{mode}} |
6888 | @itemx @samp{cond_ashr@var{mode}} | |
6889 | @itemx @samp{cond_lshr@var{mode}} | |
9d4ac06e RS |
6890 | When operand 1 is true, perform an operation on operands 2 and 3 and |
6891 | store the result in operand 0, otherwise store operand 4 in operand 0. | |
6892 | The operation works elementwise if the operands are vectors. | |
6893 | ||
6894 | The scalar case is equivalent to: | |
6895 | ||
6896 | @smallexample | |
6897 | op0 = op1 ? op2 @var{op} op3 : op4; | |
6898 | @end smallexample | |
6899 | ||
6900 | while the vector case is equivalent to: | |
0972596e RS |
6901 | |
6902 | @smallexample | |
9d4ac06e RS |
6903 | for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) |
6904 | op0[i] = op1[i] ? op2[i] @var{op} op3[i] : op4[i]; | |
0972596e RS |
6905 | @end smallexample |
6906 | ||
6907 | where, for example, @var{op} is @code{+} for @samp{cond_add@var{mode}}. | |
6908 | ||
6909 | When defined for floating-point modes, the contents of @samp{op3[i]} | |
06293766 | 6910 | are not interpreted if @samp{op1[i]} is false, just like they would not |
0972596e RS |
6911 | be in a normal C @samp{?:} condition. |
6912 | ||
9d4ac06e RS |
6913 | Operands 0, 2, 3 and 4 all have mode @var{m}. Operand 1 is a scalar |
6914 | integer if @var{m} is scalar, otherwise it has the mode returned by | |
6915 | @code{TARGET_VECTORIZE_GET_MASK_MODE}. | |
0972596e | 6916 | |
c04bb6d9 RS |
6917 | @samp{cond_@var{op}@var{mode}} generally corresponds to a conditional |
6918 | form of @samp{@var{op}@var{mode}3}. As an exception, the vector forms | |
6919 | of shifts correspond to patterns like @code{vashl@var{mode}3} rather | |
6920 | than patterns like @code{ashl@var{mode}3}. | |
6921 | ||
b41d1f6e RS |
6922 | @cindex @code{cond_fma@var{mode}} instruction pattern |
6923 | @cindex @code{cond_fms@var{mode}} instruction pattern | |
6924 | @cindex @code{cond_fnma@var{mode}} instruction pattern | |
6925 | @cindex @code{cond_fnms@var{mode}} instruction pattern | |
6926 | @item @samp{cond_fma@var{mode}} | |
6927 | @itemx @samp{cond_fms@var{mode}} | |
6928 | @itemx @samp{cond_fnma@var{mode}} | |
6929 | @itemx @samp{cond_fnms@var{mode}} | |
6930 | Like @samp{cond_add@var{m}}, except that the conditional operation | |
6931 | takes 3 operands rather than two. For example, the vector form of | |
6932 | @samp{cond_fma@var{mode}} is equivalent to: | |
6933 | ||
6934 | @smallexample | |
6935 | for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++) | |
6936 | op0[i] = op1[i] ? fma (op2[i], op3[i], op4[i]) : op5[i]; | |
6937 | @end smallexample | |
6938 | ||
ce68b5cf KT |
6939 | @cindex @code{neg@var{mode}cc} instruction pattern |
6940 | @item @samp{neg@var{mode}cc} | |
6941 | Similar to @samp{mov@var{mode}cc} but for conditional negation. Conditionally | |
6942 | move the negation of operand 2 or the unchanged operand 3 into operand 0 | |
6943 | according to the comparison in operand 1. If the comparison is true, the negation | |
6944 | of operand 2 is moved into operand 0, otherwise operand 3 is moved. | |
6945 | ||
6946 | @cindex @code{not@var{mode}cc} instruction pattern | |
6947 | @item @samp{not@var{mode}cc} | |
6948 | Similar to @samp{neg@var{mode}cc} but for conditional complement. | |
6949 | Conditionally move the bitwise complement of operand 2 or the unchanged | |
6950 | operand 3 into operand 0 according to the comparison in operand 1. | |
6951 | If the comparison is true, the complement of operand 2 is moved into | |
6952 | operand 0, otherwise operand 3 is moved. | |
6953 | ||
f90b7a5a PB |
6954 | @cindex @code{cstore@var{mode}4} instruction pattern |
6955 | @item @samp{cstore@var{mode}4} | |
6956 | Store zero or nonzero in operand 0 according to whether a comparison | |
6957 | is true. Operand 1 is a comparison operator. Operand 2 and operand 3 | |
6958 | are the first and second operand of the comparison, respectively. | |
6959 | You specify the mode that operand 0 must have when you write the | |
6960 | @code{match_operand} expression. The compiler automatically sees which | |
6961 | mode you have used and supplies an operand of that mode. | |
03dda8e3 RK |
6962 | |
6963 | The value stored for a true condition must have 1 as its low bit, or | |
6964 | else must be negative. Otherwise the instruction is not suitable and | |
6965 | you should omit it from the machine description. You describe to the | |
6966 | compiler exactly which value is stored by defining the macro | |
6967 | @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be | |
ac5eda13 PB |
6968 | found that can be used for all the possible comparison operators, you |
6969 | should pick one and use a @code{define_expand} to map all results | |
6970 | onto the one you chose. | |
6971 | ||
6972 | These operations may @code{FAIL}, but should do so only in relatively | |
6973 | uncommon cases; if they would @code{FAIL} for common cases involving | |
6974 | integer comparisons, it is best to restrict the predicates to not | |
6975 | allow these operands. Likewise if a given comparison operator will | |
6976 | always fail, independent of the operands (for floating-point modes, the | |
6977 | @code{ordered_comparison_operator} predicate is often useful in this case). | |
6978 | ||
6979 | If this pattern is omitted, the compiler will generate a conditional | |
6980 | branch---for example, it may copy a constant one to the target and branching | |
6981 | around an assignment of zero to the target---or a libcall. If the predicate | |
6982 | for operand 1 only rejects some operators, it will also try reordering the | |
6983 | operands and/or inverting the result value (e.g.@: by an exclusive OR). | |
6984 | These possibilities could be cheaper or equivalent to the instructions | |
6985 | used for the @samp{cstore@var{mode}4} pattern followed by those required | |
6986 | to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this | |
6987 | case, you can and should make operand 1's predicate reject some operators | |
6988 | in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether | |
6989 | from the machine description. | |
03dda8e3 | 6990 | |
66c87bae KH |
6991 | @cindex @code{cbranch@var{mode}4} instruction pattern |
6992 | @item @samp{cbranch@var{mode}4} | |
6993 | Conditional branch instruction combined with a compare instruction. | |
6994 | Operand 0 is a comparison operator. Operand 1 and operand 2 are the | |
6995 | first and second operands of the comparison, respectively. Operand 3 | |
481efdd9 | 6996 | is the @code{code_label} to jump to. |
66c87bae | 6997 | |
d26eedb6 HPN |
6998 | @cindex @code{jump} instruction pattern |
6999 | @item @samp{jump} | |
7000 | A jump inside a function; an unconditional branch. Operand 0 is the | |
481efdd9 EB |
7001 | @code{code_label} to jump to. This pattern name is mandatory on all |
7002 | machines. | |
d26eedb6 | 7003 | |
03dda8e3 RK |
7004 | @cindex @code{call} instruction pattern |
7005 | @item @samp{call} | |
7006 | Subroutine call instruction returning no value. Operand 0 is the | |
7007 | function to call; operand 1 is the number of bytes of arguments pushed | |
ee189a73 HPN |
7008 | as a @code{const_int}. Operand 2 is the result of calling the target |
7009 | hook @code{TARGET_FUNCTION_ARG} with the second argument @code{arg} | |
7010 | yielding true for @code{arg.end_marker_p ()}, in a call after all | |
7011 | parameters have been passed to that hook. By default this is the first | |
7012 | register beyond those used for arguments in the call, or @code{NULL} if | |
7013 | all the argument-registers are used in the call. | |
03dda8e3 RK |
7014 | |
7015 | On most machines, operand 2 is not actually stored into the RTL | |
7016 | pattern. It is supplied for the sake of some RISC machines which need | |
7017 | to put this information into the assembler code; they can put it in | |
7018 | the RTL instead of operand 1. | |
7019 | ||
7020 | Operand 0 should be a @code{mem} RTX whose address is the address of the | |
7021 | function. Note, however, that this address can be a @code{symbol_ref} | |
7022 | expression even if it would not be a legitimate memory address on the | |
7023 | target machine. If it is also not a valid argument for a call | |
7024 | instruction, the pattern for this operation should be a | |
7025 | @code{define_expand} (@pxref{Expander Definitions}) that places the | |
7026 | address into a register and uses that register in the call instruction. | |
7027 | ||
7028 | @cindex @code{call_value} instruction pattern | |
7029 | @item @samp{call_value} | |
7030 | Subroutine call instruction returning a value. Operand 0 is the hard | |
7031 | register in which the value is returned. There are three more | |
7032 | operands, the same as the three operands of the @samp{call} | |
7033 | instruction (but with numbers increased by one). | |
7034 | ||
7035 | Subroutines that return @code{BLKmode} objects use the @samp{call} | |
7036 | insn. | |
7037 | ||
7038 | @cindex @code{call_pop} instruction pattern | |
7039 | @cindex @code{call_value_pop} instruction pattern | |
7040 | @item @samp{call_pop}, @samp{call_value_pop} | |
7041 | Similar to @samp{call} and @samp{call_value}, except used if defined and | |
df2a54e9 | 7042 | if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel} |
03dda8e3 RK |
7043 | that contains both the function call and a @code{set} to indicate the |
7044 | adjustment made to the frame pointer. | |
7045 | ||
df2a54e9 | 7046 | For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these |
03dda8e3 RK |
7047 | patterns increases the number of functions for which the frame pointer |
7048 | can be eliminated, if desired. | |
7049 | ||
7050 | @cindex @code{untyped_call} instruction pattern | |
7051 | @item @samp{untyped_call} | |
7052 | Subroutine call instruction returning a value of any type. Operand 0 is | |
7053 | the function to call; operand 1 is a memory location where the result of | |
7054 | calling the function is to be stored; operand 2 is a @code{parallel} | |
7055 | expression where each element is a @code{set} expression that indicates | |
7056 | the saving of a function return value into the result block. | |
7057 | ||
7058 | This instruction pattern should be defined to support | |
7059 | @code{__builtin_apply} on machines where special instructions are needed | |
7060 | to call a subroutine with arbitrary arguments or to save the value | |
7061 | returned. This instruction pattern is required on machines that have | |
e979f9e8 JM |
7062 | multiple registers that can hold a return value |
7063 | (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register). | |
03dda8e3 RK |
7064 | |
7065 | @cindex @code{return} instruction pattern | |
7066 | @item @samp{return} | |
7067 | Subroutine return instruction. This instruction pattern name should be | |
7068 | defined only if a single instruction can do all the work of returning | |
7069 | from a function. | |
7070 | ||
7071 | Like the @samp{mov@var{m}} patterns, this pattern is also used after the | |
7072 | RTL generation phase. In this case it is to support machines where | |
7073 | multiple instructions are usually needed to return from a function, but | |
7074 | some class of functions only requires one instruction to implement a | |
7075 | return. Normally, the applicable functions are those which do not need | |
7076 | to save any registers or allocate stack space. | |
7077 | ||
26898771 BS |
7078 | It is valid for this pattern to expand to an instruction using |
7079 | @code{simple_return} if no epilogue is required. | |
7080 | ||
7081 | @cindex @code{simple_return} instruction pattern | |
7082 | @item @samp{simple_return} | |
7083 | Subroutine return instruction. This instruction pattern name should be | |
7084 | defined only if a single instruction can do all the work of returning | |
7085 | from a function on a path where no epilogue is required. This pattern | |
7086 | is very similar to the @code{return} instruction pattern, but it is emitted | |
7087 | only by the shrink-wrapping optimization on paths where the function | |
7088 | prologue has not been executed, and a function return should occur without | |
7089 | any of the effects of the epilogue. Additional uses may be introduced on | |
7090 | paths where both the prologue and the epilogue have executed. | |
7091 | ||
03dda8e3 RK |
7092 | @findex reload_completed |
7093 | @findex leaf_function_p | |
7094 | For such machines, the condition specified in this pattern should only | |
df2a54e9 | 7095 | be true when @code{reload_completed} is nonzero and the function's |
03dda8e3 RK |
7096 | epilogue would only be a single instruction. For machines with register |
7097 | windows, the routine @code{leaf_function_p} may be used to determine if | |
7098 | a register window push is required. | |
7099 | ||
7100 | Machines that have conditional return instructions should define patterns | |
7101 | such as | |
7102 | ||
7103 | @smallexample | |
7104 | (define_insn "" | |
7105 | [(set (pc) | |
7106 | (if_then_else (match_operator | |
7107 | 0 "comparison_operator" | |
bd1cd0d0 | 7108 | [(reg:CC CC_REG) (const_int 0)]) |
03dda8e3 RK |
7109 | (return) |
7110 | (pc)))] | |
7111 | "@var{condition}" | |
7112 | "@dots{}") | |
7113 | @end smallexample | |
7114 | ||
7115 | where @var{condition} would normally be the same condition specified on the | |
7116 | named @samp{return} pattern. | |
7117 | ||
7118 | @cindex @code{untyped_return} instruction pattern | |
7119 | @item @samp{untyped_return} | |
7120 | Untyped subroutine return instruction. This instruction pattern should | |
7121 | be defined to support @code{__builtin_return} on machines where special | |
7122 | instructions are needed to return a value of any type. | |
7123 | ||
7124 | Operand 0 is a memory location where the result of calling a function | |
7125 | with @code{__builtin_apply} is stored; operand 1 is a @code{parallel} | |
7126 | expression where each element is a @code{set} expression that indicates | |
7127 | the restoring of a function return value from the result block. | |
7128 | ||
7129 | @cindex @code{nop} instruction pattern | |
7130 | @item @samp{nop} | |
7131 | No-op instruction. This instruction pattern name should always be defined | |
7132 | to output a no-op in assembler code. @code{(const_int 0)} will do as an | |
7133 | RTL pattern. | |
7134 | ||
7135 | @cindex @code{indirect_jump} instruction pattern | |
7136 | @item @samp{indirect_jump} | |
7137 | An instruction to jump to an address which is operand zero. | |
7138 | This pattern name is mandatory on all machines. | |
7139 | ||
7140 | @cindex @code{casesi} instruction pattern | |
7141 | @item @samp{casesi} | |
7142 | Instruction to jump through a dispatch table, including bounds checking. | |
7143 | This instruction takes five operands: | |
7144 | ||
7145 | @enumerate | |
7146 | @item | |
7147 | The index to dispatch on, which has mode @code{SImode}. | |
7148 | ||
7149 | @item | |
7150 | The lower bound for indices in the table, an integer constant. | |
7151 | ||
7152 | @item | |
7153 | The total range of indices in the table---the largest index | |
7154 | minus the smallest one (both inclusive). | |
7155 | ||
7156 | @item | |
7157 | A label that precedes the table itself. | |
7158 | ||
7159 | @item | |
7160 | A label to jump to if the index has a value outside the bounds. | |
03dda8e3 RK |
7161 | @end enumerate |
7162 | ||
e4ae5e77 | 7163 | The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a |
da5c6bde | 7164 | @code{jump_table_data}. The number of elements in the table is one plus the |
03dda8e3 RK |
7165 | difference between the upper bound and the lower bound. |
7166 | ||
7167 | @cindex @code{tablejump} instruction pattern | |
7168 | @item @samp{tablejump} | |
7169 | Instruction to jump to a variable address. This is a low-level | |
7170 | capability which can be used to implement a dispatch table when there | |
7171 | is no @samp{casesi} pattern. | |
7172 | ||
7173 | This pattern requires two operands: the address or offset, and a label | |
7174 | which should immediately precede the jump table. If the macro | |
f1f5f142 JL |
7175 | @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first |
7176 | operand is an offset which counts from the address of the table; otherwise, | |
7177 | it is an absolute address to jump to. In either case, the first operand has | |
03dda8e3 RK |
7178 | mode @code{Pmode}. |
7179 | ||
7180 | The @samp{tablejump} insn is always the last insn before the jump | |
7181 | table it uses. Its assembler code normally has no need to use the | |
7182 | second operand, but you should incorporate it in the RTL pattern so | |
7183 | that the jump optimizer will not delete the table as unreachable code. | |
7184 | ||
6e4fcc95 | 7185 | |
6e4fcc95 MH |
7186 | @cindex @code{doloop_end} instruction pattern |
7187 | @item @samp{doloop_end} | |
1d0216c8 RS |
7188 | Conditional branch instruction that decrements a register and |
7189 | jumps if the register is nonzero. Operand 0 is the register to | |
7190 | decrement and test; operand 1 is the label to jump to if the | |
7191 | register is nonzero. | |
5c25e11d | 7192 | @xref{Looping Patterns}. |
6e4fcc95 MH |
7193 | |
7194 | This optional instruction pattern should be defined for machines with | |
7195 | low-overhead looping instructions as the loop optimizer will try to | |
1d0216c8 RS |
7196 | modify suitable loops to utilize it. The target hook |
7197 | @code{TARGET_CAN_USE_DOLOOP_P} controls the conditions under which | |
7198 | low-overhead loops can be used. | |
6e4fcc95 MH |
7199 | |
7200 | @cindex @code{doloop_begin} instruction pattern | |
7201 | @item @samp{doloop_begin} | |
7202 | Companion instruction to @code{doloop_end} required for machines that | |
1d0216c8 RS |
7203 | need to perform some initialization, such as loading a special counter |
7204 | register. Operand 1 is the associated @code{doloop_end} pattern and | |
7205 | operand 0 is the register that it decrements. | |
6e4fcc95 | 7206 | |
1d0216c8 RS |
7207 | If initialization insns do not always need to be emitted, use a |
7208 | @code{define_expand} (@pxref{Expander Definitions}) and make it fail. | |
6e4fcc95 | 7209 | |
03dda8e3 RK |
7210 | @cindex @code{canonicalize_funcptr_for_compare} instruction pattern |
7211 | @item @samp{canonicalize_funcptr_for_compare} | |
7212 | Canonicalize the function pointer in operand 1 and store the result | |
7213 | into operand 0. | |
7214 | ||
7215 | Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1 | |
7216 | may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc | |
7217 | and also has mode @code{Pmode}. | |
7218 | ||
7219 | Canonicalization of a function pointer usually involves computing | |
7220 | the address of the function which would be called if the function | |
7221 | pointer were used in an indirect call. | |
7222 | ||
7223 | Only define this pattern if function pointers on the target machine | |
7224 | can have different values but still call the same function when | |
7225 | used in an indirect call. | |
7226 | ||
7227 | @cindex @code{save_stack_block} instruction pattern | |
7228 | @cindex @code{save_stack_function} instruction pattern | |
7229 | @cindex @code{save_stack_nonlocal} instruction pattern | |
7230 | @cindex @code{restore_stack_block} instruction pattern | |
7231 | @cindex @code{restore_stack_function} instruction pattern | |
7232 | @cindex @code{restore_stack_nonlocal} instruction pattern | |
7233 | @item @samp{save_stack_block} | |
7234 | @itemx @samp{save_stack_function} | |
7235 | @itemx @samp{save_stack_nonlocal} | |
7236 | @itemx @samp{restore_stack_block} | |
7237 | @itemx @samp{restore_stack_function} | |
7238 | @itemx @samp{restore_stack_nonlocal} | |
7239 | Most machines save and restore the stack pointer by copying it to or | |
7240 | from an object of mode @code{Pmode}. Do not define these patterns on | |
7241 | such machines. | |
7242 | ||
7243 | Some machines require special handling for stack pointer saves and | |
7244 | restores. On those machines, define the patterns corresponding to the | |
7245 | non-standard cases by using a @code{define_expand} (@pxref{Expander | |
7246 | Definitions}) that produces the required insns. The three types of | |
7247 | saves and restores are: | |
7248 | ||
7249 | @enumerate | |
7250 | @item | |
7251 | @samp{save_stack_block} saves the stack pointer at the start of a block | |
7252 | that allocates a variable-sized object, and @samp{restore_stack_block} | |
7253 | restores the stack pointer when the block is exited. | |
7254 | ||
7255 | @item | |
7256 | @samp{save_stack_function} and @samp{restore_stack_function} do a | |
7257 | similar job for the outermost block of a function and are used when the | |
7258 | function allocates variable-sized objects or calls @code{alloca}. Only | |
7259 | the epilogue uses the restored stack pointer, allowing a simpler save or | |
7260 | restore sequence on some machines. | |
7261 | ||
7262 | @item | |
7263 | @samp{save_stack_nonlocal} is used in functions that contain labels | |
7264 | branched to by nested functions. It saves the stack pointer in such a | |
7265 | way that the inner function can use @samp{restore_stack_nonlocal} to | |
7266 | restore the stack pointer. The compiler generates code to restore the | |
7267 | frame and argument pointer registers, but some machines require saving | |
7268 | and restoring additional data such as register window information or | |
7269 | stack backchains. Place insns in these patterns to save and restore any | |
7270 | such required data. | |
7271 | @end enumerate | |
7272 | ||
7273 | When saving the stack pointer, operand 0 is the save area and operand 1 | |
73c8090f DE |
7274 | is the stack pointer. The mode used to allocate the save area defaults |
7275 | to @code{Pmode} but you can override that choice by defining the | |
7e390c9d | 7276 | @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must |
73c8090f DE |
7277 | specify an integral mode, or @code{VOIDmode} if no save area is needed |
7278 | for a particular type of save (either because no save is needed or | |
7279 | because a machine-specific save area can be used). Operand 0 is the | |
7280 | stack pointer and operand 1 is the save area for restore operations. If | |
7281 | @samp{save_stack_block} is defined, operand 0 must not be | |
7282 | @code{VOIDmode} since these saves can be arbitrarily nested. | |
03dda8e3 RK |
7283 | |
7284 | A save area is a @code{mem} that is at a constant offset from | |
7285 | @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by | |
7286 | nonlocal gotos and a @code{reg} in the other two cases. | |
7287 | ||
7288 | @cindex @code{allocate_stack} instruction pattern | |
7289 | @item @samp{allocate_stack} | |
72938a4c | 7290 | Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from |
03dda8e3 RK |
7291 | the stack pointer to create space for dynamically allocated data. |
7292 | ||
72938a4c MM |
7293 | Store the resultant pointer to this space into operand 0. If you |
7294 | are allocating space from the main stack, do this by emitting a | |
7295 | move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0. | |
7296 | If you are allocating the space elsewhere, generate code to copy the | |
7297 | location of the space to operand 0. In the latter case, you must | |
956d6950 | 7298 | ensure this space gets freed when the corresponding space on the main |
72938a4c MM |
7299 | stack is free. |
7300 | ||
03dda8e3 RK |
7301 | Do not define this pattern if all that must be done is the subtraction. |
7302 | Some machines require other operations such as stack probes or | |
7303 | maintaining the back chain. Define this pattern to emit those | |
7304 | operations in addition to updating the stack pointer. | |
7305 | ||
861bb6c1 JL |
7306 | @cindex @code{check_stack} instruction pattern |
7307 | @item @samp{check_stack} | |
507d0069 EB |
7308 | If stack checking (@pxref{Stack Checking}) cannot be done on your system by |
7309 | probing the stack, define this pattern to perform the needed check and signal | |
7310 | an error if the stack has overflowed. The single operand is the address in | |
7311 | the stack farthest from the current stack pointer that you need to validate. | |
7312 | Normally, on platforms where this pattern is needed, you would obtain the | |
7313 | stack limit from a global or thread-specific variable or register. | |
d809253a | 7314 | |
7b84aac0 EB |
7315 | @cindex @code{probe_stack_address} instruction pattern |
7316 | @item @samp{probe_stack_address} | |
7317 | If stack checking (@pxref{Stack Checking}) can be done on your system by | |
7318 | probing the stack but without the need to actually access it, define this | |
7319 | pattern and signal an error if the stack has overflowed. The single operand | |
7320 | is the memory address in the stack that needs to be probed. | |
7321 | ||
d809253a EB |
7322 | @cindex @code{probe_stack} instruction pattern |
7323 | @item @samp{probe_stack} | |
507d0069 EB |
7324 | If stack checking (@pxref{Stack Checking}) can be done on your system by |
7325 | probing the stack but doing it with a ``store zero'' instruction is not valid | |
7326 | or optimal, define this pattern to do the probing differently and signal an | |
7327 | error if the stack has overflowed. The single operand is the memory reference | |
7328 | in the stack that needs to be probed. | |
861bb6c1 | 7329 | |
03dda8e3 RK |
7330 | @cindex @code{nonlocal_goto} instruction pattern |
7331 | @item @samp{nonlocal_goto} | |
7332 | Emit code to generate a non-local goto, e.g., a jump from one function | |
7333 | to a label in an outer function. This pattern has four arguments, | |
7334 | each representing a value to be used in the jump. The first | |
45bb86fd | 7335 | argument is to be loaded into the frame pointer, the second is |
03dda8e3 RK |
7336 | the address to branch to (code to dispatch to the actual label), |
7337 | the third is the address of a location where the stack is saved, | |
7338 | and the last is the address of the label, to be placed in the | |
7339 | location for the incoming static chain. | |
7340 | ||
f0523f02 | 7341 | On most machines you need not define this pattern, since GCC will |
03dda8e3 RK |
7342 | already generate the correct code, which is to load the frame pointer |
7343 | and static chain, restore the stack (using the | |
7344 | @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly | |
7345 | to the dispatcher. You need only define this pattern if this code will | |
7346 | not work on your machine. | |
7347 | ||
7348 | @cindex @code{nonlocal_goto_receiver} instruction pattern | |
7349 | @item @samp{nonlocal_goto_receiver} | |
7350 | This pattern, if defined, contains code needed at the target of a | |
161d7b59 | 7351 | nonlocal goto after the code already generated by GCC@. You will not |
03dda8e3 RK |
7352 | normally need to define this pattern. A typical reason why you might |
7353 | need this pattern is if some value, such as a pointer to a global table, | |
c30ddbc9 | 7354 | must be restored when the frame pointer is restored. Note that a nonlocal |
89bcce1b | 7355 | goto only occurs within a unit-of-translation, so a global table pointer |
c30ddbc9 RH |
7356 | that is shared by all functions of a given module need not be restored. |
7357 | There are no arguments. | |
861bb6c1 JL |
7358 | |
7359 | @cindex @code{exception_receiver} instruction pattern | |
7360 | @item @samp{exception_receiver} | |
7361 | This pattern, if defined, contains code needed at the site of an | |
7362 | exception handler that isn't needed at the site of a nonlocal goto. You | |
7363 | will not normally need to define this pattern. A typical reason why you | |
7364 | might need this pattern is if some value, such as a pointer to a global | |
7365 | table, must be restored after control flow is branched to the handler of | |
7366 | an exception. There are no arguments. | |
c85f7c16 | 7367 | |
c30ddbc9 RH |
7368 | @cindex @code{builtin_setjmp_setup} instruction pattern |
7369 | @item @samp{builtin_setjmp_setup} | |
7370 | This pattern, if defined, contains additional code needed to initialize | |
7371 | the @code{jmp_buf}. You will not normally need to define this pattern. | |
7372 | A typical reason why you might need this pattern is if some value, such | |
7373 | as a pointer to a global table, must be restored. Though it is | |
7374 | preferred that the pointer value be recalculated if possible (given the | |
7375 | address of a label for instance). The single argument is a pointer to | |
7376 | the @code{jmp_buf}. Note that the buffer is five words long and that | |
7377 | the first three are normally used by the generic mechanism. | |
7378 | ||
c85f7c16 JL |
7379 | @cindex @code{builtin_setjmp_receiver} instruction pattern |
7380 | @item @samp{builtin_setjmp_receiver} | |
e4ae5e77 | 7381 | This pattern, if defined, contains code needed at the site of a |
c771326b | 7382 | built-in setjmp that isn't needed at the site of a nonlocal goto. You |
c85f7c16 JL |
7383 | will not normally need to define this pattern. A typical reason why you |
7384 | might need this pattern is if some value, such as a pointer to a global | |
c30ddbc9 | 7385 | table, must be restored. It takes one argument, which is the label |
073a8998 | 7386 | to which builtin_longjmp transferred control; this pattern may be emitted |
c30ddbc9 RH |
7387 | at a small offset from that label. |
7388 | ||
7389 | @cindex @code{builtin_longjmp} instruction pattern | |
7390 | @item @samp{builtin_longjmp} | |
7391 | This pattern, if defined, performs the entire action of the longjmp. | |
7392 | You will not normally need to define this pattern unless you also define | |
7393 | @code{builtin_setjmp_setup}. The single argument is a pointer to the | |
7394 | @code{jmp_buf}. | |
f69864aa | 7395 | |
52a11cbf RH |
7396 | @cindex @code{eh_return} instruction pattern |
7397 | @item @samp{eh_return} | |
f69864aa | 7398 | This pattern, if defined, affects the way @code{__builtin_eh_return}, |
52a11cbf RH |
7399 | and thence the call frame exception handling library routines, are |
7400 | built. It is intended to handle non-trivial actions needed along | |
7401 | the abnormal return path. | |
7402 | ||
34dc173c | 7403 | The address of the exception handler to which the function should return |
daf2f129 | 7404 | is passed as operand to this pattern. It will normally need to copied by |
34dc173c UW |
7405 | the pattern to some special register or memory location. |
7406 | If the pattern needs to determine the location of the target call | |
7407 | frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX}, | |
7408 | if defined; it will have already been assigned. | |
7409 | ||
7410 | If this pattern is not defined, the default action will be to simply | |
7411 | copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either | |
7412 | that macro or this pattern needs to be defined if call frame exception | |
7413 | handling is to be used. | |
0b433de6 JL |
7414 | |
7415 | @cindex @code{prologue} instruction pattern | |
17b53c33 | 7416 | @anchor{prologue instruction pattern} |
0b433de6 JL |
7417 | @item @samp{prologue} |
7418 | This pattern, if defined, emits RTL for entry to a function. The function | |
b192711e | 7419 | entry is responsible for setting up the stack frame, initializing the frame |
0b433de6 JL |
7420 | pointer register, saving callee saved registers, etc. |
7421 | ||
7422 | Using a prologue pattern is generally preferred over defining | |
17b53c33 | 7423 | @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue. |
0b433de6 JL |
7424 | |
7425 | The @code{prologue} pattern is particularly useful for targets which perform | |
7426 | instruction scheduling. | |
7427 | ||
12c5ffe5 EB |
7428 | @cindex @code{window_save} instruction pattern |
7429 | @anchor{window_save instruction pattern} | |
7430 | @item @samp{window_save} | |
7431 | This pattern, if defined, emits RTL for a register window save. It should | |
7432 | be defined if the target machine has register windows but the window events | |
7433 | are decoupled from calls to subroutines. The canonical example is the SPARC | |
7434 | architecture. | |
7435 | ||
0b433de6 | 7436 | @cindex @code{epilogue} instruction pattern |
17b53c33 | 7437 | @anchor{epilogue instruction pattern} |
0b433de6 | 7438 | @item @samp{epilogue} |
396ad517 | 7439 | This pattern emits RTL for exit from a function. The function |
b192711e | 7440 | exit is responsible for deallocating the stack frame, restoring callee saved |
0b433de6 JL |
7441 | registers and emitting the return instruction. |
7442 | ||
7443 | Using an epilogue pattern is generally preferred over defining | |
17b53c33 | 7444 | @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue. |
0b433de6 JL |
7445 | |
7446 | The @code{epilogue} pattern is particularly useful for targets which perform | |
7447 | instruction scheduling or which have delay slots for their return instruction. | |
7448 | ||
7449 | @cindex @code{sibcall_epilogue} instruction pattern | |
7450 | @item @samp{sibcall_epilogue} | |
7451 | This pattern, if defined, emits RTL for exit from a function without the final | |
7452 | branch back to the calling function. This pattern will be emitted before any | |
7453 | sibling call (aka tail call) sites. | |
7454 | ||
7455 | The @code{sibcall_epilogue} pattern must not clobber any arguments used for | |
7456 | parameter passing or any stack slots for arguments passed to the current | |
ebb48a4d | 7457 | function. |
a157febd GK |
7458 | |
7459 | @cindex @code{trap} instruction pattern | |
7460 | @item @samp{trap} | |
7461 | This pattern, if defined, signals an error, typically by causing some | |
4b1ea1f3 | 7462 | kind of signal to be raised. |
a157febd | 7463 | |
f90b7a5a PB |
7464 | @cindex @code{ctrap@var{MM}4} instruction pattern |
7465 | @item @samp{ctrap@var{MM}4} | |
a157febd | 7466 | Conditional trap instruction. Operand 0 is a piece of RTL which |
f90b7a5a PB |
7467 | performs a comparison, and operands 1 and 2 are the arms of the |
7468 | comparison. Operand 3 is the trap code, an integer. | |
a157febd | 7469 | |
f90b7a5a | 7470 | A typical @code{ctrap} pattern looks like |
a157febd GK |
7471 | |
7472 | @smallexample | |
f90b7a5a | 7473 | (define_insn "ctrapsi4" |
ebb48a4d | 7474 | [(trap_if (match_operator 0 "trap_operator" |
f90b7a5a | 7475 | [(match_operand 1 "register_operand") |
73b8bfe1 | 7476 | (match_operand 2 "immediate_operand")]) |
f90b7a5a | 7477 | (match_operand 3 "const_int_operand" "i"))] |
a157febd GK |
7478 | "" |
7479 | "@dots{}") | |
7480 | @end smallexample | |
7481 | ||
e83d297b JJ |
7482 | @cindex @code{prefetch} instruction pattern |
7483 | @item @samp{prefetch} | |
e83d297b JJ |
7484 | This pattern, if defined, emits code for a non-faulting data prefetch |
7485 | instruction. Operand 0 is the address of the memory to prefetch. Operand 1 | |
7486 | is a constant 1 if the prefetch is preparing for a write to the memory | |
7487 | address, or a constant 0 otherwise. Operand 2 is the expected degree of | |
7488 | temporal locality of the data and is a value between 0 and 3, inclusive; 0 | |
7489 | means that the data has no temporal locality, so it need not be left in the | |
7490 | cache after the access; 3 means that the data has a high degree of temporal | |
7491 | locality and should be left in all levels of cache possible; 1 and 2 mean, | |
7492 | respectively, a low or moderate degree of temporal locality. | |
7493 | ||
7494 | Targets that do not support write prefetches or locality hints can ignore | |
7495 | the values of operands 1 and 2. | |
7496 | ||
b6bd3371 DE |
7497 | @cindex @code{blockage} instruction pattern |
7498 | @item @samp{blockage} | |
b6bd3371 | 7499 | This pattern defines a pseudo insn that prevents the instruction |
adddc347 HPN |
7500 | scheduler and other passes from moving instructions and using register |
7501 | equivalences across the boundary defined by the blockage insn. | |
7502 | This needs to be an UNSPEC_VOLATILE pattern or a volatile ASM. | |
b6bd3371 | 7503 | |
51ced7e4 UB |
7504 | @cindex @code{memory_blockage} instruction pattern |
7505 | @item @samp{memory_blockage} | |
7506 | This pattern, if defined, represents a compiler memory barrier, and will be | |
7507 | placed at points across which RTL passes may not propagate memory accesses. | |
7508 | This instruction needs to read and write volatile BLKmode memory. It does | |
7509 | not need to generate any machine instruction. If this pattern is not defined, | |
7510 | the compiler falls back to emitting an instruction corresponding | |
7511 | to @code{asm volatile ("" ::: "memory")}. | |
7512 | ||
48ae6c13 RH |
7513 | @cindex @code{memory_barrier} instruction pattern |
7514 | @item @samp{memory_barrier} | |
48ae6c13 RH |
7515 | If the target memory model is not fully synchronous, then this pattern |
7516 | should be defined to an instruction that orders both loads and stores | |
7517 | before the instruction with respect to loads and stores after the instruction. | |
7518 | This pattern has no operands. | |
7519 | ||
425fc685 RE |
7520 | @cindex @code{speculation_barrier} instruction pattern |
7521 | @item @samp{speculation_barrier} | |
7522 | If the target can support speculative execution, then this pattern should | |
7523 | be defined to an instruction that will block subsequent execution until | |
7524 | any prior speculation conditions has been resolved. The pattern must also | |
7525 | ensure that the compiler cannot move memory operations past the barrier, | |
7526 | so it needs to be an UNSPEC_VOLATILE pattern. The pattern has no | |
7527 | operands. | |
7528 | ||
7529 | If this pattern is not defined then the default expansion of | |
7530 | @code{__builtin_speculation_safe_value} will emit a warning. You can | |
7531 | suppress this warning by defining this pattern with a final condition | |
7532 | of @code{0} (zero), which tells the compiler that a speculation | |
7533 | barrier is not needed for this target. | |
7534 | ||
48ae6c13 RH |
7535 | @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern |
7536 | @item @samp{sync_compare_and_swap@var{mode}} | |
48ae6c13 RH |
7537 | This pattern, if defined, emits code for an atomic compare-and-swap |
7538 | operation. Operand 1 is the memory on which the atomic operation is | |
7539 | performed. Operand 2 is the ``old'' value to be compared against the | |
7540 | current contents of the memory location. Operand 3 is the ``new'' value | |
7541 | to store in the memory if the compare succeeds. Operand 0 is the result | |
915167f5 GK |
7542 | of the operation; it should contain the contents of the memory |
7543 | before the operation. If the compare succeeds, this should obviously be | |
7544 | a copy of operand 2. | |
48ae6c13 RH |
7545 | |
7546 | This pattern must show that both operand 0 and operand 1 are modified. | |
7547 | ||
915167f5 GK |
7548 | This pattern must issue any memory barrier instructions such that all |
7549 | memory operations before the atomic operation occur before the atomic | |
7550 | operation and all memory operations after the atomic operation occur | |
7551 | after the atomic operation. | |
48ae6c13 | 7552 | |
4a77c72b | 7553 | For targets where the success or failure of the compare-and-swap |
f90b7a5a PB |
7554 | operation is available via the status flags, it is possible to |
7555 | avoid a separate compare operation and issue the subsequent | |
7556 | branch or store-flag operation immediately after the compare-and-swap. | |
7557 | To this end, GCC will look for a @code{MODE_CC} set in the | |
7558 | output of @code{sync_compare_and_swap@var{mode}}; if the machine | |
7559 | description includes such a set, the target should also define special | |
7560 | @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then | |
7561 | be able to take the destination of the @code{MODE_CC} set and pass it | |
7562 | to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first | |
7563 | operand of the comparison (the second will be @code{(const_int 0)}). | |
48ae6c13 | 7564 | |
cedb4a1a RH |
7565 | For targets where the operating system may provide support for this |
7566 | operation via library calls, the @code{sync_compare_and_swap_optab} | |
7567 | may be initialized to a function with the same interface as the | |
7568 | @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire | |
7569 | set of @var{__sync} builtins are supported via library calls, the | |
7570 | target can initialize all of the optabs at once with | |
7571 | @code{init_sync_libfuncs}. | |
7572 | For the purposes of C++11 @code{std::atomic::is_lock_free}, it is | |
7573 | assumed that these library calls do @emph{not} use any kind of | |
7574 | interruptable locking. | |
7575 | ||
48ae6c13 RH |
7576 | @cindex @code{sync_add@var{mode}} instruction pattern |
7577 | @cindex @code{sync_sub@var{mode}} instruction pattern | |
7578 | @cindex @code{sync_ior@var{mode}} instruction pattern | |
7579 | @cindex @code{sync_and@var{mode}} instruction pattern | |
7580 | @cindex @code{sync_xor@var{mode}} instruction pattern | |
7581 | @cindex @code{sync_nand@var{mode}} instruction pattern | |
7582 | @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}} | |
7583 | @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}} | |
7584 | @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}} | |
48ae6c13 RH |
7585 | These patterns emit code for an atomic operation on memory. |
7586 | Operand 0 is the memory on which the atomic operation is performed. | |
7587 | Operand 1 is the second operand to the binary operator. | |
7588 | ||
915167f5 GK |
7589 | This pattern must issue any memory barrier instructions such that all |
7590 | memory operations before the atomic operation occur before the atomic | |
7591 | operation and all memory operations after the atomic operation occur | |
7592 | after the atomic operation. | |
48ae6c13 RH |
7593 | |
7594 | If these patterns are not defined, the operation will be constructed | |
7595 | from a compare-and-swap operation, if defined. | |
7596 | ||
7597 | @cindex @code{sync_old_add@var{mode}} instruction pattern | |
7598 | @cindex @code{sync_old_sub@var{mode}} instruction pattern | |
7599 | @cindex @code{sync_old_ior@var{mode}} instruction pattern | |
7600 | @cindex @code{sync_old_and@var{mode}} instruction pattern | |
7601 | @cindex @code{sync_old_xor@var{mode}} instruction pattern | |
7602 | @cindex @code{sync_old_nand@var{mode}} instruction pattern | |
7603 | @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}} | |
7604 | @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}} | |
7605 | @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}} | |
c29c1030 | 7606 | These patterns emit code for an atomic operation on memory, |
48ae6c13 RH |
7607 | and return the value that the memory contained before the operation. |
7608 | Operand 0 is the result value, operand 1 is the memory on which the | |
7609 | atomic operation is performed, and operand 2 is the second operand | |
7610 | to the binary operator. | |
7611 | ||
915167f5 GK |
7612 | This pattern must issue any memory barrier instructions such that all |
7613 | memory operations before the atomic operation occur before the atomic | |
7614 | operation and all memory operations after the atomic operation occur | |
7615 | after the atomic operation. | |
48ae6c13 RH |
7616 | |
7617 | If these patterns are not defined, the operation will be constructed | |
7618 | from a compare-and-swap operation, if defined. | |
7619 | ||
7620 | @cindex @code{sync_new_add@var{mode}} instruction pattern | |
7621 | @cindex @code{sync_new_sub@var{mode}} instruction pattern | |
7622 | @cindex @code{sync_new_ior@var{mode}} instruction pattern | |
7623 | @cindex @code{sync_new_and@var{mode}} instruction pattern | |
7624 | @cindex @code{sync_new_xor@var{mode}} instruction pattern | |
7625 | @cindex @code{sync_new_nand@var{mode}} instruction pattern | |
7626 | @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}} | |
7627 | @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}} | |
7628 | @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}} | |
48ae6c13 RH |
7629 | These patterns are like their @code{sync_old_@var{op}} counterparts, |
7630 | except that they return the value that exists in the memory location | |
7631 | after the operation, rather than before the operation. | |
7632 | ||
7633 | @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern | |
7634 | @item @samp{sync_lock_test_and_set@var{mode}} | |
48ae6c13 RH |
7635 | This pattern takes two forms, based on the capabilities of the target. |
7636 | In either case, operand 0 is the result of the operand, operand 1 is | |
7637 | the memory on which the atomic operation is performed, and operand 2 | |
7638 | is the value to set in the lock. | |
7639 | ||
7640 | In the ideal case, this operation is an atomic exchange operation, in | |
7641 | which the previous value in memory operand is copied into the result | |
7642 | operand, and the value operand is stored in the memory operand. | |
7643 | ||
7644 | For less capable targets, any value operand that is not the constant 1 | |
7645 | should be rejected with @code{FAIL}. In this case the target may use | |
7646 | an atomic test-and-set bit operation. The result operand should contain | |
7647 | 1 if the bit was previously set and 0 if the bit was previously clear. | |
7648 | The true contents of the memory operand are implementation defined. | |
7649 | ||
7650 | This pattern must issue any memory barrier instructions such that the | |
915167f5 GK |
7651 | pattern as a whole acts as an acquire barrier, that is all memory |
7652 | operations after the pattern do not occur until the lock is acquired. | |
48ae6c13 RH |
7653 | |
7654 | If this pattern is not defined, the operation will be constructed from | |
7655 | a compare-and-swap operation, if defined. | |
7656 | ||
7657 | @cindex @code{sync_lock_release@var{mode}} instruction pattern | |
7658 | @item @samp{sync_lock_release@var{mode}} | |
48ae6c13 RH |
7659 | This pattern, if defined, releases a lock set by |
7660 | @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory | |
8635a919 GK |
7661 | that contains the lock; operand 1 is the value to store in the lock. |
7662 | ||
7663 | If the target doesn't implement full semantics for | |
7664 | @code{sync_lock_test_and_set@var{mode}}, any value operand which is not | |
7665 | the constant 0 should be rejected with @code{FAIL}, and the true contents | |
7666 | of the memory operand are implementation defined. | |
48ae6c13 RH |
7667 | |
7668 | This pattern must issue any memory barrier instructions such that the | |
915167f5 GK |
7669 | pattern as a whole acts as a release barrier, that is the lock is |
7670 | released only after all previous memory operations have completed. | |
48ae6c13 RH |
7671 | |
7672 | If this pattern is not defined, then a @code{memory_barrier} pattern | |
8635a919 | 7673 | will be emitted, followed by a store of the value to the memory operand. |
48ae6c13 | 7674 | |
86951993 AM |
7675 | @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern |
7676 | @item @samp{atomic_compare_and_swap@var{mode}} | |
7677 | This pattern, if defined, emits code for an atomic compare-and-swap | |
7678 | operation with memory model semantics. Operand 2 is the memory on which | |
7679 | the atomic operation is performed. Operand 0 is an output operand which | |
7680 | is set to true or false based on whether the operation succeeded. Operand | |
7681 | 1 is an output operand which is set to the contents of the memory before | |
7682 | the operation was attempted. Operand 3 is the value that is expected to | |
7683 | be in memory. Operand 4 is the value to put in memory if the expected | |
7684 | value is found there. Operand 5 is set to 1 if this compare and swap is to | |
7685 | be treated as a weak operation. Operand 6 is the memory model to be used | |
7686 | if the operation is a success. Operand 7 is the memory model to be used | |
7687 | if the operation fails. | |
7688 | ||
7689 | If memory referred to in operand 2 contains the value in operand 3, then | |
7690 | operand 4 is stored in memory pointed to by operand 2 and fencing based on | |
7691 | the memory model in operand 6 is issued. | |
7692 | ||
7693 | If memory referred to in operand 2 does not contain the value in operand 3, | |
7694 | then fencing based on the memory model in operand 7 is issued. | |
7695 | ||
7696 | If a target does not support weak compare-and-swap operations, or the port | |
7697 | elects not to implement weak operations, the argument in operand 5 can be | |
7698 | ignored. Note a strong implementation must be provided. | |
7699 | ||
7700 | If this pattern is not provided, the @code{__atomic_compare_exchange} | |
7701 | built-in functions will utilize the legacy @code{sync_compare_and_swap} | |
7702 | pattern with an @code{__ATOMIC_SEQ_CST} memory model. | |
7703 | ||
7704 | @cindex @code{atomic_load@var{mode}} instruction pattern | |
7705 | @item @samp{atomic_load@var{mode}} | |
7706 | This pattern implements an atomic load operation with memory model | |
7707 | semantics. Operand 1 is the memory address being loaded from. Operand 0 | |
7708 | is the result of the load. Operand 2 is the memory model to be used for | |
7709 | the load operation. | |
7710 | ||
7711 | If not present, the @code{__atomic_load} built-in function will either | |
7712 | resort to a normal load with memory barriers, or a compare-and-swap | |
7713 | operation if a normal load would not be atomic. | |
7714 | ||
7715 | @cindex @code{atomic_store@var{mode}} instruction pattern | |
7716 | @item @samp{atomic_store@var{mode}} | |
7717 | This pattern implements an atomic store operation with memory model | |
7718 | semantics. Operand 0 is the memory address being stored to. Operand 1 | |
7719 | is the value to be written. Operand 2 is the memory model to be used for | |
7720 | the operation. | |
7721 | ||
7722 | If not present, the @code{__atomic_store} built-in function will attempt to | |
7723 | perform a normal store and surround it with any required memory fences. If | |
7724 | the store would not be atomic, then an @code{__atomic_exchange} is | |
7725 | attempted with the result being ignored. | |
7726 | ||
7727 | @cindex @code{atomic_exchange@var{mode}} instruction pattern | |
7728 | @item @samp{atomic_exchange@var{mode}} | |
7729 | This pattern implements an atomic exchange operation with memory model | |
7730 | semantics. Operand 1 is the memory location the operation is performed on. | |
7731 | Operand 0 is an output operand which is set to the original value contained | |
7732 | in the memory pointed to by operand 1. Operand 2 is the value to be | |
7733 | stored. Operand 3 is the memory model to be used. | |
7734 | ||
7735 | If this pattern is not present, the built-in function | |
7736 | @code{__atomic_exchange} will attempt to preform the operation with a | |
7737 | compare and swap loop. | |
7738 | ||
7739 | @cindex @code{atomic_add@var{mode}} instruction pattern | |
7740 | @cindex @code{atomic_sub@var{mode}} instruction pattern | |
7741 | @cindex @code{atomic_or@var{mode}} instruction pattern | |
7742 | @cindex @code{atomic_and@var{mode}} instruction pattern | |
7743 | @cindex @code{atomic_xor@var{mode}} instruction pattern | |
7744 | @cindex @code{atomic_nand@var{mode}} instruction pattern | |
7745 | @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}} | |
7746 | @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}} | |
7747 | @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}} | |
86951993 AM |
7748 | These patterns emit code for an atomic operation on memory with memory |
7749 | model semantics. Operand 0 is the memory on which the atomic operation is | |
7750 | performed. Operand 1 is the second operand to the binary operator. | |
7751 | Operand 2 is the memory model to be used by the operation. | |
7752 | ||
7753 | If these patterns are not defined, attempts will be made to use legacy | |
c29c1030 | 7754 | @code{sync} patterns, or equivalent patterns which return a result. If |
86951993 AM |
7755 | none of these are available a compare-and-swap loop will be used. |
7756 | ||
7757 | @cindex @code{atomic_fetch_add@var{mode}} instruction pattern | |
7758 | @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern | |
7759 | @cindex @code{atomic_fetch_or@var{mode}} instruction pattern | |
7760 | @cindex @code{atomic_fetch_and@var{mode}} instruction pattern | |
7761 | @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern | |
7762 | @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern | |
7763 | @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}} | |
7764 | @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}} | |
7765 | @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}} | |
86951993 AM |
7766 | These patterns emit code for an atomic operation on memory with memory |
7767 | model semantics, and return the original value. Operand 0 is an output | |
7768 | operand which contains the value of the memory location before the | |
7769 | operation was performed. Operand 1 is the memory on which the atomic | |
7770 | operation is performed. Operand 2 is the second operand to the binary | |
7771 | operator. Operand 3 is the memory model to be used by the operation. | |
7772 | ||
7773 | If these patterns are not defined, attempts will be made to use legacy | |
7774 | @code{sync} patterns. If none of these are available a compare-and-swap | |
7775 | loop will be used. | |
7776 | ||
7777 | @cindex @code{atomic_add_fetch@var{mode}} instruction pattern | |
7778 | @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern | |
7779 | @cindex @code{atomic_or_fetch@var{mode}} instruction pattern | |
7780 | @cindex @code{atomic_and_fetch@var{mode}} instruction pattern | |
7781 | @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern | |
7782 | @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern | |
7783 | @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}} | |
7784 | @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}} | |
7785 | @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}} | |
86951993 AM |
7786 | These patterns emit code for an atomic operation on memory with memory |
7787 | model semantics and return the result after the operation is performed. | |
7788 | Operand 0 is an output operand which contains the value after the | |
7789 | operation. Operand 1 is the memory on which the atomic operation is | |
7790 | performed. Operand 2 is the second operand to the binary operator. | |
7791 | Operand 3 is the memory model to be used by the operation. | |
7792 | ||
7793 | If these patterns are not defined, attempts will be made to use legacy | |
c29c1030 | 7794 | @code{sync} patterns, or equivalent patterns which return the result before |
86951993 AM |
7795 | the operation followed by the arithmetic operation required to produce the |
7796 | result. If none of these are available a compare-and-swap loop will be | |
7797 | used. | |
7798 | ||
f8a27aa6 RH |
7799 | @cindex @code{atomic_test_and_set} instruction pattern |
7800 | @item @samp{atomic_test_and_set} | |
f8a27aa6 RH |
7801 | This pattern emits code for @code{__builtin_atomic_test_and_set}. |
7802 | Operand 0 is an output operand which is set to true if the previous | |
7803 | previous contents of the byte was "set", and false otherwise. Operand 1 | |
7804 | is the @code{QImode} memory to be modified. Operand 2 is the memory | |
7805 | model to be used. | |
7806 | ||
7807 | The specific value that defines "set" is implementation defined, and | |
7808 | is normally based on what is performed by the native atomic test and set | |
7809 | instruction. | |
7810 | ||
adedd5c1 JJ |
7811 | @cindex @code{atomic_bit_test_and_set@var{mode}} instruction pattern |
7812 | @cindex @code{atomic_bit_test_and_complement@var{mode}} instruction pattern | |
7813 | @cindex @code{atomic_bit_test_and_reset@var{mode}} instruction pattern | |
7814 | @item @samp{atomic_bit_test_and_set@var{mode}} | |
7815 | @itemx @samp{atomic_bit_test_and_complement@var{mode}} | |
7816 | @itemx @samp{atomic_bit_test_and_reset@var{mode}} | |
7817 | These patterns emit code for an atomic bitwise operation on memory with memory | |
7818 | model semantics, and return the original value of the specified bit. | |
7819 | Operand 0 is an output operand which contains the value of the specified bit | |
7820 | from the memory location before the operation was performed. Operand 1 is the | |
7821 | memory on which the atomic operation is performed. Operand 2 is the bit within | |
7822 | the operand, starting with least significant bit. Operand 3 is the memory model | |
7823 | to be used by the operation. Operand 4 is a flag - it is @code{const1_rtx} | |
7824 | if operand 0 should contain the original value of the specified bit in the | |
7825 | least significant bit of the operand, and @code{const0_rtx} if the bit should | |
7826 | be in its original position in the operand. | |
7827 | @code{atomic_bit_test_and_set@var{mode}} atomically sets the specified bit after | |
7828 | remembering its original value, @code{atomic_bit_test_and_complement@var{mode}} | |
7829 | inverts the specified bit and @code{atomic_bit_test_and_reset@var{mode}} clears | |
7830 | the specified bit. | |
7831 | ||
7832 | If these patterns are not defined, attempts will be made to use | |
7833 | @code{atomic_fetch_or@var{mode}}, @code{atomic_fetch_xor@var{mode}} or | |
7834 | @code{atomic_fetch_and@var{mode}} instruction patterns, or their @code{sync} | |
7835 | counterparts. If none of these are available a compare-and-swap | |
7836 | loop will be used. | |
7837 | ||
6362627b JJ |
7838 | @cindex @code{atomic_add_fetch_cmp_0@var{mode}} instruction pattern |
7839 | @cindex @code{atomic_sub_fetch_cmp_0@var{mode}} instruction pattern | |
7840 | @cindex @code{atomic_and_fetch_cmp_0@var{mode}} instruction pattern | |
7841 | @cindex @code{atomic_or_fetch_cmp_0@var{mode}} instruction pattern | |
7842 | @cindex @code{atomic_xor_fetch_cmp_0@var{mode}} instruction pattern | |
7843 | @item @samp{atomic_add_fetch_cmp_0@var{mode}} | |
7844 | @itemx @samp{atomic_sub_fetch_cmp_0@var{mode}} | |
7845 | @itemx @samp{atomic_and_fetch_cmp_0@var{mode}} | |
7846 | @itemx @samp{atomic_or_fetch_cmp_0@var{mode}} | |
7847 | @itemx @samp{atomic_xor_fetch_cmp_0@var{mode}} | |
7848 | These patterns emit code for an atomic operation on memory with memory | |
7849 | model semantics if the fetch result is used only in a comparison against | |
7850 | zero. | |
7851 | Operand 0 is an output operand which contains a boolean result of comparison | |
7852 | of the value after the operation against zero. Operand 1 is the memory on | |
7853 | which the atomic operation is performed. Operand 2 is the second operand | |
7854 | to the binary operator. Operand 3 is the memory model to be used by the | |
7855 | operation. Operand 4 is an integer holding the comparison code, one of | |
7856 | @code{EQ}, @code{NE}, @code{LT}, @code{GT}, @code{LE} or @code{GE}. | |
7857 | ||
7858 | If these patterns are not defined, attempts will be made to use separate | |
7859 | atomic operation and fetch pattern followed by comparison of the result | |
7860 | against zero. | |
7861 | ||
5e5ccf0d AM |
7862 | @cindex @code{mem_thread_fence} instruction pattern |
7863 | @item @samp{mem_thread_fence} | |
86951993 AM |
7864 | This pattern emits code required to implement a thread fence with |
7865 | memory model semantics. Operand 0 is the memory model to be used. | |
7866 | ||
5e5ccf0d AM |
7867 | For the @code{__ATOMIC_RELAXED} model no instructions need to be issued |
7868 | and this expansion is not invoked. | |
7869 | ||
7870 | The compiler always emits a compiler memory barrier regardless of what | |
7871 | expanding this pattern produced. | |
7872 | ||
7873 | If this pattern is not defined, the compiler falls back to expanding the | |
7874 | @code{memory_barrier} pattern, then to emitting @code{__sync_synchronize} | |
7875 | library call, and finally to just placing a compiler memory barrier. | |
86951993 | 7876 | |
f959607b CLT |
7877 | @cindex @code{get_thread_pointer@var{mode}} instruction pattern |
7878 | @cindex @code{set_thread_pointer@var{mode}} instruction pattern | |
7879 | @item @samp{get_thread_pointer@var{mode}} | |
7880 | @itemx @samp{set_thread_pointer@var{mode}} | |
7881 | These patterns emit code that reads/sets the TLS thread pointer. Currently, | |
7882 | these are only needed if the target needs to support the | |
7883 | @code{__builtin_thread_pointer} and @code{__builtin_set_thread_pointer} | |
7884 | builtins. | |
7885 | ||
7886 | The get/set patterns have a single output/input operand respectively, | |
7887 | with @var{mode} intended to be @code{Pmode}. | |
7888 | ||
89d75572 TP |
7889 | @cindex @code{stack_protect_combined_set} instruction pattern |
7890 | @item @samp{stack_protect_combined_set} | |
7891 | This pattern, if defined, moves a @code{ptr_mode} value from an address | |
7892 | whose declaration RTX is given in operand 1 to the memory in operand 0 | |
7893 | without leaving the value in a register afterward. If several | |
7894 | instructions are needed by the target to perform the operation (eg. to | |
7895 | load the address from a GOT entry then load the @code{ptr_mode} value | |
7896 | and finally store it), it is the backend's responsibility to ensure no | |
7897 | intermediate result gets spilled. This is to avoid leaking the value | |
7898 | some place that an attacker might use to rewrite the stack guard slot | |
7899 | after having clobbered it. | |
7900 | ||
7901 | If this pattern is not defined, then the address declaration is | |
7902 | expanded first in the standard way and a @code{stack_protect_set} | |
7903 | pattern is then generated to move the value from that address to the | |
7904 | address in operand 0. | |
7905 | ||
7d69de61 RH |
7906 | @cindex @code{stack_protect_set} instruction pattern |
7907 | @item @samp{stack_protect_set} | |
89d75572 TP |
7908 | This pattern, if defined, moves a @code{ptr_mode} value from the valid |
7909 | memory location in operand 1 to the memory in operand 0 without leaving | |
7910 | the value in a register afterward. This is to avoid leaking the value | |
7911 | some place that an attacker might use to rewrite the stack guard slot | |
7912 | after having clobbered it. | |
7913 | ||
7914 | Note: on targets where the addressing modes do not allow to load | |
7915 | directly from stack guard address, the address is expanded in a standard | |
7916 | way first which could cause some spills. | |
7d69de61 RH |
7917 | |
7918 | If this pattern is not defined, then a plain move pattern is generated. | |
7919 | ||
89d75572 TP |
7920 | @cindex @code{stack_protect_combined_test} instruction pattern |
7921 | @item @samp{stack_protect_combined_test} | |
7922 | This pattern, if defined, compares a @code{ptr_mode} value from an | |
7923 | address whose declaration RTX is given in operand 1 with the memory in | |
7924 | operand 0 without leaving the value in a register afterward and | |
7925 | branches to operand 2 if the values were equal. If several | |
7926 | instructions are needed by the target to perform the operation (eg. to | |
7927 | load the address from a GOT entry then load the @code{ptr_mode} value | |
7928 | and finally store it), it is the backend's responsibility to ensure no | |
7929 | intermediate result gets spilled. This is to avoid leaking the value | |
7930 | some place that an attacker might use to rewrite the stack guard slot | |
7931 | after having clobbered it. | |
7932 | ||
7933 | If this pattern is not defined, then the address declaration is | |
7934 | expanded first in the standard way and a @code{stack_protect_test} | |
7935 | pattern is then generated to compare the value from that address to the | |
7936 | value at the memory in operand 0. | |
7937 | ||
7d69de61 RH |
7938 | @cindex @code{stack_protect_test} instruction pattern |
7939 | @item @samp{stack_protect_test} | |
643e867f | 7940 | This pattern, if defined, compares a @code{ptr_mode} value from the |
89d75572 TP |
7941 | valid memory location in operand 1 with the memory in operand 0 without |
7942 | leaving the value in a register afterward and branches to operand 2 if | |
7943 | the values were equal. | |
7d69de61 | 7944 | |
3aebbe5f JJ |
7945 | If this pattern is not defined, then a plain compare pattern and |
7946 | conditional branch pattern is used. | |
7d69de61 | 7947 | |
677feb77 DD |
7948 | @cindex @code{clear_cache} instruction pattern |
7949 | @item @samp{clear_cache} | |
677feb77 DD |
7950 | This pattern, if defined, flushes the instruction cache for a region of |
7951 | memory. The region is bounded to by the Pmode pointers in operand 0 | |
7952 | inclusive and operand 1 exclusive. | |
7953 | ||
7954 | If this pattern is not defined, a call to the library function | |
7955 | @code{__clear_cache} is used. | |
7956 | ||
463d9108 JJ |
7957 | @cindex @code{spaceship@var{m}3} instruction pattern |
7958 | @item @samp{spaceship@var{m}3} | |
7959 | Initialize output operand 0 with mode of integer type to -1, 0, 1 or 2 | |
7960 | if operand 1 with mode @var{m} compares less than operand 2, equal to | |
7961 | operand 2, greater than operand 2 or is unordered with operand 2. | |
7962 | @var{m} should be a scalar floating point mode. | |
7963 | ||
7964 | This pattern is not allowed to @code{FAIL}. | |
7965 | ||
03dda8e3 RK |
7966 | @end table |
7967 | ||
a5249a21 HPN |
7968 | @end ifset |
7969 | @c Each of the following nodes are wrapped in separate | |
7970 | @c "@ifset INTERNALS" to work around memory limits for the default | |
7971 | @c configuration in older tetex distributions. Known to not work: | |
7972 | @c tetex-1.0.7, known to work: tetex-2.0.2. | |
7973 | @ifset INTERNALS | |
03dda8e3 RK |
7974 | @node Pattern Ordering |
7975 | @section When the Order of Patterns Matters | |
7976 | @cindex Pattern Ordering | |
7977 | @cindex Ordering of Patterns | |
7978 | ||
7979 | Sometimes an insn can match more than one instruction pattern. Then the | |
7980 | pattern that appears first in the machine description is the one used. | |
7981 | Therefore, more specific patterns (patterns that will match fewer things) | |
7982 | and faster instructions (those that will produce better code when they | |
7983 | do match) should usually go first in the description. | |
7984 | ||
7985 | In some cases the effect of ordering the patterns can be used to hide | |
7986 | a pattern when it is not valid. For example, the 68000 has an | |
7987 | instruction for converting a fullword to floating point and another | |
7988 | for converting a byte to floating point. An instruction converting | |
7989 | an integer to floating point could match either one. We put the | |
7990 | pattern to convert the fullword first to make sure that one will | |
7991 | be used rather than the other. (Otherwise a large integer might | |
7992 | be generated as a single-byte immediate quantity, which would not work.) | |
7993 | Instead of using this pattern ordering it would be possible to make the | |
7994 | pattern for convert-a-byte smart enough to deal properly with any | |
7995 | constant value. | |
7996 | ||
a5249a21 HPN |
7997 | @end ifset |
7998 | @ifset INTERNALS | |
03dda8e3 RK |
7999 | @node Dependent Patterns |
8000 | @section Interdependence of Patterns | |
8001 | @cindex Dependent Patterns | |
8002 | @cindex Interdependence of Patterns | |
8003 | ||
03dda8e3 RK |
8004 | In some cases machines support instructions identical except for the |
8005 | machine mode of one or more operands. For example, there may be | |
8006 | ``sign-extend halfword'' and ``sign-extend byte'' instructions whose | |
8007 | patterns are | |
8008 | ||
3ab51846 | 8009 | @smallexample |
03dda8e3 RK |
8010 | (set (match_operand:SI 0 @dots{}) |
8011 | (extend:SI (match_operand:HI 1 @dots{}))) | |
8012 | ||
8013 | (set (match_operand:SI 0 @dots{}) | |
8014 | (extend:SI (match_operand:QI 1 @dots{}))) | |
3ab51846 | 8015 | @end smallexample |
03dda8e3 RK |
8016 | |
8017 | @noindent | |
8018 | Constant integers do not specify a machine mode, so an instruction to | |
8019 | extend a constant value could match either pattern. The pattern it | |
8020 | actually will match is the one that appears first in the file. For correct | |
8021 | results, this must be the one for the widest possible mode (@code{HImode}, | |
8022 | here). If the pattern matches the @code{QImode} instruction, the results | |
8023 | will be incorrect if the constant value does not actually fit that mode. | |
8024 | ||
8025 | Such instructions to extend constants are rarely generated because they are | |
8026 | optimized away, but they do occasionally happen in nonoptimized | |
8027 | compilations. | |
8028 | ||
8029 | If a constraint in a pattern allows a constant, the reload pass may | |
8030 | replace a register with a constant permitted by the constraint in some | |
8031 | cases. Similarly for memory references. Because of this substitution, | |
8032 | you should not provide separate patterns for increment and decrement | |
8033 | instructions. Instead, they should be generated from the same pattern | |
8034 | that supports register-register add insns by examining the operands and | |
8035 | generating the appropriate machine instruction. | |
8036 | ||
a5249a21 HPN |
8037 | @end ifset |
8038 | @ifset INTERNALS | |
03dda8e3 RK |
8039 | @node Jump Patterns |
8040 | @section Defining Jump Instruction Patterns | |
8041 | @cindex jump instruction patterns | |
8042 | @cindex defining jump instruction patterns | |
8043 | ||
f90b7a5a PB |
8044 | GCC does not assume anything about how the machine realizes jumps. |
8045 | The machine description should define a single pattern, usually | |
8046 | a @code{define_expand}, which expands to all the required insns. | |
8047 | ||
8048 | Usually, this would be a comparison insn to set the condition code | |
8049 | and a separate branch insn testing the condition code and branching | |
8050 | or not according to its value. For many machines, however, | |
8051 | separating compares and branches is limiting, which is why the | |
8052 | more flexible approach with one @code{define_expand} is used in GCC. | |
8053 | The machine description becomes clearer for architectures that | |
8054 | have compare-and-branch instructions but no condition code. It also | |
8055 | works better when different sets of comparison operators are supported | |
630ba2fd SB |
8056 | by different kinds of conditional branches (e.g.@: integer vs.@: |
8057 | floating-point), or by conditional branches with respect to conditional stores. | |
f90b7a5a | 8058 | |
bd1cd0d0 SB |
8059 | Two separate insns are always used on most machines that use a separate |
8060 | condition code register (@pxref{Condition Code}). | |
f90b7a5a PB |
8061 | |
8062 | Even in this case having a single entry point for conditional branches | |
8063 | is advantageous, because it handles equally well the case where a single | |
8064 | comparison instruction records the results of both signed and unsigned | |
8065 | comparison of the given operands (with the branch insns coming in distinct | |
8066 | signed and unsigned flavors) as in the x86 or SPARC, and the case where | |
8067 | there are distinct signed and unsigned compare instructions and only | |
8068 | one set of conditional branch instructions as in the PowerPC. | |
03dda8e3 | 8069 | |
a5249a21 HPN |
8070 | @end ifset |
8071 | @ifset INTERNALS | |
6e4fcc95 MH |
8072 | @node Looping Patterns |
8073 | @section Defining Looping Instruction Patterns | |
8074 | @cindex looping instruction patterns | |
8075 | @cindex defining looping instruction patterns | |
8076 | ||
05713b80 | 8077 | Some machines have special jump instructions that can be utilized to |
6e4fcc95 MH |
8078 | make loops more efficient. A common example is the 68000 @samp{dbra} |
8079 | instruction which performs a decrement of a register and a branch if the | |
8080 | result was greater than zero. Other machines, in particular digital | |
8081 | signal processors (DSPs), have special block repeat instructions to | |
8082 | provide low-overhead loop support. For example, the TI TMS320C3x/C4x | |
8083 | DSPs have a block repeat instruction that loads special registers to | |
8084 | mark the top and end of a loop and to count the number of loop | |
8085 | iterations. This avoids the need for fetching and executing a | |
c771326b | 8086 | @samp{dbra}-like instruction and avoids pipeline stalls associated with |
6e4fcc95 MH |
8087 | the jump. |
8088 | ||
f9adcdec PK |
8089 | GCC has two special named patterns to support low overhead looping. |
8090 | They are @samp{doloop_begin} and @samp{doloop_end}. These are emitted | |
8091 | by the loop optimizer for certain well-behaved loops with a finite | |
8092 | number of loop iterations using information collected during strength | |
8093 | reduction. | |
6e4fcc95 MH |
8094 | |
8095 | The @samp{doloop_end} pattern describes the actual looping instruction | |
8096 | (or the implicit looping operation) and the @samp{doloop_begin} pattern | |
c21cd8b1 | 8097 | is an optional companion pattern that can be used for initialization |
6e4fcc95 MH |
8098 | needed for some low-overhead looping instructions. |
8099 | ||
8100 | Note that some machines require the actual looping instruction to be | |
8101 | emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting | |
8102 | the true RTL for a looping instruction at the top of the loop can cause | |
8103 | problems with flow analysis. So instead, a dummy @code{doloop} insn is | |
8104 | emitted at the end of the loop. The machine dependent reorg pass checks | |
8105 | for the presence of this @code{doloop} insn and then searches back to | |
8106 | the top of the loop, where it inserts the true looping insn (provided | |
8107 | there are no instructions in the loop which would cause problems). Any | |
8108 | additional labels can be emitted at this point. In addition, if the | |
8109 | desired special iteration counter register was not allocated, this | |
8110 | machine dependent reorg pass could emit a traditional compare and jump | |
8111 | instruction pair. | |
8112 | ||
f9adcdec PK |
8113 | For the @samp{doloop_end} pattern, the loop optimizer allocates an |
8114 | additional pseudo register as an iteration counter. This pseudo | |
8115 | register cannot be used within the loop (i.e., general induction | |
8116 | variables cannot be derived from it), however, in many cases the loop | |
8117 | induction variable may become redundant and removed by the flow pass. | |
8118 | ||
8119 | The @samp{doloop_end} pattern must have a specific structure to be | |
8120 | handled correctly by GCC. The example below is taken (slightly | |
8121 | simplified) from the PDP-11 target: | |
8122 | ||
8123 | @smallexample | |
8124 | @group | |
a01abe9d PK |
8125 | (define_expand "doloop_end" |
8126 | [(parallel [(set (pc) | |
8127 | (if_then_else | |
8128 | (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m") | |
8129 | (const_int 1)) | |
8130 | (label_ref (match_operand 1 "" "")) | |
8131 | (pc))) | |
8132 | (set (match_dup 0) | |
8133 | (plus:HI (match_dup 0) | |
8134 | (const_int -1)))])] | |
8135 | "" | |
8136 | "@{ | |
8137 | if (GET_MODE (operands[0]) != HImode) | |
8138 | FAIL; | |
8139 | @}") | |
8140 | ||
8141 | (define_insn "doloop_end_insn" | |
f9adcdec PK |
8142 | [(set (pc) |
8143 | (if_then_else | |
8144 | (ne (match_operand:HI 0 "nonimmediate_operand" "+r,!m") | |
8145 | (const_int 1)) | |
8146 | (label_ref (match_operand 1 "" "")) | |
8147 | (pc))) | |
8148 | (set (match_dup 0) | |
8149 | (plus:HI (match_dup 0) | |
8150 | (const_int -1)))] | |
8151 | "" | |
8152 | ||
8153 | @{ | |
8154 | if (which_alternative == 0) | |
8155 | return "sob %0,%l1"; | |
8156 | ||
8157 | /* emulate sob */ | |
8158 | output_asm_insn ("dec %0", operands); | |
8159 | return "bne %l1"; | |
8160 | @}) | |
8161 | @end group | |
8162 | @end smallexample | |
8163 | ||
8164 | The first part of the pattern describes the branch condition. GCC | |
8165 | supports three cases for the way the target machine handles the loop | |
8166 | counter: | |
8167 | @itemize @bullet | |
8168 | @item Loop terminates when the loop register decrements to zero. This | |
8169 | is represented by a @code{ne} comparison of the register (its old value) | |
8170 | with constant 1 (as in the example above). | |
8171 | @item Loop terminates when the loop register decrements to @minus{}1. | |
8172 | This is represented by a @code{ne} comparison of the register with | |
8173 | constant zero. | |
8174 | @item Loop terminates when the loop register decrements to a negative | |
8175 | value. This is represented by a @code{ge} comparison of the register | |
8176 | with constant zero. For this case, GCC will attach a @code{REG_NONNEG} | |
8177 | note to the @code{doloop_end} insn if it can determine that the register | |
8178 | will be non-negative. | |
8179 | @end itemize | |
6e4fcc95 | 8180 | |
f9adcdec PK |
8181 | Since the @code{doloop_end} insn is a jump insn that also has an output, |
8182 | the reload pass does not handle the output operand. Therefore, the | |
8183 | constraint must allow for that operand to be in memory rather than a | |
a01abe9d PK |
8184 | register. In the example shown above, that is handled (in the |
8185 | @code{doloop_end_insn} pattern) by using a loop instruction sequence | |
8186 | that can handle memory operands when the memory alternative appears. | |
8187 | ||
8188 | GCC does not check the mode of the loop register operand when generating | |
8189 | the @code{doloop_end} pattern. If the pattern is only valid for some | |
8190 | modes but not others, the pattern should be a @code{define_expand} | |
8191 | pattern that checks the operand mode in the preparation code, and issues | |
8192 | @code{FAIL} if an unsupported mode is found. The example above does | |
8193 | this, since the machine instruction to be used only exists for | |
8194 | @code{HImode}. | |
8195 | ||
8196 | If the @code{doloop_end} pattern is a @code{define_expand}, there must | |
8197 | also be a @code{define_insn} or @code{define_insn_and_split} matching | |
8198 | the generated pattern. Otherwise, the compiler will fail during loop | |
8199 | optimization. | |
6e4fcc95 | 8200 | |
a5249a21 HPN |
8201 | @end ifset |
8202 | @ifset INTERNALS | |
03dda8e3 RK |
8203 | @node Insn Canonicalizations |
8204 | @section Canonicalization of Instructions | |
8205 | @cindex canonicalization of instructions | |
8206 | @cindex insn canonicalization | |
8207 | ||
8208 | There are often cases where multiple RTL expressions could represent an | |
8209 | operation performed by a single machine instruction. This situation is | |
8210 | most commonly encountered with logical, branch, and multiply-accumulate | |
8211 | instructions. In such cases, the compiler attempts to convert these | |
8212 | multiple RTL expressions into a single canonical form to reduce the | |
8213 | number of insn patterns required. | |
8214 | ||
8215 | In addition to algebraic simplifications, following canonicalizations | |
8216 | are performed: | |
8217 | ||
8218 | @itemize @bullet | |
8219 | @item | |
8220 | For commutative and comparison operators, a constant is always made the | |
8221 | second operand. If a machine only supports a constant as the second | |
8222 | operand, only patterns that match a constant in the second operand need | |
8223 | be supplied. | |
8224 | ||
e3d6e740 GK |
8225 | @item |
8226 | For associative operators, a sequence of operators will always chain | |
8227 | to the left; for instance, only the left operand of an integer @code{plus} | |
8228 | can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor}, | |
8229 | @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and | |
8230 | @code{umax} are associative when applied to integers, and sometimes to | |
8231 | floating-point. | |
8232 | ||
8233 | @item | |
03dda8e3 RK |
8234 | @cindex @code{neg}, canonicalization of |
8235 | @cindex @code{not}, canonicalization of | |
8236 | @cindex @code{mult}, canonicalization of | |
8237 | @cindex @code{plus}, canonicalization of | |
8238 | @cindex @code{minus}, canonicalization of | |
8239 | For these operators, if only one operand is a @code{neg}, @code{not}, | |
8240 | @code{mult}, @code{plus}, or @code{minus} expression, it will be the | |
8241 | first operand. | |
8242 | ||
16823694 GK |
8243 | @item |
8244 | In combinations of @code{neg}, @code{mult}, @code{plus}, and | |
8245 | @code{minus}, the @code{neg} operations (if any) will be moved inside | |
daf2f129 | 8246 | the operations as far as possible. For instance, |
16823694 | 8247 | @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but |
9302a061 | 8248 | @code{(plus (mult (neg B) C) A)} is canonicalized as |
16823694 GK |
8249 | @code{(minus A (mult B C))}. |
8250 | ||
03dda8e3 RK |
8251 | @cindex @code{compare}, canonicalization of |
8252 | @item | |
8253 | For the @code{compare} operator, a constant is always the second operand | |
bd1cd0d0 | 8254 | if the first argument is a condition code register. |
03dda8e3 | 8255 | |
81ad201a UB |
8256 | @item |
8257 | For instructions that inherently set a condition code register, the | |
8258 | @code{compare} operator is always written as the first RTL expression of | |
8259 | the @code{parallel} instruction pattern. For example, | |
8260 | ||
8261 | @smallexample | |
8262 | (define_insn "" | |
8263 | [(set (reg:CCZ FLAGS_REG) | |
8264 | (compare:CCZ | |
8265 | (plus:SI | |
8266 | (match_operand:SI 1 "register_operand" "%r") | |
8267 | (match_operand:SI 2 "register_operand" "r")) | |
8268 | (const_int 0))) | |
8269 | (set (match_operand:SI 0 "register_operand" "=r") | |
8270 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8271 | "" | |
8272 | "addl %0, %1, %2") | |
8273 | @end smallexample | |
8274 | ||
f90b7a5a | 8275 | @item |
03dda8e3 RK |
8276 | An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or |
8277 | @code{minus} is made the first operand under the same conditions as | |
8278 | above. | |
8279 | ||
921c4418 RIL |
8280 | @item |
8281 | @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to | |
8282 | @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead | |
8283 | of @code{ltu}. | |
8284 | ||
03dda8e3 RK |
8285 | @item |
8286 | @code{(minus @var{x} (const_int @var{n}))} is converted to | |
8287 | @code{(plus @var{x} (const_int @var{-n}))}. | |
8288 | ||
8289 | @item | |
8290 | Within address computations (i.e., inside @code{mem}), a left shift is | |
8291 | converted into the appropriate multiplication by a power of two. | |
8292 | ||
8293 | @cindex @code{ior}, canonicalization of | |
8294 | @cindex @code{and}, canonicalization of | |
8295 | @cindex De Morgan's law | |
72938a4c | 8296 | @item |
090359d6 | 8297 | De Morgan's Law is used to move bitwise negation inside a bitwise |
03dda8e3 RK |
8298 | logical-and or logical-or operation. If this results in only one |
8299 | operand being a @code{not} expression, it will be the first one. | |
8300 | ||
8301 | A machine that has an instruction that performs a bitwise logical-and of one | |
8302 | operand with the bitwise negation of the other should specify the pattern | |
8303 | for that instruction as | |
8304 | ||
3ab51846 | 8305 | @smallexample |
03dda8e3 RK |
8306 | (define_insn "" |
8307 | [(set (match_operand:@var{m} 0 @dots{}) | |
8308 | (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
8309 | (match_operand:@var{m} 2 @dots{})))] | |
8310 | "@dots{}" | |
8311 | "@dots{}") | |
3ab51846 | 8312 | @end smallexample |
03dda8e3 RK |
8313 | |
8314 | @noindent | |
8315 | Similarly, a pattern for a ``NAND'' instruction should be written | |
8316 | ||
3ab51846 | 8317 | @smallexample |
03dda8e3 RK |
8318 | (define_insn "" |
8319 | [(set (match_operand:@var{m} 0 @dots{}) | |
8320 | (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{})) | |
8321 | (not:@var{m} (match_operand:@var{m} 2 @dots{}))))] | |
8322 | "@dots{}" | |
8323 | "@dots{}") | |
3ab51846 | 8324 | @end smallexample |
03dda8e3 RK |
8325 | |
8326 | In both cases, it is not necessary to include patterns for the many | |
8327 | logically equivalent RTL expressions. | |
8328 | ||
8329 | @cindex @code{xor}, canonicalization of | |
8330 | @item | |
8331 | The only possible RTL expressions involving both bitwise exclusive-or | |
8332 | and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})} | |
bd819a4a | 8333 | and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}. |
03dda8e3 RK |
8334 | |
8335 | @item | |
8336 | The sum of three items, one of which is a constant, will only appear in | |
8337 | the form | |
8338 | ||
3ab51846 | 8339 | @smallexample |
03dda8e3 | 8340 | (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant}) |
3ab51846 | 8341 | @end smallexample |
03dda8e3 | 8342 | |
03dda8e3 RK |
8343 | @cindex @code{zero_extract}, canonicalization of |
8344 | @cindex @code{sign_extract}, canonicalization of | |
8345 | @item | |
8346 | Equality comparisons of a group of bits (usually a single bit) with zero | |
8347 | will be written using @code{zero_extract} rather than the equivalent | |
8348 | @code{and} or @code{sign_extract} operations. | |
8349 | ||
c536876e AS |
8350 | @cindex @code{mult}, canonicalization of |
8351 | @item | |
8352 | @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x}) | |
8353 | (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1} | |
8354 | (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise | |
8355 | for @code{zero_extend}. | |
8356 | ||
8357 | @item | |
8358 | @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2} | |
8359 | @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted | |
8360 | to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2} | |
8361 | @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for | |
8362 | patterns using @code{zero_extend} and @code{lshiftrt}. If the second | |
8363 | operand of @code{mult} is also a shift, then that is extended also. | |
8364 | This transformation is only applied when it can be proven that the | |
8365 | original operation had sufficient precision to prevent overflow. | |
8366 | ||
03dda8e3 RK |
8367 | @end itemize |
8368 | ||
cd16503a | 8369 | Further canonicalization rules are defined in the function |
e53b6e56 | 8370 | @code{commutative_operand_precedence} in @file{gcc/rtlanal.cc}. |
cd16503a | 8371 | |
a5249a21 HPN |
8372 | @end ifset |
8373 | @ifset INTERNALS | |
03dda8e3 RK |
8374 | @node Expander Definitions |
8375 | @section Defining RTL Sequences for Code Generation | |
8376 | @cindex expander definitions | |
8377 | @cindex code generation RTL sequences | |
8378 | @cindex defining RTL sequences for code generation | |
8379 | ||
8380 | On some target machines, some standard pattern names for RTL generation | |
8381 | cannot be handled with single insn, but a sequence of RTL insns can | |
8382 | represent them. For these target machines, you can write a | |
161d7b59 | 8383 | @code{define_expand} to specify how to generate the sequence of RTL@. |
03dda8e3 RK |
8384 | |
8385 | @findex define_expand | |
8386 | A @code{define_expand} is an RTL expression that looks almost like a | |
8387 | @code{define_insn}; but, unlike the latter, a @code{define_expand} is used | |
8388 | only for RTL generation and it can produce more than one RTL insn. | |
8389 | ||
8390 | A @code{define_expand} RTX has four operands: | |
8391 | ||
8392 | @itemize @bullet | |
8393 | @item | |
8394 | The name. Each @code{define_expand} must have a name, since the only | |
8395 | use for it is to refer to it by name. | |
8396 | ||
03dda8e3 | 8397 | @item |
f3a3d0d3 RH |
8398 | The RTL template. This is a vector of RTL expressions representing |
8399 | a sequence of separate instructions. Unlike @code{define_insn}, there | |
8400 | is no implicit surrounding @code{PARALLEL}. | |
03dda8e3 RK |
8401 | |
8402 | @item | |
8403 | The condition, a string containing a C expression. This expression is | |
8404 | used to express how the availability of this pattern depends on | |
f0523f02 JM |
8405 | subclasses of target machine, selected by command-line options when GCC |
8406 | is run. This is just like the condition of a @code{define_insn} that | |
03dda8e3 RK |
8407 | has a standard name. Therefore, the condition (if present) may not |
8408 | depend on the data in the insn being matched, but only the | |
8409 | target-machine-type flags. The compiler needs to test these conditions | |
8410 | during initialization in order to learn exactly which named instructions | |
8411 | are available in a particular run. | |
8412 | ||
8413 | @item | |
8414 | The preparation statements, a string containing zero or more C | |
8415 | statements which are to be executed before RTL code is generated from | |
8416 | the RTL template. | |
8417 | ||
8418 | Usually these statements prepare temporary registers for use as | |
8419 | internal operands in the RTL template, but they can also generate RTL | |
8420 | insns directly by calling routines such as @code{emit_insn}, etc. | |
8421 | Any such insns precede the ones that come from the RTL template. | |
477c104e MK |
8422 | |
8423 | @item | |
8424 | Optionally, a vector containing the values of attributes. @xref{Insn | |
8425 | Attributes}. | |
03dda8e3 RK |
8426 | @end itemize |
8427 | ||
8428 | Every RTL insn emitted by a @code{define_expand} must match some | |
8429 | @code{define_insn} in the machine description. Otherwise, the compiler | |
8430 | will crash when trying to generate code for the insn or trying to optimize | |
8431 | it. | |
8432 | ||
8433 | The RTL template, in addition to controlling generation of RTL insns, | |
8434 | also describes the operands that need to be specified when this pattern | |
8435 | is used. In particular, it gives a predicate for each operand. | |
8436 | ||
8437 | A true operand, which needs to be specified in order to generate RTL from | |
8438 | the pattern, should be described with a @code{match_operand} in its first | |
8439 | occurrence in the RTL template. This enters information on the operand's | |
f0523f02 | 8440 | predicate into the tables that record such things. GCC uses the |
03dda8e3 RK |
8441 | information to preload the operand into a register if that is required for |
8442 | valid RTL code. If the operand is referred to more than once, subsequent | |
8443 | references should use @code{match_dup}. | |
8444 | ||
8445 | The RTL template may also refer to internal ``operands'' which are | |
8446 | temporary registers or labels used only within the sequence made by the | |
8447 | @code{define_expand}. Internal operands are substituted into the RTL | |
8448 | template with @code{match_dup}, never with @code{match_operand}. The | |
8449 | values of the internal operands are not passed in as arguments by the | |
8450 | compiler when it requests use of this pattern. Instead, they are computed | |
8451 | within the pattern, in the preparation statements. These statements | |
8452 | compute the values and store them into the appropriate elements of | |
8453 | @code{operands} so that @code{match_dup} can find them. | |
8454 | ||
8455 | There are two special macros defined for use in the preparation statements: | |
8456 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
8457 | as a statement. | |
8458 | ||
8459 | @table @code | |
8460 | ||
8461 | @findex DONE | |
8462 | @item DONE | |
8463 | Use the @code{DONE} macro to end RTL generation for the pattern. The | |
8464 | only RTL insns resulting from the pattern on this occasion will be | |
8465 | those already emitted by explicit calls to @code{emit_insn} within the | |
8466 | preparation statements; the RTL template will not be generated. | |
8467 | ||
8468 | @findex FAIL | |
8469 | @item FAIL | |
8470 | Make the pattern fail on this occasion. When a pattern fails, it means | |
8471 | that the pattern was not truly available. The calling routines in the | |
8472 | compiler will try other strategies for code generation using other patterns. | |
8473 | ||
8474 | Failure is currently supported only for binary (addition, multiplication, | |
c771326b | 8475 | shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv}) |
03dda8e3 RK |
8476 | operations. |
8477 | @end table | |
8478 | ||
55e4756f DD |
8479 | If the preparation falls through (invokes neither @code{DONE} nor |
8480 | @code{FAIL}), then the @code{define_expand} acts like a | |
8481 | @code{define_insn} in that the RTL template is used to generate the | |
8482 | insn. | |
8483 | ||
8484 | The RTL template is not used for matching, only for generating the | |
8485 | initial insn list. If the preparation statement always invokes | |
8486 | @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple | |
8487 | list of operands, such as this example: | |
8488 | ||
8489 | @smallexample | |
8490 | @group | |
8491 | (define_expand "addsi3" | |
8492 | [(match_operand:SI 0 "register_operand" "") | |
8493 | (match_operand:SI 1 "register_operand" "") | |
8494 | (match_operand:SI 2 "register_operand" "")] | |
55e4756f DD |
8495 | "" |
8496 | " | |
58097133 | 8497 | @{ |
55e4756f DD |
8498 | handle_add (operands[0], operands[1], operands[2]); |
8499 | DONE; | |
58097133 | 8500 | @}") |
55e4756f DD |
8501 | @end group |
8502 | @end smallexample | |
8503 | ||
03dda8e3 RK |
8504 | Here is an example, the definition of left-shift for the SPUR chip: |
8505 | ||
8506 | @smallexample | |
8507 | @group | |
8508 | (define_expand "ashlsi3" | |
8509 | [(set (match_operand:SI 0 "register_operand" "") | |
8510 | (ashift:SI | |
03dda8e3 RK |
8511 | (match_operand:SI 1 "register_operand" "") |
8512 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
8513 | "" | |
8514 | " | |
03dda8e3 RK |
8515 | @{ |
8516 | if (GET_CODE (operands[2]) != CONST_INT | |
8517 | || (unsigned) INTVAL (operands[2]) > 3) | |
8518 | FAIL; | |
8519 | @}") | |
8520 | @end group | |
8521 | @end smallexample | |
8522 | ||
8523 | @noindent | |
8524 | This example uses @code{define_expand} so that it can generate an RTL insn | |
8525 | for shifting when the shift-count is in the supported range of 0 to 3 but | |
8526 | fail in other cases where machine insns aren't available. When it fails, | |
8527 | the compiler tries another strategy using different patterns (such as, a | |
8528 | library call). | |
8529 | ||
8530 | If the compiler were able to handle nontrivial condition-strings in | |
8531 | patterns with names, then it would be possible to use a | |
8532 | @code{define_insn} in that case. Here is another case (zero-extension | |
8533 | on the 68000) which makes more use of the power of @code{define_expand}: | |
8534 | ||
8535 | @smallexample | |
8536 | (define_expand "zero_extendhisi2" | |
8537 | [(set (match_operand:SI 0 "general_operand" "") | |
8538 | (const_int 0)) | |
8539 | (set (strict_low_part | |
8540 | (subreg:HI | |
8541 | (match_dup 0) | |
8542 | 0)) | |
8543 | (match_operand:HI 1 "general_operand" ""))] | |
8544 | "" | |
8545 | "operands[1] = make_safe_from (operands[1], operands[0]);") | |
8546 | @end smallexample | |
8547 | ||
8548 | @noindent | |
8549 | @findex make_safe_from | |
8550 | Here two RTL insns are generated, one to clear the entire output operand | |
8551 | and the other to copy the input operand into its low half. This sequence | |
8552 | is incorrect if the input operand refers to [the old value of] the output | |
8553 | operand, so the preparation statement makes sure this isn't so. The | |
8554 | function @code{make_safe_from} copies the @code{operands[1]} into a | |
8555 | temporary register if it refers to @code{operands[0]}. It does this | |
8556 | by emitting another RTL insn. | |
8557 | ||
8558 | Finally, a third example shows the use of an internal operand. | |
8559 | Zero-extension on the SPUR chip is done by @code{and}-ing the result | |
8560 | against a halfword mask. But this mask cannot be represented by a | |
8561 | @code{const_int} because the constant value is too large to be legitimate | |
8562 | on this machine. So it must be copied into a register with | |
8563 | @code{force_reg} and then the register used in the @code{and}. | |
8564 | ||
8565 | @smallexample | |
8566 | (define_expand "zero_extendhisi2" | |
8567 | [(set (match_operand:SI 0 "register_operand" "") | |
8568 | (and:SI (subreg:SI | |
8569 | (match_operand:HI 1 "register_operand" "") | |
8570 | 0) | |
8571 | (match_dup 2)))] | |
8572 | "" | |
8573 | "operands[2] | |
3a598fbe | 8574 | = force_reg (SImode, GEN_INT (65535)); ") |
03dda8e3 RK |
8575 | @end smallexample |
8576 | ||
f4559287 | 8577 | @emph{Note:} If the @code{define_expand} is used to serve a |
c771326b | 8578 | standard binary or unary arithmetic operation or a bit-field operation, |
03dda8e3 RK |
8579 | then the last insn it generates must not be a @code{code_label}, |
8580 | @code{barrier} or @code{note}. It must be an @code{insn}, | |
8581 | @code{jump_insn} or @code{call_insn}. If you don't need a real insn | |
8582 | at the end, emit an insn to copy the result of the operation into | |
8583 | itself. Such an insn will generate no code, but it can avoid problems | |
bd819a4a | 8584 | in the compiler. |
03dda8e3 | 8585 | |
a5249a21 HPN |
8586 | @end ifset |
8587 | @ifset INTERNALS | |
03dda8e3 RK |
8588 | @node Insn Splitting |
8589 | @section Defining How to Split Instructions | |
8590 | @cindex insn splitting | |
8591 | @cindex instruction splitting | |
8592 | @cindex splitting instructions | |
8593 | ||
fae15c93 VM |
8594 | There are two cases where you should specify how to split a pattern |
8595 | into multiple insns. On machines that have instructions requiring | |
8596 | delay slots (@pxref{Delay Slots}) or that have instructions whose | |
8597 | output is not available for multiple cycles (@pxref{Processor pipeline | |
8598 | description}), the compiler phases that optimize these cases need to | |
8599 | be able to move insns into one-instruction delay slots. However, some | |
8600 | insns may generate more than one machine instruction. These insns | |
8601 | cannot be placed into a delay slot. | |
03dda8e3 RK |
8602 | |
8603 | Often you can rewrite the single insn as a list of individual insns, | |
8604 | each corresponding to one machine instruction. The disadvantage of | |
8605 | doing so is that it will cause the compilation to be slower and require | |
8606 | more space. If the resulting insns are too complex, it may also | |
8607 | suppress some optimizations. The compiler splits the insn if there is a | |
8608 | reason to believe that it might improve instruction or delay slot | |
8609 | scheduling. | |
8610 | ||
8611 | The insn combiner phase also splits putative insns. If three insns are | |
8612 | merged into one insn with a complex expression that cannot be matched by | |
8613 | some @code{define_insn} pattern, the combiner phase attempts to split | |
8614 | the complex pattern into two insns that are recognized. Usually it can | |
8615 | break the complex pattern into two patterns by splitting out some | |
8616 | subexpression. However, in some other cases, such as performing an | |
8617 | addition of a large constant in two insns on a RISC machine, the way to | |
8618 | split the addition into two insns is machine-dependent. | |
8619 | ||
f3a3d0d3 | 8620 | @findex define_split |
03dda8e3 RK |
8621 | The @code{define_split} definition tells the compiler how to split a |
8622 | complex insn into several simpler insns. It looks like this: | |
8623 | ||
8624 | @smallexample | |
8625 | (define_split | |
8626 | [@var{insn-pattern}] | |
8627 | "@var{condition}" | |
8628 | [@var{new-insn-pattern-1} | |
8629 | @var{new-insn-pattern-2} | |
8630 | @dots{}] | |
630d3d5a | 8631 | "@var{preparation-statements}") |
03dda8e3 RK |
8632 | @end smallexample |
8633 | ||
8634 | @var{insn-pattern} is a pattern that needs to be split and | |
8635 | @var{condition} is the final condition to be tested, as in a | |
8636 | @code{define_insn}. When an insn matching @var{insn-pattern} and | |
8637 | satisfying @var{condition} is found, it is replaced in the insn list | |
8638 | with the insns given by @var{new-insn-pattern-1}, | |
8639 | @var{new-insn-pattern-2}, etc. | |
8640 | ||
630d3d5a | 8641 | The @var{preparation-statements} are similar to those statements that |
03dda8e3 RK |
8642 | are specified for @code{define_expand} (@pxref{Expander Definitions}) |
8643 | and are executed before the new RTL is generated to prepare for the | |
8644 | generated code or emit some insns whose pattern is not fixed. Unlike | |
8645 | those in @code{define_expand}, however, these statements must not | |
8646 | generate any new pseudo-registers. Once reload has completed, they also | |
8647 | must not allocate any space in the stack frame. | |
8648 | ||
582d1f90 PK |
8649 | There are two special macros defined for use in the preparation statements: |
8650 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
8651 | as a statement. | |
8652 | ||
8653 | @table @code | |
8654 | ||
8655 | @findex DONE | |
8656 | @item DONE | |
8657 | Use the @code{DONE} macro to end RTL generation for the splitter. The | |
8658 | only RTL insns generated as replacement for the matched input insn will | |
8659 | be those already emitted by explicit calls to @code{emit_insn} within | |
8660 | the preparation statements; the replacement pattern is not used. | |
8661 | ||
8662 | @findex FAIL | |
8663 | @item FAIL | |
8664 | Make the @code{define_split} fail on this occasion. When a @code{define_split} | |
8665 | fails, it means that the splitter was not truly available for the inputs | |
8666 | it was given, and the input insn will not be split. | |
8667 | @end table | |
8668 | ||
8669 | If the preparation falls through (invokes neither @code{DONE} nor | |
8670 | @code{FAIL}), then the @code{define_split} uses the replacement | |
8671 | template. | |
8672 | ||
03dda8e3 RK |
8673 | Patterns are matched against @var{insn-pattern} in two different |
8674 | circumstances. If an insn needs to be split for delay slot scheduling | |
8675 | or insn scheduling, the insn is already known to be valid, which means | |
8676 | that it must have been matched by some @code{define_insn} and, if | |
df2a54e9 | 8677 | @code{reload_completed} is nonzero, is known to satisfy the constraints |
03dda8e3 RK |
8678 | of that @code{define_insn}. In that case, the new insn patterns must |
8679 | also be insns that are matched by some @code{define_insn} and, if | |
df2a54e9 | 8680 | @code{reload_completed} is nonzero, must also satisfy the constraints |
03dda8e3 RK |
8681 | of those definitions. |
8682 | ||
8683 | As an example of this usage of @code{define_split}, consider the following | |
8684 | example from @file{a29k.md}, which splits a @code{sign_extend} from | |
8685 | @code{HImode} to @code{SImode} into a pair of shift insns: | |
8686 | ||
8687 | @smallexample | |
8688 | (define_split | |
8689 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
8690 | (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] | |
8691 | "" | |
8692 | [(set (match_dup 0) | |
8693 | (ashift:SI (match_dup 1) | |
8694 | (const_int 16))) | |
8695 | (set (match_dup 0) | |
8696 | (ashiftrt:SI (match_dup 0) | |
8697 | (const_int 16)))] | |
8698 | " | |
8699 | @{ operands[1] = gen_lowpart (SImode, operands[1]); @}") | |
8700 | @end smallexample | |
8701 | ||
8702 | When the combiner phase tries to split an insn pattern, it is always the | |
8703 | case that the pattern is @emph{not} matched by any @code{define_insn}. | |
8704 | The combiner pass first tries to split a single @code{set} expression | |
8705 | and then the same @code{set} expression inside a @code{parallel}, but | |
8706 | followed by a @code{clobber} of a pseudo-reg to use as a scratch | |
8cb0906b | 8707 | register. In these cases, the combiner expects exactly one or two new insn |
03dda8e3 RK |
8708 | patterns to be generated. It will verify that these patterns match some |
8709 | @code{define_insn} definitions, so you need not do this test in the | |
8710 | @code{define_split} (of course, there is no point in writing a | |
8711 | @code{define_split} that will never produce insns that match). | |
8712 | ||
8713 | Here is an example of this use of @code{define_split}, taken from | |
8714 | @file{rs6000.md}: | |
8715 | ||
8716 | @smallexample | |
8717 | (define_split | |
8718 | [(set (match_operand:SI 0 "gen_reg_operand" "") | |
8719 | (plus:SI (match_operand:SI 1 "gen_reg_operand" "") | |
8720 | (match_operand:SI 2 "non_add_cint_operand" "")))] | |
8721 | "" | |
8722 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) | |
8723 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
8724 | " | |
8725 | @{ | |
8726 | int low = INTVAL (operands[2]) & 0xffff; | |
8727 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
8728 | ||
8729 | if (low & 0x8000) | |
8730 | high++, low |= 0xffff0000; | |
8731 | ||
3a598fbe JL |
8732 | operands[3] = GEN_INT (high << 16); |
8733 | operands[4] = GEN_INT (low); | |
03dda8e3 RK |
8734 | @}") |
8735 | @end smallexample | |
8736 | ||
8737 | Here the predicate @code{non_add_cint_operand} matches any | |
8738 | @code{const_int} that is @emph{not} a valid operand of a single add | |
8739 | insn. The add with the smaller displacement is written so that it | |
8740 | can be substituted into the address of a subsequent operation. | |
8741 | ||
8742 | An example that uses a scratch register, from the same file, generates | |
8743 | an equality comparison of a register and a large constant: | |
8744 | ||
8745 | @smallexample | |
8746 | (define_split | |
8747 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
8748 | (compare:CC (match_operand:SI 1 "gen_reg_operand" "") | |
8749 | (match_operand:SI 2 "non_short_cint_operand" ""))) | |
8750 | (clobber (match_operand:SI 3 "gen_reg_operand" ""))] | |
8751 | "find_single_use (operands[0], insn, 0) | |
8752 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
8753 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
8754 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
8755 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
8756 | " | |
8757 | @{ | |
12bcfaa1 | 8758 | /* @r{Get the constant we are comparing against, C, and see what it |
03dda8e3 | 8759 | looks like sign-extended to 16 bits. Then see what constant |
12bcfaa1 | 8760 | could be XOR'ed with C to get the sign-extended value.} */ |
03dda8e3 RK |
8761 | |
8762 | int c = INTVAL (operands[2]); | |
8763 | int sextc = (c << 16) >> 16; | |
8764 | int xorv = c ^ sextc; | |
8765 | ||
3a598fbe JL |
8766 | operands[4] = GEN_INT (xorv); |
8767 | operands[5] = GEN_INT (sextc); | |
03dda8e3 RK |
8768 | @}") |
8769 | @end smallexample | |
8770 | ||
8771 | To avoid confusion, don't write a single @code{define_split} that | |
8772 | accepts some insns that match some @code{define_insn} as well as some | |
8773 | insns that don't. Instead, write two separate @code{define_split} | |
8774 | definitions, one for the insns that are valid and one for the insns that | |
8775 | are not valid. | |
8776 | ||
6b24c259 JH |
8777 | The splitter is allowed to split jump instructions into sequence of |
8778 | jumps or create new jumps in while splitting non-jump instructions. As | |
d5f9df6a | 8779 | the control flow graph and branch prediction information needs to be updated, |
f282ffb3 | 8780 | several restriction apply. |
6b24c259 JH |
8781 | |
8782 | Splitting of jump instruction into sequence that over by another jump | |
c21cd8b1 | 8783 | instruction is always valid, as compiler expect identical behavior of new |
6b24c259 JH |
8784 | jump. When new sequence contains multiple jump instructions or new labels, |
8785 | more assistance is needed. Splitter is required to create only unconditional | |
8786 | jumps, or simple conditional jump instructions. Additionally it must attach a | |
63519d23 | 8787 | @code{REG_BR_PROB} note to each conditional jump. A global variable |
addd6f64 | 8788 | @code{split_branch_probability} holds the probability of the original branch in case |
e4ae5e77 | 8789 | it was a simple conditional jump, @minus{}1 otherwise. To simplify |
addd6f64 | 8790 | recomputing of edge frequencies, the new sequence is required to have only |
6b24c259 JH |
8791 | forward jumps to the newly created labels. |
8792 | ||
fae81b38 | 8793 | @findex define_insn_and_split |
c88c0d42 CP |
8794 | For the common case where the pattern of a define_split exactly matches the |
8795 | pattern of a define_insn, use @code{define_insn_and_split}. It looks like | |
8796 | this: | |
8797 | ||
8798 | @smallexample | |
8799 | (define_insn_and_split | |
8800 | [@var{insn-pattern}] | |
8801 | "@var{condition}" | |
8802 | "@var{output-template}" | |
8803 | "@var{split-condition}" | |
8804 | [@var{new-insn-pattern-1} | |
8805 | @var{new-insn-pattern-2} | |
8806 | @dots{}] | |
630d3d5a | 8807 | "@var{preparation-statements}" |
c88c0d42 CP |
8808 | [@var{insn-attributes}]) |
8809 | ||
8810 | @end smallexample | |
8811 | ||
8812 | @var{insn-pattern}, @var{condition}, @var{output-template}, and | |
8813 | @var{insn-attributes} are used as in @code{define_insn}. The | |
8814 | @var{new-insn-pattern} vector and the @var{preparation-statements} are used as | |
8815 | in a @code{define_split}. The @var{split-condition} is also used as in | |
8816 | @code{define_split}, with the additional behavior that if the condition starts | |
8817 | with @samp{&&}, the condition used for the split will be the constructed as a | |
d7d9c429 | 8818 | logical ``and'' of the split condition with the insn condition. For example, |
c88c0d42 CP |
8819 | from i386.md: |
8820 | ||
8821 | @smallexample | |
8822 | (define_insn_and_split "zero_extendhisi2_and" | |
8823 | [(set (match_operand:SI 0 "register_operand" "=r") | |
8824 | (zero_extend:SI (match_operand:HI 1 "register_operand" "0"))) | |
8825 | (clobber (reg:CC 17))] | |
8826 | "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size" | |
8827 | "#" | |
8828 | "&& reload_completed" | |
f282ffb3 | 8829 | [(parallel [(set (match_dup 0) |
9c34dbbf | 8830 | (and:SI (match_dup 0) (const_int 65535))) |
6ccde948 | 8831 | (clobber (reg:CC 17))])] |
c88c0d42 CP |
8832 | "" |
8833 | [(set_attr "type" "alu1")]) | |
8834 | ||
8835 | @end smallexample | |
8836 | ||
ebb48a4d | 8837 | In this case, the actual split condition will be |
aee96fe9 | 8838 | @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}. |
c88c0d42 CP |
8839 | |
8840 | The @code{define_insn_and_split} construction provides exactly the same | |
8841 | functionality as two separate @code{define_insn} and @code{define_split} | |
8842 | patterns. It exists for compactness, and as a maintenance tool to prevent | |
8843 | having to ensure the two patterns' templates match. | |
8844 | ||
f4fde1b3 RS |
8845 | @findex define_insn_and_rewrite |
8846 | It is sometimes useful to have a @code{define_insn_and_split} | |
8847 | that replaces specific operands of an instruction but leaves the | |
8848 | rest of the instruction pattern unchanged. You can do this directly | |
8849 | with a @code{define_insn_and_split}, but it requires a | |
8850 | @var{new-insn-pattern-1} that repeats most of the original @var{insn-pattern}. | |
8851 | There is also the complication that an implicit @code{parallel} in | |
8852 | @var{insn-pattern} must become an explicit @code{parallel} in | |
8853 | @var{new-insn-pattern-1}, which is easy to overlook. | |
8854 | A simpler alternative is to use @code{define_insn_and_rewrite}, which | |
8855 | is a form of @code{define_insn_and_split} that automatically generates | |
8856 | @var{new-insn-pattern-1} by replacing each @code{match_operand} | |
8857 | in @var{insn-pattern} with a corresponding @code{match_dup}, and each | |
8858 | @code{match_operator} in the pattern with a corresponding @code{match_op_dup}. | |
8859 | The arguments are otherwise identical to @code{define_insn_and_split}: | |
8860 | ||
8861 | @smallexample | |
8862 | (define_insn_and_rewrite | |
8863 | [@var{insn-pattern}] | |
8864 | "@var{condition}" | |
8865 | "@var{output-template}" | |
8866 | "@var{split-condition}" | |
8867 | "@var{preparation-statements}" | |
8868 | [@var{insn-attributes}]) | |
8869 | @end smallexample | |
8870 | ||
8871 | The @code{match_dup}s and @code{match_op_dup}s in the new | |
8872 | instruction pattern use any new operand values that the | |
8873 | @var{preparation-statements} store in the @code{operands} array, | |
8874 | as for a normal @code{define_insn_and_split}. @var{preparation-statements} | |
8875 | can also emit additional instructions before the new instruction. | |
8876 | They can even emit an entirely different sequence of instructions and | |
8877 | use @code{DONE} to avoid emitting a new form of the original | |
8878 | instruction. | |
8879 | ||
8880 | The split in a @code{define_insn_and_rewrite} is only intended | |
8881 | to apply to existing instructions that match @var{insn-pattern}. | |
8882 | @var{split-condition} must therefore start with @code{&&}, | |
8883 | so that the split condition applies on top of @var{condition}. | |
8884 | ||
8885 | Here is an example from the AArch64 SVE port, in which operand 1 is | |
8886 | known to be equivalent to an all-true constant and isn't used by the | |
8887 | output template: | |
8888 | ||
8889 | @smallexample | |
8890 | (define_insn_and_rewrite "*while_ult<GPI:mode><PRED_ALL:mode>_cc" | |
8891 | [(set (reg:CC CC_REGNUM) | |
8892 | (compare:CC | |
8893 | (unspec:SI [(match_operand:PRED_ALL 1) | |
8894 | (unspec:PRED_ALL | |
8895 | [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") | |
8896 | (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")] | |
8897 | UNSPEC_WHILE_LO)] | |
8898 | UNSPEC_PTEST_PTRUE) | |
8899 | (const_int 0))) | |
8900 | (set (match_operand:PRED_ALL 0 "register_operand" "=Upa") | |
8901 | (unspec:PRED_ALL [(match_dup 2) | |
8902 | (match_dup 3)] | |
8903 | UNSPEC_WHILE_LO))] | |
8904 | "TARGET_SVE" | |
8905 | "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3" | |
8906 | ;; Force the compiler to drop the unused predicate operand, so that we | |
8907 | ;; don't have an unnecessary PTRUE. | |
8908 | "&& !CONSTANT_P (operands[1])" | |
8909 | @{ | |
8910 | operands[1] = CONSTM1_RTX (<MODE>mode); | |
8911 | @} | |
8912 | ) | |
8913 | @end smallexample | |
8914 | ||
8915 | The splitter in this case simply replaces operand 1 with the constant | |
8916 | value that it is known to have. The equivalent @code{define_insn_and_split} | |
8917 | would be: | |
8918 | ||
8919 | @smallexample | |
8920 | (define_insn_and_split "*while_ult<GPI:mode><PRED_ALL:mode>_cc" | |
8921 | [(set (reg:CC CC_REGNUM) | |
8922 | (compare:CC | |
8923 | (unspec:SI [(match_operand:PRED_ALL 1) | |
8924 | (unspec:PRED_ALL | |
8925 | [(match_operand:GPI 2 "aarch64_reg_or_zero" "rZ") | |
8926 | (match_operand:GPI 3 "aarch64_reg_or_zero" "rZ")] | |
8927 | UNSPEC_WHILE_LO)] | |
8928 | UNSPEC_PTEST_PTRUE) | |
8929 | (const_int 0))) | |
8930 | (set (match_operand:PRED_ALL 0 "register_operand" "=Upa") | |
8931 | (unspec:PRED_ALL [(match_dup 2) | |
8932 | (match_dup 3)] | |
8933 | UNSPEC_WHILE_LO))] | |
8934 | "TARGET_SVE" | |
8935 | "whilelo\t%0.<PRED_ALL:Vetype>, %<w>2, %<w>3" | |
8936 | ;; Force the compiler to drop the unused predicate operand, so that we | |
8937 | ;; don't have an unnecessary PTRUE. | |
8938 | "&& !CONSTANT_P (operands[1])" | |
8939 | [(parallel | |
8940 | [(set (reg:CC CC_REGNUM) | |
8941 | (compare:CC | |
8942 | (unspec:SI [(match_dup 1) | |
8943 | (unspec:PRED_ALL [(match_dup 2) | |
8944 | (match_dup 3)] | |
8945 | UNSPEC_WHILE_LO)] | |
8946 | UNSPEC_PTEST_PTRUE) | |
8947 | (const_int 0))) | |
8948 | (set (match_dup 0) | |
8949 | (unspec:PRED_ALL [(match_dup 2) | |
8950 | (match_dup 3)] | |
8951 | UNSPEC_WHILE_LO))])] | |
8952 | @{ | |
8953 | operands[1] = CONSTM1_RTX (<MODE>mode); | |
8954 | @} | |
8955 | ) | |
8956 | @end smallexample | |
8957 | ||
a5249a21 HPN |
8958 | @end ifset |
8959 | @ifset INTERNALS | |
04d8aa70 AM |
8960 | @node Including Patterns |
8961 | @section Including Patterns in Machine Descriptions. | |
8962 | @cindex insn includes | |
8963 | ||
8964 | @findex include | |
8965 | The @code{include} pattern tells the compiler tools where to | |
8966 | look for patterns that are in files other than in the file | |
8a36672b | 8967 | @file{.md}. This is used only at build time and there is no preprocessing allowed. |
04d8aa70 AM |
8968 | |
8969 | It looks like: | |
8970 | ||
8971 | @smallexample | |
8972 | ||
8973 | (include | |
8974 | @var{pathname}) | |
8975 | @end smallexample | |
8976 | ||
8977 | For example: | |
8978 | ||
8979 | @smallexample | |
8980 | ||
f282ffb3 | 8981 | (include "filestuff") |
04d8aa70 AM |
8982 | |
8983 | @end smallexample | |
8984 | ||
27d30956 | 8985 | Where @var{pathname} is a string that specifies the location of the file, |
8a36672b | 8986 | specifies the include file to be in @file{gcc/config/target/filestuff}. The |
04d8aa70 AM |
8987 | directory @file{gcc/config/target} is regarded as the default directory. |
8988 | ||
8989 | ||
f282ffb3 JM |
8990 | Machine descriptions may be split up into smaller more manageable subsections |
8991 | and placed into subdirectories. | |
04d8aa70 AM |
8992 | |
8993 | By specifying: | |
8994 | ||
8995 | @smallexample | |
8996 | ||
f282ffb3 | 8997 | (include "BOGUS/filestuff") |
04d8aa70 AM |
8998 | |
8999 | @end smallexample | |
9000 | ||
9001 | the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}. | |
9002 | ||
9003 | Specifying an absolute path for the include file such as; | |
9004 | @smallexample | |
9005 | ||
f282ffb3 | 9006 | (include "/u2/BOGUS/filestuff") |
04d8aa70 AM |
9007 | |
9008 | @end smallexample | |
f282ffb3 | 9009 | is permitted but is not encouraged. |
04d8aa70 AM |
9010 | |
9011 | @subsection RTL Generation Tool Options for Directory Search | |
9012 | @cindex directory options .md | |
9013 | @cindex options, directory search | |
9014 | @cindex search options | |
9015 | ||
9016 | The @option{-I@var{dir}} option specifies directories to search for machine descriptions. | |
9017 | For example: | |
9018 | ||
9019 | @smallexample | |
9020 | ||
9021 | genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md | |
9022 | ||
9023 | @end smallexample | |
9024 | ||
9025 | ||
9026 | Add the directory @var{dir} to the head of the list of directories to be | |
9027 | searched for header files. This can be used to override a system machine definition | |
9028 | file, substituting your own version, since these directories are | |
9029 | searched before the default machine description file directories. If you use more than | |
9030 | one @option{-I} option, the directories are scanned in left-to-right | |
9031 | order; the standard default directory come after. | |
9032 | ||
9033 | ||
a5249a21 HPN |
9034 | @end ifset |
9035 | @ifset INTERNALS | |
f3a3d0d3 RH |
9036 | @node Peephole Definitions |
9037 | @section Machine-Specific Peephole Optimizers | |
9038 | @cindex peephole optimizer definitions | |
9039 | @cindex defining peephole optimizers | |
9040 | ||
9041 | In addition to instruction patterns the @file{md} file may contain | |
9042 | definitions of machine-specific peephole optimizations. | |
9043 | ||
9044 | The combiner does not notice certain peephole optimizations when the data | |
9045 | flow in the program does not suggest that it should try them. For example, | |
9046 | sometimes two consecutive insns related in purpose can be combined even | |
9047 | though the second one does not appear to use a register computed in the | |
9048 | first one. A machine-specific peephole optimizer can detect such | |
9049 | opportunities. | |
9050 | ||
9051 | There are two forms of peephole definitions that may be used. The | |
9052 | original @code{define_peephole} is run at assembly output time to | |
9053 | match insns and substitute assembly text. Use of @code{define_peephole} | |
9054 | is deprecated. | |
9055 | ||
9056 | A newer @code{define_peephole2} matches insns and substitutes new | |
9057 | insns. The @code{peephole2} pass is run after register allocation | |
ebb48a4d | 9058 | but before scheduling, which may result in much better code for |
f3a3d0d3 RH |
9059 | targets that do scheduling. |
9060 | ||
9061 | @menu | |
9062 | * define_peephole:: RTL to Text Peephole Optimizers | |
9063 | * define_peephole2:: RTL to RTL Peephole Optimizers | |
9064 | @end menu | |
9065 | ||
a5249a21 HPN |
9066 | @end ifset |
9067 | @ifset INTERNALS | |
f3a3d0d3 RH |
9068 | @node define_peephole |
9069 | @subsection RTL to Text Peephole Optimizers | |
9070 | @findex define_peephole | |
9071 | ||
9072 | @need 1000 | |
9073 | A definition looks like this: | |
9074 | ||
9075 | @smallexample | |
9076 | (define_peephole | |
9077 | [@var{insn-pattern-1} | |
9078 | @var{insn-pattern-2} | |
9079 | @dots{}] | |
9080 | "@var{condition}" | |
9081 | "@var{template}" | |
630d3d5a | 9082 | "@var{optional-insn-attributes}") |
f3a3d0d3 RH |
9083 | @end smallexample |
9084 | ||
9085 | @noindent | |
9086 | The last string operand may be omitted if you are not using any | |
9087 | machine-specific information in this machine description. If present, | |
9088 | it must obey the same rules as in a @code{define_insn}. | |
9089 | ||
9090 | In this skeleton, @var{insn-pattern-1} and so on are patterns to match | |
9091 | consecutive insns. The optimization applies to a sequence of insns when | |
9092 | @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches | |
bd819a4a | 9093 | the next, and so on. |
f3a3d0d3 RH |
9094 | |
9095 | Each of the insns matched by a peephole must also match a | |
9096 | @code{define_insn}. Peepholes are checked only at the last stage just | |
9097 | before code generation, and only optionally. Therefore, any insn which | |
9098 | would match a peephole but no @code{define_insn} will cause a crash in code | |
9099 | generation in an unoptimized compilation, or at various optimization | |
9100 | stages. | |
9101 | ||
9102 | The operands of the insns are matched with @code{match_operands}, | |
9103 | @code{match_operator}, and @code{match_dup}, as usual. What is not | |
9104 | usual is that the operand numbers apply to all the insn patterns in the | |
9105 | definition. So, you can check for identical operands in two insns by | |
9106 | using @code{match_operand} in one insn and @code{match_dup} in the | |
9107 | other. | |
9108 | ||
9109 | The operand constraints used in @code{match_operand} patterns do not have | |
9110 | any direct effect on the applicability of the peephole, but they will | |
9111 | be validated afterward, so make sure your constraints are general enough | |
9112 | to apply whenever the peephole matches. If the peephole matches | |
9113 | but the constraints are not satisfied, the compiler will crash. | |
9114 | ||
9115 | It is safe to omit constraints in all the operands of the peephole; or | |
9116 | you can write constraints which serve as a double-check on the criteria | |
9117 | previously tested. | |
9118 | ||
9119 | Once a sequence of insns matches the patterns, the @var{condition} is | |
9120 | checked. This is a C expression which makes the final decision whether to | |
9121 | perform the optimization (we do so if the expression is nonzero). If | |
9122 | @var{condition} is omitted (in other words, the string is empty) then the | |
9123 | optimization is applied to every sequence of insns that matches the | |
9124 | patterns. | |
9125 | ||
9126 | The defined peephole optimizations are applied after register allocation | |
9127 | is complete. Therefore, the peephole definition can check which | |
9128 | operands have ended up in which kinds of registers, just by looking at | |
9129 | the operands. | |
9130 | ||
9131 | @findex prev_active_insn | |
9132 | The way to refer to the operands in @var{condition} is to write | |
9133 | @code{operands[@var{i}]} for operand number @var{i} (as matched by | |
9134 | @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn} | |
9135 | to refer to the last of the insns being matched; use | |
9136 | @code{prev_active_insn} to find the preceding insns. | |
9137 | ||
9138 | @findex dead_or_set_p | |
9139 | When optimizing computations with intermediate results, you can use | |
9140 | @var{condition} to match only when the intermediate results are not used | |
9141 | elsewhere. Use the C expression @code{dead_or_set_p (@var{insn}, | |
9142 | @var{op})}, where @var{insn} is the insn in which you expect the value | |
9143 | to be used for the last time (from the value of @code{insn}, together | |
9144 | with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate | |
bd819a4a | 9145 | value (from @code{operands[@var{i}]}). |
f3a3d0d3 RH |
9146 | |
9147 | Applying the optimization means replacing the sequence of insns with one | |
9148 | new insn. The @var{template} controls ultimate output of assembler code | |
9149 | for this combined insn. It works exactly like the template of a | |
9150 | @code{define_insn}. Operand numbers in this template are the same ones | |
9151 | used in matching the original sequence of insns. | |
9152 | ||
9153 | The result of a defined peephole optimizer does not need to match any of | |
9154 | the insn patterns in the machine description; it does not even have an | |
9155 | opportunity to match them. The peephole optimizer definition itself serves | |
9156 | as the insn pattern to control how the insn is output. | |
9157 | ||
9158 | Defined peephole optimizers are run as assembler code is being output, | |
9159 | so the insns they produce are never combined or rearranged in any way. | |
9160 | ||
9161 | Here is an example, taken from the 68000 machine description: | |
9162 | ||
9163 | @smallexample | |
9164 | (define_peephole | |
9165 | [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) | |
9166 | (set (match_operand:DF 0 "register_operand" "=f") | |
9167 | (match_operand:DF 1 "register_operand" "ad"))] | |
9168 | "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" | |
f3a3d0d3 RH |
9169 | @{ |
9170 | rtx xoperands[2]; | |
a2a8cc44 | 9171 | xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
f3a3d0d3 | 9172 | #ifdef MOTOROLA |
0f40f9f7 ZW |
9173 | output_asm_insn ("move.l %1,(sp)", xoperands); |
9174 | output_asm_insn ("move.l %1,-(sp)", operands); | |
9175 | return "fmove.d (sp)+,%0"; | |
f3a3d0d3 | 9176 | #else |
0f40f9f7 ZW |
9177 | output_asm_insn ("movel %1,sp@@", xoperands); |
9178 | output_asm_insn ("movel %1,sp@@-", operands); | |
9179 | return "fmoved sp@@+,%0"; | |
f3a3d0d3 | 9180 | #endif |
0f40f9f7 | 9181 | @}) |
f3a3d0d3 RH |
9182 | @end smallexample |
9183 | ||
9184 | @need 1000 | |
9185 | The effect of this optimization is to change | |
9186 | ||
9187 | @smallexample | |
9188 | @group | |
9189 | jbsr _foobar | |
9190 | addql #4,sp | |
9191 | movel d1,sp@@- | |
9192 | movel d0,sp@@- | |
9193 | fmoved sp@@+,fp0 | |
9194 | @end group | |
9195 | @end smallexample | |
9196 | ||
9197 | @noindent | |
9198 | into | |
9199 | ||
9200 | @smallexample | |
9201 | @group | |
9202 | jbsr _foobar | |
9203 | movel d1,sp@@ | |
9204 | movel d0,sp@@- | |
9205 | fmoved sp@@+,fp0 | |
9206 | @end group | |
9207 | @end smallexample | |
9208 | ||
9209 | @ignore | |
9210 | @findex CC_REVERSED | |
9211 | If a peephole matches a sequence including one or more jump insns, you must | |
9212 | take account of the flags such as @code{CC_REVERSED} which specify that the | |
9213 | condition codes are represented in an unusual manner. The compiler | |
9214 | automatically alters any ordinary conditional jumps which occur in such | |
9215 | situations, but the compiler cannot alter jumps which have been replaced by | |
9216 | peephole optimizations. So it is up to you to alter the assembler code | |
9217 | that the peephole produces. Supply C code to write the assembler output, | |
9218 | and in this C code check the condition code status flags and change the | |
9219 | assembler code as appropriate. | |
9220 | @end ignore | |
9221 | ||
9222 | @var{insn-pattern-1} and so on look @emph{almost} like the second | |
9223 | operand of @code{define_insn}. There is one important difference: the | |
9224 | second operand of @code{define_insn} consists of one or more RTX's | |
9225 | enclosed in square brackets. Usually, there is only one: then the same | |
9226 | action can be written as an element of a @code{define_peephole}. But | |
9227 | when there are multiple actions in a @code{define_insn}, they are | |
9228 | implicitly enclosed in a @code{parallel}. Then you must explicitly | |
9229 | write the @code{parallel}, and the square brackets within it, in the | |
9230 | @code{define_peephole}. Thus, if an insn pattern looks like this, | |
9231 | ||
9232 | @smallexample | |
9233 | (define_insn "divmodsi4" | |
9234 | [(set (match_operand:SI 0 "general_operand" "=d") | |
9235 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
9236 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
9237 | (set (match_operand:SI 3 "general_operand" "=d") | |
9238 | (mod:SI (match_dup 1) (match_dup 2)))] | |
9239 | "TARGET_68020" | |
9240 | "divsl%.l %2,%3:%0") | |
9241 | @end smallexample | |
9242 | ||
9243 | @noindent | |
9244 | then the way to mention this insn in a peephole is as follows: | |
9245 | ||
9246 | @smallexample | |
9247 | (define_peephole | |
9248 | [@dots{} | |
9249 | (parallel | |
9250 | [(set (match_operand:SI 0 "general_operand" "=d") | |
9251 | (div:SI (match_operand:SI 1 "general_operand" "0") | |
9252 | (match_operand:SI 2 "general_operand" "dmsK"))) | |
9253 | (set (match_operand:SI 3 "general_operand" "=d") | |
9254 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
9255 | @dots{}] | |
9256 | @dots{}) | |
9257 | @end smallexample | |
9258 | ||
a5249a21 HPN |
9259 | @end ifset |
9260 | @ifset INTERNALS | |
f3a3d0d3 RH |
9261 | @node define_peephole2 |
9262 | @subsection RTL to RTL Peephole Optimizers | |
9263 | @findex define_peephole2 | |
9264 | ||
9265 | The @code{define_peephole2} definition tells the compiler how to | |
ebb48a4d | 9266 | substitute one sequence of instructions for another sequence, |
f3a3d0d3 RH |
9267 | what additional scratch registers may be needed and what their |
9268 | lifetimes must be. | |
9269 | ||
9270 | @smallexample | |
9271 | (define_peephole2 | |
9272 | [@var{insn-pattern-1} | |
9273 | @var{insn-pattern-2} | |
9274 | @dots{}] | |
9275 | "@var{condition}" | |
9276 | [@var{new-insn-pattern-1} | |
9277 | @var{new-insn-pattern-2} | |
9278 | @dots{}] | |
630d3d5a | 9279 | "@var{preparation-statements}") |
f3a3d0d3 RH |
9280 | @end smallexample |
9281 | ||
9282 | The definition is almost identical to @code{define_split} | |
9283 | (@pxref{Insn Splitting}) except that the pattern to match is not a | |
9284 | single instruction, but a sequence of instructions. | |
9285 | ||
9286 | It is possible to request additional scratch registers for use in the | |
9287 | output template. If appropriate registers are not free, the pattern | |
9288 | will simply not match. | |
9289 | ||
9290 | @findex match_scratch | |
9291 | @findex match_dup | |
9292 | Scratch registers are requested with a @code{match_scratch} pattern at | |
9293 | the top level of the input pattern. The allocated register (initially) will | |
9294 | be dead at the point requested within the original sequence. If the scratch | |
9295 | is used at more than a single point, a @code{match_dup} pattern at the | |
9296 | top level of the input pattern marks the last position in the input sequence | |
9297 | at which the register must be available. | |
9298 | ||
9299 | Here is an example from the IA-32 machine description: | |
9300 | ||
9301 | @smallexample | |
9302 | (define_peephole2 | |
9303 | [(match_scratch:SI 2 "r") | |
9304 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
9305 | (match_operator:SI 3 "arith_or_logical_operator" | |
9306 | [(match_dup 0) | |
9307 | (match_operand:SI 1 "memory_operand" "")])) | |
9308 | (clobber (reg:CC 17))])] | |
9309 | "! optimize_size && ! TARGET_READ_MODIFY" | |
9310 | [(set (match_dup 2) (match_dup 1)) | |
9311 | (parallel [(set (match_dup 0) | |
9312 | (match_op_dup 3 [(match_dup 0) (match_dup 2)])) | |
9313 | (clobber (reg:CC 17))])] | |
9314 | "") | |
9315 | @end smallexample | |
9316 | ||
9317 | @noindent | |
9318 | This pattern tries to split a load from its use in the hopes that we'll be | |
9319 | able to schedule around the memory load latency. It allocates a single | |
9320 | @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs | |
9321 | to be live only at the point just before the arithmetic. | |
9322 | ||
b192711e | 9323 | A real example requiring extended scratch lifetimes is harder to come by, |
f3a3d0d3 RH |
9324 | so here's a silly made-up example: |
9325 | ||
9326 | @smallexample | |
9327 | (define_peephole2 | |
9328 | [(match_scratch:SI 4 "r") | |
9329 | (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" "")) | |
9330 | (set (match_operand:SI 2 "" "") (match_dup 1)) | |
9331 | (match_dup 4) | |
9332 | (set (match_operand:SI 3 "" "") (match_dup 1))] | |
630d3d5a | 9333 | "/* @r{determine 1 does not overlap 0 and 2} */" |
f3a3d0d3 RH |
9334 | [(set (match_dup 4) (match_dup 1)) |
9335 | (set (match_dup 0) (match_dup 4)) | |
c8fbf1fa | 9336 | (set (match_dup 2) (match_dup 4)) |
f3a3d0d3 RH |
9337 | (set (match_dup 3) (match_dup 4))] |
9338 | "") | |
9339 | @end smallexample | |
9340 | ||
582d1f90 PK |
9341 | There are two special macros defined for use in the preparation statements: |
9342 | @code{DONE} and @code{FAIL}. Use them with a following semicolon, | |
9343 | as a statement. | |
9344 | ||
9345 | @table @code | |
9346 | ||
9347 | @findex DONE | |
9348 | @item DONE | |
9349 | Use the @code{DONE} macro to end RTL generation for the peephole. The | |
9350 | only RTL insns generated as replacement for the matched input insn will | |
9351 | be those already emitted by explicit calls to @code{emit_insn} within | |
9352 | the preparation statements; the replacement pattern is not used. | |
9353 | ||
9354 | @findex FAIL | |
9355 | @item FAIL | |
9356 | Make the @code{define_peephole2} fail on this occasion. When a @code{define_peephole2} | |
9357 | fails, it means that the replacement was not truly available for the | |
9358 | particular inputs it was given. In that case, GCC may still apply a | |
9359 | later @code{define_peephole2} that also matches the given insn pattern. | |
9360 | (Note that this is different from @code{define_split}, where @code{FAIL} | |
9361 | prevents the input insn from being split at all.) | |
9362 | @end table | |
9363 | ||
9364 | If the preparation falls through (invokes neither @code{DONE} nor | |
9365 | @code{FAIL}), then the @code{define_peephole2} uses the replacement | |
9366 | template. | |
9367 | ||
f3a3d0d3 | 9368 | @noindent |
a628d195 RH |
9369 | If we had not added the @code{(match_dup 4)} in the middle of the input |
9370 | sequence, it might have been the case that the register we chose at the | |
9371 | beginning of the sequence is killed by the first or second @code{set}. | |
f3a3d0d3 | 9372 | |
a5249a21 HPN |
9373 | @end ifset |
9374 | @ifset INTERNALS | |
03dda8e3 RK |
9375 | @node Insn Attributes |
9376 | @section Instruction Attributes | |
9377 | @cindex insn attributes | |
9378 | @cindex instruction attributes | |
9379 | ||
9380 | In addition to describing the instruction supported by the target machine, | |
9381 | the @file{md} file also defines a group of @dfn{attributes} and a set of | |
9382 | values for each. Every generated insn is assigned a value for each attribute. | |
9383 | One possible attribute would be the effect that the insn has on the machine's | |
bd1cd0d0 | 9384 | condition code. |
03dda8e3 RK |
9385 | |
9386 | @menu | |
9387 | * Defining Attributes:: Specifying attributes and their values. | |
9388 | * Expressions:: Valid expressions for attribute values. | |
9389 | * Tagging Insns:: Assigning attribute values to insns. | |
9390 | * Attr Example:: An example of assigning attributes. | |
9391 | * Insn Lengths:: Computing the length of insns. | |
9392 | * Constant Attributes:: Defining attributes that are constant. | |
13b72c22 | 9393 | * Mnemonic Attribute:: Obtain the instruction mnemonic as attribute value. |
03dda8e3 | 9394 | * Delay Slots:: Defining delay slots required for a machine. |
fae15c93 | 9395 | * Processor pipeline description:: Specifying information for insn scheduling. |
03dda8e3 RK |
9396 | @end menu |
9397 | ||
a5249a21 HPN |
9398 | @end ifset |
9399 | @ifset INTERNALS | |
03dda8e3 RK |
9400 | @node Defining Attributes |
9401 | @subsection Defining Attributes and their Values | |
9402 | @cindex defining attributes and their values | |
9403 | @cindex attributes, defining | |
9404 | ||
9405 | @findex define_attr | |
9406 | The @code{define_attr} expression is used to define each attribute required | |
9407 | by the target machine. It looks like: | |
9408 | ||
9409 | @smallexample | |
9410 | (define_attr @var{name} @var{list-of-values} @var{default}) | |
9411 | @end smallexample | |
9412 | ||
13b72c22 AK |
9413 | @var{name} is a string specifying the name of the attribute being |
9414 | defined. Some attributes are used in a special way by the rest of the | |
9415 | compiler. The @code{enabled} attribute can be used to conditionally | |
9416 | enable or disable insn alternatives (@pxref{Disable Insn | |
9417 | Alternatives}). The @code{predicable} attribute, together with a | |
9418 | suitable @code{define_cond_exec} (@pxref{Conditional Execution}), can | |
9419 | be used to automatically generate conditional variants of instruction | |
9420 | patterns. The @code{mnemonic} attribute can be used to check for the | |
9421 | instruction mnemonic (@pxref{Mnemonic Attribute}). The compiler | |
9422 | internally uses the names @code{ce_enabled} and @code{nonce_enabled}, | |
9423 | so they should not be used elsewhere as alternative names. | |
03dda8e3 RK |
9424 | |
9425 | @var{list-of-values} is either a string that specifies a comma-separated | |
9426 | list of values that can be assigned to the attribute, or a null string to | |
9427 | indicate that the attribute takes numeric values. | |
9428 | ||
9429 | @var{default} is an attribute expression that gives the value of this | |
9430 | attribute for insns that match patterns whose definition does not include | |
9431 | an explicit value for this attribute. @xref{Attr Example}, for more | |
9432 | information on the handling of defaults. @xref{Constant Attributes}, | |
9433 | for information on attributes that do not depend on any particular insn. | |
9434 | ||
9435 | @findex insn-attr.h | |
9436 | For each defined attribute, a number of definitions are written to the | |
9437 | @file{insn-attr.h} file. For cases where an explicit set of values is | |
9438 | specified for an attribute, the following are defined: | |
9439 | ||
9440 | @itemize @bullet | |
9441 | @item | |
9442 | A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}. | |
9443 | ||
9444 | @item | |
2eac577f | 9445 | An enumerated class is defined for @samp{attr_@var{name}} with |
03dda8e3 | 9446 | elements of the form @samp{@var{upper-name}_@var{upper-value}} where |
4bd0bee9 | 9447 | the attribute name and value are first converted to uppercase. |
03dda8e3 RK |
9448 | |
9449 | @item | |
9450 | A function @samp{get_attr_@var{name}} is defined that is passed an insn and | |
9451 | returns the attribute value for that insn. | |
9452 | @end itemize | |
9453 | ||
9454 | For example, if the following is present in the @file{md} file: | |
9455 | ||
9456 | @smallexample | |
9457 | (define_attr "type" "branch,fp,load,store,arith" @dots{}) | |
9458 | @end smallexample | |
9459 | ||
9460 | @noindent | |
9461 | the following lines will be written to the file @file{insn-attr.h}. | |
9462 | ||
9463 | @smallexample | |
d327457f | 9464 | #define HAVE_ATTR_type 1 |
03dda8e3 RK |
9465 | enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD, |
9466 | TYPE_STORE, TYPE_ARITH@}; | |
9467 | extern enum attr_type get_attr_type (); | |
9468 | @end smallexample | |
9469 | ||
9470 | If the attribute takes numeric values, no @code{enum} type will be | |
9471 | defined and the function to obtain the attribute's value will return | |
9472 | @code{int}. | |
9473 | ||
7ac28727 AK |
9474 | There are attributes which are tied to a specific meaning. These |
9475 | attributes are not free to use for other purposes: | |
9476 | ||
9477 | @table @code | |
9478 | @item length | |
9479 | The @code{length} attribute is used to calculate the length of emitted | |
9480 | code chunks. This is especially important when verifying branch | |
9481 | distances. @xref{Insn Lengths}. | |
9482 | ||
9483 | @item enabled | |
9484 | The @code{enabled} attribute can be defined to prevent certain | |
9485 | alternatives of an insn definition from being used during code | |
9486 | generation. @xref{Disable Insn Alternatives}. | |
13b72c22 AK |
9487 | |
9488 | @item mnemonic | |
9489 | The @code{mnemonic} attribute can be defined to implement instruction | |
630ba2fd | 9490 | specific checks in e.g.@: the pipeline description. |
13b72c22 | 9491 | @xref{Mnemonic Attribute}. |
7ac28727 AK |
9492 | @end table |
9493 | ||
d327457f JR |
9494 | For each of these special attributes, the corresponding |
9495 | @samp{HAVE_ATTR_@var{name}} @samp{#define} is also written when the | |
9496 | attribute is not defined; in that case, it is defined as @samp{0}. | |
9497 | ||
8f4fe86c RS |
9498 | @findex define_enum_attr |
9499 | @anchor{define_enum_attr} | |
9500 | Another way of defining an attribute is to use: | |
9501 | ||
9502 | @smallexample | |
9503 | (define_enum_attr "@var{attr}" "@var{enum}" @var{default}) | |
9504 | @end smallexample | |
9505 | ||
9506 | This works in just the same way as @code{define_attr}, except that | |
9507 | the list of values is taken from a separate enumeration called | |
9508 | @var{enum} (@pxref{define_enum}). This form allows you to use | |
9509 | the same list of values for several attributes without having to | |
9510 | repeat the list each time. For example: | |
9511 | ||
9512 | @smallexample | |
9513 | (define_enum "processor" [ | |
9514 | model_a | |
9515 | model_b | |
9516 | @dots{} | |
9517 | ]) | |
9518 | (define_enum_attr "arch" "processor" | |
9519 | (const (symbol_ref "target_arch"))) | |
9520 | (define_enum_attr "tune" "processor" | |
9521 | (const (symbol_ref "target_tune"))) | |
9522 | @end smallexample | |
9523 | ||
9524 | defines the same attributes as: | |
9525 | ||
9526 | @smallexample | |
9527 | (define_attr "arch" "model_a,model_b,@dots{}" | |
9528 | (const (symbol_ref "target_arch"))) | |
9529 | (define_attr "tune" "model_a,model_b,@dots{}" | |
9530 | (const (symbol_ref "target_tune"))) | |
9531 | @end smallexample | |
9532 | ||
9533 | but without duplicating the processor list. The second example defines two | |
9534 | separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first | |
9535 | defines a single C enum (@code{processor}). | |
a5249a21 HPN |
9536 | @end ifset |
9537 | @ifset INTERNALS | |
03dda8e3 RK |
9538 | @node Expressions |
9539 | @subsection Attribute Expressions | |
9540 | @cindex attribute expressions | |
9541 | ||
9542 | RTL expressions used to define attributes use the codes described above | |
9543 | plus a few specific to attribute definitions, to be discussed below. | |
9544 | Attribute value expressions must have one of the following forms: | |
9545 | ||
9546 | @table @code | |
9547 | @cindex @code{const_int} and attributes | |
9548 | @item (const_int @var{i}) | |
9549 | The integer @var{i} specifies the value of a numeric attribute. @var{i} | |
9550 | must be non-negative. | |
9551 | ||
9552 | The value of a numeric attribute can be specified either with a | |
00bc45c1 RH |
9553 | @code{const_int}, or as an integer represented as a string in |
9554 | @code{const_string}, @code{eq_attr} (see below), @code{attr}, | |
9555 | @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr} | |
9556 | overrides on specific instructions (@pxref{Tagging Insns}). | |
03dda8e3 RK |
9557 | |
9558 | @cindex @code{const_string} and attributes | |
9559 | @item (const_string @var{value}) | |
9560 | The string @var{value} specifies a constant attribute value. | |
9561 | If @var{value} is specified as @samp{"*"}, it means that the default value of | |
9562 | the attribute is to be used for the insn containing this expression. | |
9563 | @samp{"*"} obviously cannot be used in the @var{default} expression | |
bd819a4a | 9564 | of a @code{define_attr}. |
03dda8e3 RK |
9565 | |
9566 | If the attribute whose value is being specified is numeric, @var{value} | |
9567 | must be a string containing a non-negative integer (normally | |
9568 | @code{const_int} would be used in this case). Otherwise, it must | |
9569 | contain one of the valid values for the attribute. | |
9570 | ||
9571 | @cindex @code{if_then_else} and attributes | |
9572 | @item (if_then_else @var{test} @var{true-value} @var{false-value}) | |
9573 | @var{test} specifies an attribute test, whose format is defined below. | |
9574 | The value of this expression is @var{true-value} if @var{test} is true, | |
9575 | otherwise it is @var{false-value}. | |
9576 | ||
9577 | @cindex @code{cond} and attributes | |
9578 | @item (cond [@var{test1} @var{value1} @dots{}] @var{default}) | |
9579 | The first operand of this expression is a vector containing an even | |
9580 | number of expressions and consisting of pairs of @var{test} and @var{value} | |
9581 | expressions. The value of the @code{cond} expression is that of the | |
9582 | @var{value} corresponding to the first true @var{test} expression. If | |
9583 | none of the @var{test} expressions are true, the value of the @code{cond} | |
9584 | expression is that of the @var{default} expression. | |
9585 | @end table | |
9586 | ||
9587 | @var{test} expressions can have one of the following forms: | |
9588 | ||
9589 | @table @code | |
9590 | @cindex @code{const_int} and attribute tests | |
9591 | @item (const_int @var{i}) | |
df2a54e9 | 9592 | This test is true if @var{i} is nonzero and false otherwise. |
03dda8e3 RK |
9593 | |
9594 | @cindex @code{not} and attributes | |
9595 | @cindex @code{ior} and attributes | |
9596 | @cindex @code{and} and attributes | |
9597 | @item (not @var{test}) | |
9598 | @itemx (ior @var{test1} @var{test2}) | |
9599 | @itemx (and @var{test1} @var{test2}) | |
9600 | These tests are true if the indicated logical function is true. | |
9601 | ||
9602 | @cindex @code{match_operand} and attributes | |
9603 | @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints}) | |
9604 | This test is true if operand @var{n} of the insn whose attribute value | |
9605 | is being determined has mode @var{m} (this part of the test is ignored | |
9606 | if @var{m} is @code{VOIDmode}) and the function specified by the string | |
df2a54e9 | 9607 | @var{pred} returns a nonzero value when passed operand @var{n} and mode |
03dda8e3 RK |
9608 | @var{m} (this part of the test is ignored if @var{pred} is the null |
9609 | string). | |
9610 | ||
9611 | The @var{constraints} operand is ignored and should be the null string. | |
9612 | ||
0c0d3957 RS |
9613 | @cindex @code{match_test} and attributes |
9614 | @item (match_test @var{c-expr}) | |
9615 | The test is true if C expression @var{c-expr} is true. In non-constant | |
9616 | attributes, @var{c-expr} has access to the following variables: | |
9617 | ||
9618 | @table @var | |
9619 | @item insn | |
9620 | The rtl instruction under test. | |
9621 | @item which_alternative | |
9622 | The @code{define_insn} alternative that @var{insn} matches. | |
9623 | @xref{Output Statement}. | |
9624 | @item operands | |
9625 | An array of @var{insn}'s rtl operands. | |
9626 | @end table | |
9627 | ||
9628 | @var{c-expr} behaves like the condition in a C @code{if} statement, | |
9629 | so there is no need to explicitly convert the expression into a boolean | |
9630 | 0 or 1 value. For example, the following two tests are equivalent: | |
9631 | ||
9632 | @smallexample | |
9633 | (match_test "x & 2") | |
9634 | (match_test "(x & 2) != 0") | |
9635 | @end smallexample | |
9636 | ||
03dda8e3 RK |
9637 | @cindex @code{le} and attributes |
9638 | @cindex @code{leu} and attributes | |
9639 | @cindex @code{lt} and attributes | |
9640 | @cindex @code{gt} and attributes | |
9641 | @cindex @code{gtu} and attributes | |
9642 | @cindex @code{ge} and attributes | |
9643 | @cindex @code{geu} and attributes | |
9644 | @cindex @code{ne} and attributes | |
9645 | @cindex @code{eq} and attributes | |
9646 | @cindex @code{plus} and attributes | |
9647 | @cindex @code{minus} and attributes | |
9648 | @cindex @code{mult} and attributes | |
9649 | @cindex @code{div} and attributes | |
9650 | @cindex @code{mod} and attributes | |
9651 | @cindex @code{abs} and attributes | |
9652 | @cindex @code{neg} and attributes | |
9653 | @cindex @code{ashift} and attributes | |
9654 | @cindex @code{lshiftrt} and attributes | |
9655 | @cindex @code{ashiftrt} and attributes | |
9656 | @item (le @var{arith1} @var{arith2}) | |
9657 | @itemx (leu @var{arith1} @var{arith2}) | |
9658 | @itemx (lt @var{arith1} @var{arith2}) | |
9659 | @itemx (ltu @var{arith1} @var{arith2}) | |
9660 | @itemx (gt @var{arith1} @var{arith2}) | |
9661 | @itemx (gtu @var{arith1} @var{arith2}) | |
9662 | @itemx (ge @var{arith1} @var{arith2}) | |
9663 | @itemx (geu @var{arith1} @var{arith2}) | |
9664 | @itemx (ne @var{arith1} @var{arith2}) | |
9665 | @itemx (eq @var{arith1} @var{arith2}) | |
9666 | These tests are true if the indicated comparison of the two arithmetic | |
9667 | expressions is true. Arithmetic expressions are formed with | |
9668 | @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod}, | |
9669 | @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not}, | |
bd819a4a | 9670 | @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions. |
03dda8e3 RK |
9671 | |
9672 | @findex get_attr | |
9673 | @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn | |
9674 | Lengths},for additional forms). @code{symbol_ref} is a string | |
9675 | denoting a C expression that yields an @code{int} when evaluated by the | |
9676 | @samp{get_attr_@dots{}} routine. It should normally be a global | |
bd819a4a | 9677 | variable. |
03dda8e3 RK |
9678 | |
9679 | @findex eq_attr | |
9680 | @item (eq_attr @var{name} @var{value}) | |
9681 | @var{name} is a string specifying the name of an attribute. | |
9682 | ||
9683 | @var{value} is a string that is either a valid value for attribute | |
9684 | @var{name}, a comma-separated list of values, or @samp{!} followed by a | |
9685 | value or list. If @var{value} does not begin with a @samp{!}, this | |
9686 | test is true if the value of the @var{name} attribute of the current | |
9687 | insn is in the list specified by @var{value}. If @var{value} begins | |
9688 | with a @samp{!}, this test is true if the attribute's value is | |
9689 | @emph{not} in the specified list. | |
9690 | ||
9691 | For example, | |
9692 | ||
9693 | @smallexample | |
9694 | (eq_attr "type" "load,store") | |
9695 | @end smallexample | |
9696 | ||
9697 | @noindent | |
9698 | is equivalent to | |
9699 | ||
9700 | @smallexample | |
9701 | (ior (eq_attr "type" "load") (eq_attr "type" "store")) | |
9702 | @end smallexample | |
9703 | ||
9704 | If @var{name} specifies an attribute of @samp{alternative}, it refers to the | |
9705 | value of the compiler variable @code{which_alternative} | |
9706 | (@pxref{Output Statement}) and the values must be small integers. For | |
bd819a4a | 9707 | example, |
03dda8e3 RK |
9708 | |
9709 | @smallexample | |
9710 | (eq_attr "alternative" "2,3") | |
9711 | @end smallexample | |
9712 | ||
9713 | @noindent | |
9714 | is equivalent to | |
9715 | ||
9716 | @smallexample | |
9717 | (ior (eq (symbol_ref "which_alternative") (const_int 2)) | |
9718 | (eq (symbol_ref "which_alternative") (const_int 3))) | |
9719 | @end smallexample | |
9720 | ||
9721 | Note that, for most attributes, an @code{eq_attr} test is simplified in cases | |
9722 | where the value of the attribute being tested is known for all insns matching | |
bd819a4a | 9723 | a particular pattern. This is by far the most common case. |
03dda8e3 RK |
9724 | |
9725 | @findex attr_flag | |
9726 | @item (attr_flag @var{name}) | |
9727 | The value of an @code{attr_flag} expression is true if the flag | |
9728 | specified by @var{name} is true for the @code{insn} currently being | |
9729 | scheduled. | |
9730 | ||
9731 | @var{name} is a string specifying one of a fixed set of flags to test. | |
9732 | Test the flags @code{forward} and @code{backward} to determine the | |
81e7aa8e | 9733 | direction of a conditional branch. |
03dda8e3 RK |
9734 | |
9735 | This example describes a conditional branch delay slot which | |
9736 | can be nullified for forward branches that are taken (annul-true) or | |
9737 | for backward branches which are not taken (annul-false). | |
9738 | ||
9739 | @smallexample | |
9740 | (define_delay (eq_attr "type" "cbranch") | |
9741 | [(eq_attr "in_branch_delay" "true") | |
9742 | (and (eq_attr "in_branch_delay" "true") | |
9743 | (attr_flag "forward")) | |
9744 | (and (eq_attr "in_branch_delay" "true") | |
9745 | (attr_flag "backward"))]) | |
9746 | @end smallexample | |
9747 | ||
9748 | The @code{forward} and @code{backward} flags are false if the current | |
9749 | @code{insn} being scheduled is not a conditional branch. | |
9750 | ||
03dda8e3 RK |
9751 | @code{attr_flag} is only used during delay slot scheduling and has no |
9752 | meaning to other passes of the compiler. | |
00bc45c1 RH |
9753 | |
9754 | @findex attr | |
9755 | @item (attr @var{name}) | |
9756 | The value of another attribute is returned. This is most useful | |
9757 | for numeric attributes, as @code{eq_attr} and @code{attr_flag} | |
9758 | produce more efficient code for non-numeric attributes. | |
03dda8e3 RK |
9759 | @end table |
9760 | ||
a5249a21 HPN |
9761 | @end ifset |
9762 | @ifset INTERNALS | |
03dda8e3 RK |
9763 | @node Tagging Insns |
9764 | @subsection Assigning Attribute Values to Insns | |
9765 | @cindex tagging insns | |
9766 | @cindex assigning attribute values to insns | |
9767 | ||
9768 | The value assigned to an attribute of an insn is primarily determined by | |
9769 | which pattern is matched by that insn (or which @code{define_peephole} | |
9770 | generated it). Every @code{define_insn} and @code{define_peephole} can | |
9771 | have an optional last argument to specify the values of attributes for | |
9772 | matching insns. The value of any attribute not specified in a particular | |
9773 | insn is set to the default value for that attribute, as specified in its | |
9774 | @code{define_attr}. Extensive use of default values for attributes | |
9775 | permits the specification of the values for only one or two attributes | |
9776 | in the definition of most insn patterns, as seen in the example in the | |
bd819a4a | 9777 | next section. |
03dda8e3 RK |
9778 | |
9779 | The optional last argument of @code{define_insn} and | |
9780 | @code{define_peephole} is a vector of expressions, each of which defines | |
9781 | the value for a single attribute. The most general way of assigning an | |
9782 | attribute's value is to use a @code{set} expression whose first operand is an | |
9783 | @code{attr} expression giving the name of the attribute being set. The | |
9784 | second operand of the @code{set} is an attribute expression | |
bd819a4a | 9785 | (@pxref{Expressions}) giving the value of the attribute. |
03dda8e3 RK |
9786 | |
9787 | When the attribute value depends on the @samp{alternative} attribute | |
9788 | (i.e., which is the applicable alternative in the constraint of the | |
9789 | insn), the @code{set_attr_alternative} expression can be used. It | |
9790 | allows the specification of a vector of attribute expressions, one for | |
9791 | each alternative. | |
9792 | ||
9793 | @findex set_attr | |
9794 | When the generality of arbitrary attribute expressions is not required, | |
9795 | the simpler @code{set_attr} expression can be used, which allows | |
9796 | specifying a string giving either a single attribute value or a list | |
9797 | of attribute values, one for each alternative. | |
9798 | ||
9799 | The form of each of the above specifications is shown below. In each case, | |
9800 | @var{name} is a string specifying the attribute to be set. | |
9801 | ||
9802 | @table @code | |
9803 | @item (set_attr @var{name} @var{value-string}) | |
9804 | @var{value-string} is either a string giving the desired attribute value, | |
9805 | or a string containing a comma-separated list giving the values for | |
9806 | succeeding alternatives. The number of elements must match the number | |
9807 | of alternatives in the constraint of the insn pattern. | |
9808 | ||
9809 | Note that it may be useful to specify @samp{*} for some alternative, in | |
9810 | which case the attribute will assume its default value for insns matching | |
9811 | that alternative. | |
9812 | ||
9813 | @findex set_attr_alternative | |
9814 | @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}]) | |
9815 | Depending on the alternative of the insn, the value will be one of the | |
9816 | specified values. This is a shorthand for using a @code{cond} with | |
9817 | tests on the @samp{alternative} attribute. | |
9818 | ||
9819 | @findex attr | |
9820 | @item (set (attr @var{name}) @var{value}) | |
9821 | The first operand of this @code{set} must be the special RTL expression | |
9822 | @code{attr}, whose sole operand is a string giving the name of the | |
9823 | attribute being set. @var{value} is the value of the attribute. | |
9824 | @end table | |
9825 | ||
9826 | The following shows three different ways of representing the same | |
9827 | attribute value specification: | |
9828 | ||
9829 | @smallexample | |
9830 | (set_attr "type" "load,store,arith") | |
9831 | ||
9832 | (set_attr_alternative "type" | |
9833 | [(const_string "load") (const_string "store") | |
9834 | (const_string "arith")]) | |
9835 | ||
9836 | (set (attr "type") | |
9837 | (cond [(eq_attr "alternative" "1") (const_string "load") | |
9838 | (eq_attr "alternative" "2") (const_string "store")] | |
9839 | (const_string "arith"))) | |
9840 | @end smallexample | |
9841 | ||
9842 | @need 1000 | |
9843 | @findex define_asm_attributes | |
9844 | The @code{define_asm_attributes} expression provides a mechanism to | |
9845 | specify the attributes assigned to insns produced from an @code{asm} | |
9846 | statement. It has the form: | |
9847 | ||
9848 | @smallexample | |
9849 | (define_asm_attributes [@var{attr-sets}]) | |
9850 | @end smallexample | |
9851 | ||
9852 | @noindent | |
9853 | where @var{attr-sets} is specified the same as for both the | |
9854 | @code{define_insn} and the @code{define_peephole} expressions. | |
9855 | ||
9856 | These values will typically be the ``worst case'' attribute values. For | |
9857 | example, they might indicate that the condition code will be clobbered. | |
9858 | ||
9859 | A specification for a @code{length} attribute is handled specially. The | |
9860 | way to compute the length of an @code{asm} insn is to multiply the | |
9861 | length specified in the expression @code{define_asm_attributes} by the | |
9862 | number of machine instructions specified in the @code{asm} statement, | |
9863 | determined by counting the number of semicolons and newlines in the | |
9864 | string. Therefore, the value of the @code{length} attribute specified | |
9865 | in a @code{define_asm_attributes} should be the maximum possible length | |
9866 | of a single machine instruction. | |
9867 | ||
a5249a21 HPN |
9868 | @end ifset |
9869 | @ifset INTERNALS | |
03dda8e3 RK |
9870 | @node Attr Example |
9871 | @subsection Example of Attribute Specifications | |
9872 | @cindex attribute specifications example | |
9873 | @cindex attribute specifications | |
9874 | ||
9875 | The judicious use of defaulting is important in the efficient use of | |
9876 | insn attributes. Typically, insns are divided into @dfn{types} and an | |
9877 | attribute, customarily called @code{type}, is used to represent this | |
9878 | value. This attribute is normally used only to define the default value | |
9879 | for other attributes. An example will clarify this usage. | |
9880 | ||
9881 | Assume we have a RISC machine with a condition code and in which only | |
9882 | full-word operations are performed in registers. Let us assume that we | |
9883 | can divide all insns into loads, stores, (integer) arithmetic | |
9884 | operations, floating point operations, and branches. | |
9885 | ||
9886 | Here we will concern ourselves with determining the effect of an insn on | |
9887 | the condition code and will limit ourselves to the following possible | |
9888 | effects: The condition code can be set unpredictably (clobbered), not | |
9889 | be changed, be set to agree with the results of the operation, or only | |
9890 | changed if the item previously set into the condition code has been | |
9891 | modified. | |
9892 | ||
9893 | Here is part of a sample @file{md} file for such a machine: | |
9894 | ||
9895 | @smallexample | |
9896 | (define_attr "type" "load,store,arith,fp,branch" (const_string "arith")) | |
9897 | ||
9898 | (define_attr "cc" "clobber,unchanged,set,change0" | |
9899 | (cond [(eq_attr "type" "load") | |
9900 | (const_string "change0") | |
9901 | (eq_attr "type" "store,branch") | |
9902 | (const_string "unchanged") | |
9903 | (eq_attr "type" "arith") | |
9904 | (if_then_else (match_operand:SI 0 "" "") | |
9905 | (const_string "set") | |
9906 | (const_string "clobber"))] | |
9907 | (const_string "clobber"))) | |
9908 | ||
9909 | (define_insn "" | |
9910 | [(set (match_operand:SI 0 "general_operand" "=r,r,m") | |
9911 | (match_operand:SI 1 "general_operand" "r,m,r"))] | |
9912 | "" | |
9913 | "@@ | |
9914 | move %0,%1 | |
9915 | load %0,%1 | |
9916 | store %0,%1" | |
9917 | [(set_attr "type" "arith,load,store")]) | |
9918 | @end smallexample | |
9919 | ||
9920 | Note that we assume in the above example that arithmetic operations | |
9921 | performed on quantities smaller than a machine word clobber the condition | |
9922 | code since they will set the condition code to a value corresponding to the | |
9923 | full-word result. | |
9924 | ||
a5249a21 HPN |
9925 | @end ifset |
9926 | @ifset INTERNALS | |
03dda8e3 RK |
9927 | @node Insn Lengths |
9928 | @subsection Computing the Length of an Insn | |
9929 | @cindex insn lengths, computing | |
9930 | @cindex computing the length of an insn | |
9931 | ||
9932 | For many machines, multiple types of branch instructions are provided, each | |
9933 | for different length branch displacements. In most cases, the assembler | |
9934 | will choose the correct instruction to use. However, when the assembler | |
b49900cc | 9935 | cannot do so, GCC can when a special attribute, the @code{length} |
03dda8e3 RK |
9936 | attribute, is defined. This attribute must be defined to have numeric |
9937 | values by specifying a null string in its @code{define_attr}. | |
9938 | ||
b49900cc | 9939 | In the case of the @code{length} attribute, two additional forms of |
03dda8e3 RK |
9940 | arithmetic terms are allowed in test expressions: |
9941 | ||
9942 | @table @code | |
9943 | @cindex @code{match_dup} and attributes | |
9944 | @item (match_dup @var{n}) | |
9945 | This refers to the address of operand @var{n} of the current insn, which | |
9946 | must be a @code{label_ref}. | |
9947 | ||
9948 | @cindex @code{pc} and attributes | |
9949 | @item (pc) | |
0c94b59f EB |
9950 | For non-branch instructions and backward branch instructions, this refers |
9951 | to the address of the current insn. But for forward branch instructions, | |
9952 | this refers to the address of the next insn, because the length of the | |
03dda8e3 RK |
9953 | current insn is to be computed. |
9954 | @end table | |
9955 | ||
9956 | @cindex @code{addr_vec}, length of | |
9957 | @cindex @code{addr_diff_vec}, length of | |
9958 | For normal insns, the length will be determined by value of the | |
b49900cc | 9959 | @code{length} attribute. In the case of @code{addr_vec} and |
03dda8e3 RK |
9960 | @code{addr_diff_vec} insn patterns, the length is computed as |
9961 | the number of vectors multiplied by the size of each vector. | |
9962 | ||
9963 | Lengths are measured in addressable storage units (bytes). | |
9964 | ||
40da08e0 JL |
9965 | Note that it is possible to call functions via the @code{symbol_ref} |
9966 | mechanism to compute the length of an insn. However, if you use this | |
9967 | mechanism you must provide dummy clauses to express the maximum length | |
b5405bab | 9968 | without using the function call. You can see an example of this in the |
40da08e0 JL |
9969 | @code{pa} machine description for the @code{call_symref} pattern. |
9970 | ||
03dda8e3 RK |
9971 | The following macros can be used to refine the length computation: |
9972 | ||
9973 | @table @code | |
03dda8e3 RK |
9974 | @findex ADJUST_INSN_LENGTH |
9975 | @item ADJUST_INSN_LENGTH (@var{insn}, @var{length}) | |
9976 | If defined, modifies the length assigned to instruction @var{insn} as a | |
9977 | function of the context in which it is used. @var{length} is an lvalue | |
9978 | that contains the initially computed length of the insn and should be | |
a8aa4e0b | 9979 | updated with the correct length of the insn. |
03dda8e3 RK |
9980 | |
9981 | This macro will normally not be required. A case in which it is | |
161d7b59 | 9982 | required is the ROMP@. On this machine, the size of an @code{addr_vec} |
03dda8e3 RK |
9983 | insn must be increased by two to compensate for the fact that alignment |
9984 | may be required. | |
9985 | @end table | |
9986 | ||
9987 | @findex get_attr_length | |
9988 | The routine that returns @code{get_attr_length} (the value of the | |
9989 | @code{length} attribute) can be used by the output routine to | |
9990 | determine the form of the branch instruction to be written, as the | |
9991 | example below illustrates. | |
9992 | ||
9993 | As an example of the specification of variable-length branches, consider | |
9994 | the IBM 360. If we adopt the convention that a register will be set to | |
9995 | the starting address of a function, we can jump to labels within 4k of | |
9996 | the start using a four-byte instruction. Otherwise, we need a six-byte | |
9997 | sequence to load the address from memory and then branch to it. | |
9998 | ||
9999 | On such a machine, a pattern for a branch instruction might be specified | |
10000 | as follows: | |
10001 | ||
10002 | @smallexample | |
10003 | (define_insn "jump" | |
10004 | [(set (pc) | |
10005 | (label_ref (match_operand 0 "" "")))] | |
10006 | "" | |
03dda8e3 RK |
10007 | @{ |
10008 | return (get_attr_length (insn) == 4 | |
0f40f9f7 ZW |
10009 | ? "b %l0" : "l r15,=a(%l0); br r15"); |
10010 | @} | |
9c34dbbf ZW |
10011 | [(set (attr "length") |
10012 | (if_then_else (lt (match_dup 0) (const_int 4096)) | |
10013 | (const_int 4) | |
10014 | (const_int 6)))]) | |
03dda8e3 RK |
10015 | @end smallexample |
10016 | ||
a5249a21 HPN |
10017 | @end ifset |
10018 | @ifset INTERNALS | |
03dda8e3 RK |
10019 | @node Constant Attributes |
10020 | @subsection Constant Attributes | |
10021 | @cindex constant attributes | |
10022 | ||
10023 | A special form of @code{define_attr}, where the expression for the | |
10024 | default value is a @code{const} expression, indicates an attribute that | |
10025 | is constant for a given run of the compiler. Constant attributes may be | |
10026 | used to specify which variety of processor is used. For example, | |
10027 | ||
10028 | @smallexample | |
10029 | (define_attr "cpu" "m88100,m88110,m88000" | |
10030 | (const | |
10031 | (cond [(symbol_ref "TARGET_88100") (const_string "m88100") | |
10032 | (symbol_ref "TARGET_88110") (const_string "m88110")] | |
10033 | (const_string "m88000")))) | |
10034 | ||
10035 | (define_attr "memory" "fast,slow" | |
10036 | (const | |
10037 | (if_then_else (symbol_ref "TARGET_FAST_MEM") | |
10038 | (const_string "fast") | |
10039 | (const_string "slow")))) | |
10040 | @end smallexample | |
10041 | ||
10042 | The routine generated for constant attributes has no parameters as it | |
10043 | does not depend on any particular insn. RTL expressions used to define | |
10044 | the value of a constant attribute may use the @code{symbol_ref} form, | |
10045 | but may not use either the @code{match_operand} form or @code{eq_attr} | |
10046 | forms involving insn attributes. | |
10047 | ||
13b72c22 AK |
10048 | @end ifset |
10049 | @ifset INTERNALS | |
10050 | @node Mnemonic Attribute | |
10051 | @subsection Mnemonic Attribute | |
10052 | @cindex mnemonic attribute | |
10053 | ||
10054 | The @code{mnemonic} attribute is a string type attribute holding the | |
10055 | instruction mnemonic for an insn alternative. The attribute values | |
10056 | will automatically be generated by the machine description parser if | |
10057 | there is an attribute definition in the md file: | |
10058 | ||
10059 | @smallexample | |
10060 | (define_attr "mnemonic" "unknown" (const_string "unknown")) | |
10061 | @end smallexample | |
10062 | ||
10063 | The default value can be freely chosen as long as it does not collide | |
10064 | with any of the instruction mnemonics. This value will be used | |
10065 | whenever the machine description parser is not able to determine the | |
10066 | mnemonic string. This might be the case for output templates | |
10067 | containing more than a single instruction as in | |
10068 | @code{"mvcle\t%0,%1,0\;jo\t.-4"}. | |
10069 | ||
10070 | The @code{mnemonic} attribute set is not generated automatically if the | |
10071 | instruction string is generated via C code. | |
10072 | ||
10073 | An existing @code{mnemonic} attribute set in an insn definition will not | |
10074 | be overriden by the md file parser. That way it is possible to | |
10075 | manually set the instruction mnemonics for the cases where the md file | |
10076 | parser fails to determine it automatically. | |
10077 | ||
10078 | The @code{mnemonic} attribute is useful for dealing with instruction | |
10079 | specific properties in the pipeline description without defining | |
10080 | additional insn attributes. | |
10081 | ||
10082 | @smallexample | |
10083 | (define_attr "ooo_expanded" "" | |
10084 | (cond [(eq_attr "mnemonic" "dlr,dsgr,d,dsgf,stam,dsgfr,dlgr") | |
10085 | (const_int 1)] | |
10086 | (const_int 0))) | |
10087 | @end smallexample | |
10088 | ||
a5249a21 HPN |
10089 | @end ifset |
10090 | @ifset INTERNALS | |
03dda8e3 RK |
10091 | @node Delay Slots |
10092 | @subsection Delay Slot Scheduling | |
10093 | @cindex delay slots, defining | |
10094 | ||
10095 | The insn attribute mechanism can be used to specify the requirements for | |
10096 | delay slots, if any, on a target machine. An instruction is said to | |
10097 | require a @dfn{delay slot} if some instructions that are physically | |
10098 | after the instruction are executed as if they were located before it. | |
10099 | Classic examples are branch and call instructions, which often execute | |
10100 | the following instruction before the branch or call is performed. | |
10101 | ||
10102 | On some machines, conditional branch instructions can optionally | |
10103 | @dfn{annul} instructions in the delay slot. This means that the | |
10104 | instruction will not be executed for certain branch outcomes. Both | |
10105 | instructions that annul if the branch is true and instructions that | |
10106 | annul if the branch is false are supported. | |
10107 | ||
10108 | Delay slot scheduling differs from instruction scheduling in that | |
10109 | determining whether an instruction needs a delay slot is dependent only | |
10110 | on the type of instruction being generated, not on data flow between the | |
10111 | instructions. See the next section for a discussion of data-dependent | |
10112 | instruction scheduling. | |
10113 | ||
10114 | @findex define_delay | |
10115 | The requirement of an insn needing one or more delay slots is indicated | |
10116 | via the @code{define_delay} expression. It has the following form: | |
10117 | ||
10118 | @smallexample | |
10119 | (define_delay @var{test} | |
10120 | [@var{delay-1} @var{annul-true-1} @var{annul-false-1} | |
10121 | @var{delay-2} @var{annul-true-2} @var{annul-false-2} | |
10122 | @dots{}]) | |
10123 | @end smallexample | |
10124 | ||
10125 | @var{test} is an attribute test that indicates whether this | |
10126 | @code{define_delay} applies to a particular insn. If so, the number of | |
10127 | required delay slots is determined by the length of the vector specified | |
10128 | as the second argument. An insn placed in delay slot @var{n} must | |
10129 | satisfy attribute test @var{delay-n}. @var{annul-true-n} is an | |
10130 | attribute test that specifies which insns may be annulled if the branch | |
10131 | is true. Similarly, @var{annul-false-n} specifies which insns in the | |
10132 | delay slot may be annulled if the branch is false. If annulling is not | |
bd819a4a | 10133 | supported for that delay slot, @code{(nil)} should be coded. |
03dda8e3 RK |
10134 | |
10135 | For example, in the common case where branch and call insns require | |
10136 | a single delay slot, which may contain any insn other than a branch or | |
10137 | call, the following would be placed in the @file{md} file: | |
10138 | ||
10139 | @smallexample | |
10140 | (define_delay (eq_attr "type" "branch,call") | |
10141 | [(eq_attr "type" "!branch,call") (nil) (nil)]) | |
10142 | @end smallexample | |
10143 | ||
10144 | Multiple @code{define_delay} expressions may be specified. In this | |
10145 | case, each such expression specifies different delay slot requirements | |
10146 | and there must be no insn for which tests in two @code{define_delay} | |
10147 | expressions are both true. | |
10148 | ||
10149 | For example, if we have a machine that requires one delay slot for branches | |
10150 | but two for calls, no delay slot can contain a branch or call insn, | |
10151 | and any valid insn in the delay slot for the branch can be annulled if the | |
10152 | branch is true, we might represent this as follows: | |
10153 | ||
10154 | @smallexample | |
10155 | (define_delay (eq_attr "type" "branch") | |
10156 | [(eq_attr "type" "!branch,call") | |
10157 | (eq_attr "type" "!branch,call") | |
10158 | (nil)]) | |
10159 | ||
10160 | (define_delay (eq_attr "type" "call") | |
10161 | [(eq_attr "type" "!branch,call") (nil) (nil) | |
10162 | (eq_attr "type" "!branch,call") (nil) (nil)]) | |
10163 | @end smallexample | |
10164 | @c the above is *still* too long. --mew 4feb93 | |
10165 | ||
a5249a21 HPN |
10166 | @end ifset |
10167 | @ifset INTERNALS | |
fae15c93 VM |
10168 | @node Processor pipeline description |
10169 | @subsection Specifying processor pipeline description | |
10170 | @cindex processor pipeline description | |
10171 | @cindex processor functional units | |
10172 | @cindex instruction latency time | |
10173 | @cindex interlock delays | |
10174 | @cindex data dependence delays | |
10175 | @cindex reservation delays | |
10176 | @cindex pipeline hazard recognizer | |
10177 | @cindex automaton based pipeline description | |
10178 | @cindex regular expressions | |
10179 | @cindex deterministic finite state automaton | |
10180 | @cindex automaton based scheduler | |
10181 | @cindex RISC | |
10182 | @cindex VLIW | |
10183 | ||
ef261fee | 10184 | To achieve better performance, most modern processors |
fae15c93 VM |
10185 | (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW} |
10186 | processors) have many @dfn{functional units} on which several | |
10187 | instructions can be executed simultaneously. An instruction starts | |
10188 | execution if its issue conditions are satisfied. If not, the | |
ef261fee | 10189 | instruction is stalled until its conditions are satisfied. Such |
fae15c93 | 10190 | @dfn{interlock (pipeline) delay} causes interruption of the fetching |
431ae0bf | 10191 | of successor instructions (or demands nop instructions, e.g.@: for some |
fae15c93 VM |
10192 | MIPS processors). |
10193 | ||
10194 | There are two major kinds of interlock delays in modern processors. | |
10195 | The first one is a data dependence delay determining @dfn{instruction | |
10196 | latency time}. The instruction execution is not started until all | |
10197 | source data have been evaluated by prior instructions (there are more | |
10198 | complex cases when the instruction execution starts even when the data | |
c0478a66 | 10199 | are not available but will be ready in given time after the |
fae15c93 VM |
10200 | instruction execution start). Taking the data dependence delays into |
10201 | account is simple. The data dependence (true, output, and | |
10202 | anti-dependence) delay between two instructions is given by a | |
10203 | constant. In most cases this approach is adequate. The second kind | |
10204 | of interlock delays is a reservation delay. The reservation delay | |
10205 | means that two instructions under execution will be in need of shared | |
431ae0bf | 10206 | processors resources, i.e.@: buses, internal registers, and/or |
fae15c93 VM |
10207 | functional units, which are reserved for some time. Taking this kind |
10208 | of delay into account is complex especially for modern @acronym{RISC} | |
10209 | processors. | |
10210 | ||
10211 | The task of exploiting more processor parallelism is solved by an | |
ef261fee | 10212 | instruction scheduler. For a better solution to this problem, the |
fae15c93 | 10213 | instruction scheduler has to have an adequate description of the |
fa0aee89 PB |
10214 | processor parallelism (or @dfn{pipeline description}). GCC |
10215 | machine descriptions describe processor parallelism and functional | |
10216 | unit reservations for groups of instructions with the aid of | |
10217 | @dfn{regular expressions}. | |
ef261fee R |
10218 | |
10219 | The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to | |
fae15c93 | 10220 | figure out the possibility of the instruction issue by the processor |
ef261fee R |
10221 | on a given simulated processor cycle. The pipeline hazard recognizer is |
10222 | automatically generated from the processor pipeline description. The | |
fa0aee89 PB |
10223 | pipeline hazard recognizer generated from the machine description |
10224 | is based on a deterministic finite state automaton (@acronym{DFA}): | |
10225 | the instruction issue is possible if there is a transition from one | |
10226 | automaton state to another one. This algorithm is very fast, and | |
10227 | furthermore, its speed is not dependent on processor | |
10228 | complexity@footnote{However, the size of the automaton depends on | |
6ccde948 RW |
10229 | processor complexity. To limit this effect, machine descriptions |
10230 | can split orthogonal parts of the machine description among several | |
10231 | automata: but then, since each of these must be stepped independently, | |
10232 | this does cause a small decrease in the algorithm's performance.}. | |
fae15c93 | 10233 | |
fae15c93 | 10234 | @cindex automaton based pipeline description |
fa0aee89 PB |
10235 | The rest of this section describes the directives that constitute |
10236 | an automaton-based processor pipeline description. The order of | |
10237 | these constructions within the machine description file is not | |
10238 | important. | |
fae15c93 VM |
10239 | |
10240 | @findex define_automaton | |
10241 | @cindex pipeline hazard recognizer | |
10242 | The following optional construction describes names of automata | |
10243 | generated and used for the pipeline hazards recognition. Sometimes | |
10244 | the generated finite state automaton used by the pipeline hazard | |
ef261fee | 10245 | recognizer is large. If we use more than one automaton and bind functional |
daf2f129 | 10246 | units to the automata, the total size of the automata is usually |
fae15c93 VM |
10247 | less than the size of the single automaton. If there is no one such |
10248 | construction, only one finite state automaton is generated. | |
10249 | ||
10250 | @smallexample | |
10251 | (define_automaton @var{automata-names}) | |
10252 | @end smallexample | |
10253 | ||
10254 | @var{automata-names} is a string giving names of the automata. The | |
10255 | names are separated by commas. All the automata should have unique names. | |
c62347f0 | 10256 | The automaton name is used in the constructions @code{define_cpu_unit} and |
fae15c93 VM |
10257 | @code{define_query_cpu_unit}. |
10258 | ||
10259 | @findex define_cpu_unit | |
10260 | @cindex processor functional units | |
c62347f0 | 10261 | Each processor functional unit used in the description of instruction |
fae15c93 VM |
10262 | reservations should be described by the following construction. |
10263 | ||
10264 | @smallexample | |
10265 | (define_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
10266 | @end smallexample | |
10267 | ||
10268 | @var{unit-names} is a string giving the names of the functional units | |
10269 | separated by commas. Don't use name @samp{nothing}, it is reserved | |
10270 | for other goals. | |
10271 | ||
ef261fee | 10272 | @var{automaton-name} is a string giving the name of the automaton with |
fae15c93 VM |
10273 | which the unit is bound. The automaton should be described in |
10274 | construction @code{define_automaton}. You should give | |
10275 | @dfn{automaton-name}, if there is a defined automaton. | |
10276 | ||
30028c85 VM |
10277 | The assignment of units to automata are constrained by the uses of the |
10278 | units in insn reservations. The most important constraint is: if a | |
10279 | unit reservation is present on a particular cycle of an alternative | |
10280 | for an insn reservation, then some unit from the same automaton must | |
10281 | be present on the same cycle for the other alternatives of the insn | |
10282 | reservation. The rest of the constraints are mentioned in the | |
10283 | description of the subsequent constructions. | |
10284 | ||
fae15c93 VM |
10285 | @findex define_query_cpu_unit |
10286 | @cindex querying function unit reservations | |
10287 | The following construction describes CPU functional units analogously | |
30028c85 VM |
10288 | to @code{define_cpu_unit}. The reservation of such units can be |
10289 | queried for an automaton state. The instruction scheduler never | |
10290 | queries reservation of functional units for given automaton state. So | |
10291 | as a rule, you don't need this construction. This construction could | |
431ae0bf | 10292 | be used for future code generation goals (e.g.@: to generate |
30028c85 | 10293 | @acronym{VLIW} insn templates). |
fae15c93 VM |
10294 | |
10295 | @smallexample | |
10296 | (define_query_cpu_unit @var{unit-names} [@var{automaton-name}]) | |
10297 | @end smallexample | |
10298 | ||
10299 | @var{unit-names} is a string giving names of the functional units | |
10300 | separated by commas. | |
10301 | ||
ef261fee | 10302 | @var{automaton-name} is a string giving the name of the automaton with |
fae15c93 VM |
10303 | which the unit is bound. |
10304 | ||
10305 | @findex define_insn_reservation | |
10306 | @cindex instruction latency time | |
10307 | @cindex regular expressions | |
10308 | @cindex data bypass | |
ef261fee | 10309 | The following construction is the major one to describe pipeline |
fae15c93 VM |
10310 | characteristics of an instruction. |
10311 | ||
10312 | @smallexample | |
10313 | (define_insn_reservation @var{insn-name} @var{default_latency} | |
10314 | @var{condition} @var{regexp}) | |
10315 | @end smallexample | |
10316 | ||
10317 | @var{default_latency} is a number giving latency time of the | |
10318 | instruction. There is an important difference between the old | |
10319 | description and the automaton based pipeline description. The latency | |
10320 | time is used for all dependencies when we use the old description. In | |
ef261fee R |
10321 | the automaton based pipeline description, the given latency time is only |
10322 | used for true dependencies. The cost of anti-dependencies is always | |
fae15c93 VM |
10323 | zero and the cost of output dependencies is the difference between |
10324 | latency times of the producing and consuming insns (if the difference | |
ef261fee R |
10325 | is negative, the cost is considered to be zero). You can always |
10326 | change the default costs for any description by using the target hook | |
fae15c93 VM |
10327 | @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}). |
10328 | ||
cc6a602b | 10329 | @var{insn-name} is a string giving the internal name of the insn. The |
fae15c93 VM |
10330 | internal names are used in constructions @code{define_bypass} and in |
10331 | the automaton description file generated for debugging. The internal | |
ef261fee | 10332 | name has nothing in common with the names in @code{define_insn}. It is a |
fae15c93 VM |
10333 | good practice to use insn classes described in the processor manual. |
10334 | ||
10335 | @var{condition} defines what RTL insns are described by this | |
10336 | construction. You should remember that you will be in trouble if | |
10337 | @var{condition} for two or more different | |
10338 | @code{define_insn_reservation} constructions is TRUE for an insn. In | |
10339 | this case what reservation will be used for the insn is not defined. | |
10340 | Such cases are not checked during generation of the pipeline hazards | |
10341 | recognizer because in general recognizing that two conditions may have | |
10342 | the same value is quite difficult (especially if the conditions | |
10343 | contain @code{symbol_ref}). It is also not checked during the | |
10344 | pipeline hazard recognizer work because it would slow down the | |
10345 | recognizer considerably. | |
10346 | ||
ef261fee | 10347 | @var{regexp} is a string describing the reservation of the cpu's functional |
fae15c93 VM |
10348 | units by the instruction. The reservations are described by a regular |
10349 | expression according to the following syntax: | |
10350 | ||
10351 | @smallexample | |
10352 | regexp = regexp "," oneof | |
10353 | | oneof | |
10354 | ||
10355 | oneof = oneof "|" allof | |
10356 | | allof | |
10357 | ||
10358 | allof = allof "+" repeat | |
10359 | | repeat | |
daf2f129 | 10360 | |
fae15c93 VM |
10361 | repeat = element "*" number |
10362 | | element | |
10363 | ||
10364 | element = cpu_function_unit_name | |
10365 | | reservation_name | |
10366 | | result_name | |
10367 | | "nothing" | |
10368 | | "(" regexp ")" | |
10369 | @end smallexample | |
10370 | ||
10371 | @itemize @bullet | |
10372 | @item | |
10373 | @samp{,} is used for describing the start of the next cycle in | |
10374 | the reservation. | |
10375 | ||
10376 | @item | |
10377 | @samp{|} is used for describing a reservation described by the first | |
10378 | regular expression @strong{or} a reservation described by the second | |
10379 | regular expression @strong{or} etc. | |
10380 | ||
10381 | @item | |
10382 | @samp{+} is used for describing a reservation described by the first | |
10383 | regular expression @strong{and} a reservation described by the | |
10384 | second regular expression @strong{and} etc. | |
10385 | ||
10386 | @item | |
10387 | @samp{*} is used for convenience and simply means a sequence in which | |
10388 | the regular expression are repeated @var{number} times with cycle | |
10389 | advancing (see @samp{,}). | |
10390 | ||
10391 | @item | |
10392 | @samp{cpu_function_unit_name} denotes reservation of the named | |
10393 | functional unit. | |
10394 | ||
10395 | @item | |
10396 | @samp{reservation_name} --- see description of construction | |
10397 | @samp{define_reservation}. | |
10398 | ||
10399 | @item | |
10400 | @samp{nothing} denotes no unit reservations. | |
10401 | @end itemize | |
10402 | ||
10403 | @findex define_reservation | |
10404 | Sometimes unit reservations for different insns contain common parts. | |
10405 | In such case, you can simplify the pipeline description by describing | |
10406 | the common part by the following construction | |
10407 | ||
10408 | @smallexample | |
10409 | (define_reservation @var{reservation-name} @var{regexp}) | |
10410 | @end smallexample | |
10411 | ||
10412 | @var{reservation-name} is a string giving name of @var{regexp}. | |
10413 | Functional unit names and reservation names are in the same name | |
10414 | space. So the reservation names should be different from the | |
67914693 | 10415 | functional unit names and cannot be the reserved name @samp{nothing}. |
fae15c93 VM |
10416 | |
10417 | @findex define_bypass | |
10418 | @cindex instruction latency time | |
10419 | @cindex data bypass | |
10420 | The following construction is used to describe exceptions in the | |
10421 | latency time for given instruction pair. This is so called bypasses. | |
10422 | ||
10423 | @smallexample | |
10424 | (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names} | |
10425 | [@var{guard}]) | |
10426 | @end smallexample | |
10427 | ||
10428 | @var{number} defines when the result generated by the instructions | |
10429 | given in string @var{out_insn_names} will be ready for the | |
f9bf5a8e RS |
10430 | instructions given in string @var{in_insn_names}. Each of these |
10431 | strings is a comma-separated list of filename-style globs and | |
10432 | they refer to the names of @code{define_insn_reservation}s. | |
10433 | For example: | |
10434 | @smallexample | |
10435 | (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*") | |
10436 | @end smallexample | |
10437 | defines a bypass between instructions that start with | |
10438 | @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with | |
10439 | @samp{cpu1_load_}. | |
fae15c93 | 10440 | |
ef261fee | 10441 | @var{guard} is an optional string giving the name of a C function which |
fae15c93 VM |
10442 | defines an additional guard for the bypass. The function will get the |
10443 | two insns as parameters. If the function returns zero the bypass will | |
10444 | be ignored for this case. The additional guard is necessary to | |
431ae0bf | 10445 | recognize complicated bypasses, e.g.@: when the consumer is only an address |
fae15c93 VM |
10446 | of insn @samp{store} (not a stored value). |
10447 | ||
20a07f44 VM |
10448 | If there are more one bypass with the same output and input insns, the |
10449 | chosen bypass is the first bypass with a guard in description whose | |
10450 | guard function returns nonzero. If there is no such bypass, then | |
10451 | bypass without the guard function is chosen. | |
10452 | ||
fae15c93 VM |
10453 | @findex exclusion_set |
10454 | @findex presence_set | |
30028c85 | 10455 | @findex final_presence_set |
fae15c93 | 10456 | @findex absence_set |
30028c85 | 10457 | @findex final_absence_set |
fae15c93 VM |
10458 | @cindex VLIW |
10459 | @cindex RISC | |
cc6a602b BE |
10460 | The following five constructions are usually used to describe |
10461 | @acronym{VLIW} processors, or more precisely, to describe a placement | |
10462 | of small instructions into @acronym{VLIW} instruction slots. They | |
10463 | can be used for @acronym{RISC} processors, too. | |
fae15c93 VM |
10464 | |
10465 | @smallexample | |
10466 | (exclusion_set @var{unit-names} @var{unit-names}) | |
30028c85 VM |
10467 | (presence_set @var{unit-names} @var{patterns}) |
10468 | (final_presence_set @var{unit-names} @var{patterns}) | |
10469 | (absence_set @var{unit-names} @var{patterns}) | |
10470 | (final_absence_set @var{unit-names} @var{patterns}) | |
fae15c93 VM |
10471 | @end smallexample |
10472 | ||
10473 | @var{unit-names} is a string giving names of functional units | |
10474 | separated by commas. | |
10475 | ||
30028c85 | 10476 | @var{patterns} is a string giving patterns of functional units |
0bdcd332 | 10477 | separated by comma. Currently pattern is one unit or units |
30028c85 VM |
10478 | separated by white-spaces. |
10479 | ||
fae15c93 | 10480 | The first construction (@samp{exclusion_set}) means that each |
67914693 | 10481 | functional unit in the first string cannot be reserved simultaneously |
fae15c93 VM |
10482 | with a unit whose name is in the second string and vice versa. For |
10483 | example, the construction is useful for describing processors | |
431ae0bf | 10484 | (e.g.@: some SPARC processors) with a fully pipelined floating point |
fae15c93 VM |
10485 | functional unit which can execute simultaneously only single floating |
10486 | point insns or only double floating point insns. | |
10487 | ||
10488 | The second construction (@samp{presence_set}) means that each | |
67914693 | 10489 | functional unit in the first string cannot be reserved unless at |
30028c85 VM |
10490 | least one of pattern of units whose names are in the second string is |
10491 | reserved. This is an asymmetric relation. For example, it is useful | |
10492 | for description that @acronym{VLIW} @samp{slot1} is reserved after | |
10493 | @samp{slot0} reservation. We could describe it by the following | |
10494 | construction | |
10495 | ||
10496 | @smallexample | |
10497 | (presence_set "slot1" "slot0") | |
10498 | @end smallexample | |
10499 | ||
10500 | Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0} | |
10501 | reservation. In this case we could write | |
10502 | ||
10503 | @smallexample | |
10504 | (presence_set "slot1" "slot0 b0") | |
10505 | @end smallexample | |
10506 | ||
10507 | The third construction (@samp{final_presence_set}) is analogous to | |
10508 | @samp{presence_set}. The difference between them is when checking is | |
10509 | done. When an instruction is issued in given automaton state | |
10510 | reflecting all current and planned unit reservations, the automaton | |
10511 | state is changed. The first state is a source state, the second one | |
10512 | is a result state. Checking for @samp{presence_set} is done on the | |
10513 | source state reservation, checking for @samp{final_presence_set} is | |
10514 | done on the result reservation. This construction is useful to | |
10515 | describe a reservation which is actually two subsequent reservations. | |
10516 | For example, if we use | |
10517 | ||
10518 | @smallexample | |
10519 | (presence_set "slot1" "slot0") | |
10520 | @end smallexample | |
10521 | ||
10522 | the following insn will be never issued (because @samp{slot1} requires | |
10523 | @samp{slot0} which is absent in the source state). | |
10524 | ||
10525 | @smallexample | |
10526 | (define_reservation "insn_and_nop" "slot0 + slot1") | |
10527 | @end smallexample | |
10528 | ||
10529 | but it can be issued if we use analogous @samp{final_presence_set}. | |
10530 | ||
10531 | The forth construction (@samp{absence_set}) means that each functional | |
10532 | unit in the first string can be reserved only if each pattern of units | |
10533 | whose names are in the second string is not reserved. This is an | |
10534 | asymmetric relation (actually @samp{exclusion_set} is analogous to | |
ff2ce160 | 10535 | this one but it is symmetric). For example it might be useful in a |
a71b1c58 NC |
10536 | @acronym{VLIW} description to say that @samp{slot0} cannot be reserved |
10537 | after either @samp{slot1} or @samp{slot2} have been reserved. This | |
10538 | can be described as: | |
30028c85 VM |
10539 | |
10540 | @smallexample | |
a71b1c58 | 10541 | (absence_set "slot0" "slot1, slot2") |
30028c85 VM |
10542 | @end smallexample |
10543 | ||
67914693 | 10544 | Or @samp{slot2} cannot be reserved if @samp{slot0} and unit @samp{b0} |
30028c85 VM |
10545 | are reserved or @samp{slot1} and unit @samp{b1} are reserved. In |
10546 | this case we could write | |
10547 | ||
10548 | @smallexample | |
10549 | (absence_set "slot2" "slot0 b0, slot1 b1") | |
10550 | @end smallexample | |
fae15c93 | 10551 | |
ef261fee | 10552 | All functional units mentioned in a set should belong to the same |
fae15c93 VM |
10553 | automaton. |
10554 | ||
30028c85 VM |
10555 | The last construction (@samp{final_absence_set}) is analogous to |
10556 | @samp{absence_set} but checking is done on the result (state) | |
10557 | reservation. See comments for @samp{final_presence_set}. | |
10558 | ||
fae15c93 VM |
10559 | @findex automata_option |
10560 | @cindex deterministic finite state automaton | |
10561 | @cindex nondeterministic finite state automaton | |
10562 | @cindex finite state automaton minimization | |
10563 | You can control the generator of the pipeline hazard recognizer with | |
10564 | the following construction. | |
10565 | ||
10566 | @smallexample | |
10567 | (automata_option @var{options}) | |
10568 | @end smallexample | |
10569 | ||
10570 | @var{options} is a string giving options which affect the generated | |
10571 | code. Currently there are the following options: | |
10572 | ||
10573 | @itemize @bullet | |
10574 | @item | |
10575 | @dfn{no-minimization} makes no minimization of the automaton. This is | |
30028c85 VM |
10576 | only worth to do when we are debugging the description and need to |
10577 | look more accurately at reservations of states. | |
fae15c93 VM |
10578 | |
10579 | @item | |
df1133a6 BE |
10580 | @dfn{time} means printing time statistics about the generation of |
10581 | automata. | |
10582 | ||
10583 | @item | |
10584 | @dfn{stats} means printing statistics about the generated automata | |
10585 | such as the number of DFA states, NDFA states and arcs. | |
e3c8eb86 VM |
10586 | |
10587 | @item | |
10588 | @dfn{v} means a generation of the file describing the result automata. | |
10589 | The file has suffix @samp{.dfa} and can be used for the description | |
10590 | verification and debugging. | |
10591 | ||
10592 | @item | |
10593 | @dfn{w} means a generation of warning instead of error for | |
10594 | non-critical errors. | |
fae15c93 | 10595 | |
e12da141 BS |
10596 | @item |
10597 | @dfn{no-comb-vect} prevents the automaton generator from generating | |
10598 | two data structures and comparing them for space efficiency. Using | |
10599 | a comb vector to represent transitions may be better, but it can be | |
10600 | very expensive to construct. This option is useful if the build | |
10601 | process spends an unacceptably long time in genautomata. | |
10602 | ||
fae15c93 VM |
10603 | @item |
10604 | @dfn{ndfa} makes nondeterministic finite state automata. This affects | |
10605 | the treatment of operator @samp{|} in the regular expressions. The | |
10606 | usual treatment of the operator is to try the first alternative and, | |
10607 | if the reservation is not possible, the second alternative. The | |
10608 | nondeterministic treatment means trying all alternatives, some of them | |
96ddf8ef | 10609 | may be rejected by reservations in the subsequent insns. |
dfa849f3 | 10610 | |
1e6a9047 | 10611 | @item |
9c582551 | 10612 | @dfn{collapse-ndfa} modifies the behavior of the generator when |
1e6a9047 BS |
10613 | producing an automaton. An additional state transition to collapse a |
10614 | nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA} | |
10615 | state is generated. It can be triggered by passing @code{const0_rtx} to | |
10616 | state_transition. In such an automaton, cycle advance transitions are | |
10617 | available only for these collapsed states. This option is useful for | |
10618 | ports that want to use the @code{ndfa} option, but also want to use | |
10619 | @code{define_query_cpu_unit} to assign units to insns issued in a cycle. | |
10620 | ||
dfa849f3 VM |
10621 | @item |
10622 | @dfn{progress} means output of a progress bar showing how many states | |
10623 | were generated so far for automaton being processed. This is useful | |
10624 | during debugging a @acronym{DFA} description. If you see too many | |
10625 | generated states, you could interrupt the generator of the pipeline | |
10626 | hazard recognizer and try to figure out a reason for generation of the | |
10627 | huge automaton. | |
fae15c93 VM |
10628 | @end itemize |
10629 | ||
10630 | As an example, consider a superscalar @acronym{RISC} machine which can | |
10631 | issue three insns (two integer insns and one floating point insn) on | |
10632 | the cycle but can finish only two insns. To describe this, we define | |
10633 | the following functional units. | |
10634 | ||
10635 | @smallexample | |
10636 | (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline") | |
ef261fee | 10637 | (define_cpu_unit "port0, port1") |
fae15c93 VM |
10638 | @end smallexample |
10639 | ||
10640 | All simple integer insns can be executed in any integer pipeline and | |
10641 | their result is ready in two cycles. The simple integer insns are | |
10642 | issued into the first pipeline unless it is reserved, otherwise they | |
10643 | are issued into the second pipeline. Integer division and | |
10644 | multiplication insns can be executed only in the second integer | |
793e17f9 | 10645 | pipeline and their results are ready correspondingly in 9 and 4 |
431ae0bf | 10646 | cycles. The integer division is not pipelined, i.e.@: the subsequent |
67914693 | 10647 | integer division insn cannot be issued until the current division |
fae15c93 | 10648 | insn finished. Floating point insns are fully pipelined and their |
ef261fee R |
10649 | results are ready in 3 cycles. Where the result of a floating point |
10650 | insn is used by an integer insn, an additional delay of one cycle is | |
10651 | incurred. To describe all of this we could specify | |
fae15c93 VM |
10652 | |
10653 | @smallexample | |
10654 | (define_cpu_unit "div") | |
10655 | ||
68e4d4c5 | 10656 | (define_insn_reservation "simple" 2 (eq_attr "type" "int") |
ef261fee | 10657 | "(i0_pipeline | i1_pipeline), (port0 | port1)") |
fae15c93 | 10658 | |
68e4d4c5 | 10659 | (define_insn_reservation "mult" 4 (eq_attr "type" "mult") |
ef261fee | 10660 | "i1_pipeline, nothing*2, (port0 | port1)") |
fae15c93 | 10661 | |
793e17f9 | 10662 | (define_insn_reservation "div" 9 (eq_attr "type" "div") |
ef261fee | 10663 | "i1_pipeline, div*7, div + (port0 | port1)") |
fae15c93 | 10664 | |
68e4d4c5 | 10665 | (define_insn_reservation "float" 3 (eq_attr "type" "float") |
ef261fee | 10666 | "f_pipeline, nothing, (port0 | port1)) |
fae15c93 | 10667 | |
ef261fee | 10668 | (define_bypass 4 "float" "simple,mult,div") |
fae15c93 VM |
10669 | @end smallexample |
10670 | ||
10671 | To simplify the description we could describe the following reservation | |
10672 | ||
10673 | @smallexample | |
10674 | (define_reservation "finish" "port0|port1") | |
10675 | @end smallexample | |
10676 | ||
10677 | and use it in all @code{define_insn_reservation} as in the following | |
10678 | construction | |
10679 | ||
10680 | @smallexample | |
68e4d4c5 | 10681 | (define_insn_reservation "simple" 2 (eq_attr "type" "int") |
fae15c93 VM |
10682 | "(i0_pipeline | i1_pipeline), finish") |
10683 | @end smallexample | |
10684 | ||
10685 | ||
a5249a21 HPN |
10686 | @end ifset |
10687 | @ifset INTERNALS | |
3262c1f5 RH |
10688 | @node Conditional Execution |
10689 | @section Conditional Execution | |
10690 | @cindex conditional execution | |
10691 | @cindex predication | |
10692 | ||
10693 | A number of architectures provide for some form of conditional | |
10694 | execution, or predication. The hallmark of this feature is the | |
10695 | ability to nullify most of the instructions in the instruction set. | |
10696 | When the instruction set is large and not entirely symmetric, it | |
10697 | can be quite tedious to describe these forms directly in the | |
10698 | @file{.md} file. An alternative is the @code{define_cond_exec} template. | |
10699 | ||
10700 | @findex define_cond_exec | |
10701 | @smallexample | |
10702 | (define_cond_exec | |
10703 | [@var{predicate-pattern}] | |
10704 | "@var{condition}" | |
aadaf24e KT |
10705 | "@var{output-template}" |
10706 | "@var{optional-insn-attribues}") | |
3262c1f5 RH |
10707 | @end smallexample |
10708 | ||
10709 | @var{predicate-pattern} is the condition that must be true for the | |
10710 | insn to be executed at runtime and should match a relational operator. | |
10711 | One can use @code{match_operator} to match several relational operators | |
10712 | at once. Any @code{match_operand} operands must have no more than one | |
10713 | alternative. | |
10714 | ||
10715 | @var{condition} is a C expression that must be true for the generated | |
10716 | pattern to match. | |
10717 | ||
10718 | @findex current_insn_predicate | |
630d3d5a | 10719 | @var{output-template} is a string similar to the @code{define_insn} |
3262c1f5 RH |
10720 | output template (@pxref{Output Template}), except that the @samp{*} |
10721 | and @samp{@@} special cases do not apply. This is only useful if the | |
10722 | assembly text for the predicate is a simple prefix to the main insn. | |
10723 | In order to handle the general case, there is a global variable | |
10724 | @code{current_insn_predicate} that will contain the entire predicate | |
10725 | if the current insn is predicated, and will otherwise be @code{NULL}. | |
10726 | ||
aadaf24e KT |
10727 | @var{optional-insn-attributes} is an optional vector of attributes that gets |
10728 | appended to the insn attributes of the produced cond_exec rtx. It can | |
10729 | be used to add some distinguishing attribute to cond_exec rtxs produced | |
10730 | that way. An example usage would be to use this attribute in conjunction | |
10731 | with attributes on the main pattern to disable particular alternatives under | |
10732 | certain conditions. | |
10733 | ||
ebb48a4d JM |
10734 | When @code{define_cond_exec} is used, an implicit reference to |
10735 | the @code{predicable} instruction attribute is made. | |
0bddee8e BS |
10736 | @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have |
10737 | exactly two elements in its @var{list-of-values}), with the possible | |
10738 | values being @code{no} and @code{yes}. The default and all uses in | |
10739 | the insns must be a simple constant, not a complex expressions. It | |
10740 | may, however, depend on the alternative, by using a comma-separated | |
10741 | list of values. If that is the case, the port should also define an | |
10742 | @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which | |
10743 | should also allow only @code{no} and @code{yes} as its values. | |
3262c1f5 | 10744 | |
ebb48a4d | 10745 | For each @code{define_insn} for which the @code{predicable} |
3262c1f5 RH |
10746 | attribute is true, a new @code{define_insn} pattern will be |
10747 | generated that matches a predicated version of the instruction. | |
10748 | For example, | |
10749 | ||
10750 | @smallexample | |
10751 | (define_insn "addsi" | |
10752 | [(set (match_operand:SI 0 "register_operand" "r") | |
10753 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
10754 | (match_operand:SI 2 "register_operand" "r")))] | |
10755 | "@var{test1}" | |
10756 | "add %2,%1,%0") | |
10757 | ||
10758 | (define_cond_exec | |
10759 | [(ne (match_operand:CC 0 "register_operand" "c") | |
10760 | (const_int 0))] | |
10761 | "@var{test2}" | |
10762 | "(%0)") | |
10763 | @end smallexample | |
10764 | ||
10765 | @noindent | |
10766 | generates a new pattern | |
10767 | ||
10768 | @smallexample | |
10769 | (define_insn "" | |
10770 | [(cond_exec | |
10771 | (ne (match_operand:CC 3 "register_operand" "c") (const_int 0)) | |
10772 | (set (match_operand:SI 0 "register_operand" "r") | |
10773 | (plus:SI (match_operand:SI 1 "register_operand" "r") | |
10774 | (match_operand:SI 2 "register_operand" "r"))))] | |
10775 | "(@var{test2}) && (@var{test1})" | |
10776 | "(%3) add %2,%1,%0") | |
10777 | @end smallexample | |
c25c12b8 | 10778 | |
a5249a21 | 10779 | @end ifset |
477c104e MK |
10780 | @ifset INTERNALS |
10781 | @node Define Subst | |
10782 | @section RTL Templates Transformations | |
10783 | @cindex define_subst | |
10784 | ||
10785 | For some hardware architectures there are common cases when the RTL | |
10786 | templates for the instructions can be derived from the other RTL | |
10787 | templates using simple transformations. E.g., @file{i386.md} contains | |
10788 | an RTL template for the ordinary @code{sub} instruction--- | |
10789 | @code{*subsi_1}, and for the @code{sub} instruction with subsequent | |
10790 | zero-extension---@code{*subsi_1_zext}. Such cases can be easily | |
10791 | implemented by a single meta-template capable of generating a modified | |
10792 | case based on the initial one: | |
10793 | ||
10794 | @findex define_subst | |
10795 | @smallexample | |
10796 | (define_subst "@var{name}" | |
10797 | [@var{input-template}] | |
10798 | "@var{condition}" | |
10799 | [@var{output-template}]) | |
10800 | @end smallexample | |
10801 | @var{input-template} is a pattern describing the source RTL template, | |
10802 | which will be transformed. | |
10803 | ||
10804 | @var{condition} is a C expression that is conjunct with the condition | |
10805 | from the input-template to generate a condition to be used in the | |
10806 | output-template. | |
10807 | ||
10808 | @var{output-template} is a pattern that will be used in the resulting | |
10809 | template. | |
10810 | ||
10811 | @code{define_subst} mechanism is tightly coupled with the notion of the | |
bdb6985c | 10812 | subst attribute (@pxref{Subst Iterators}). The use of |
477c104e MK |
10813 | @code{define_subst} is triggered by a reference to a subst attribute in |
10814 | the transforming RTL template. This reference initiates duplication of | |
10815 | the source RTL template and substitution of the attributes with their | |
10816 | values. The source RTL template is left unchanged, while the copy is | |
10817 | transformed by @code{define_subst}. This transformation can fail in the | |
10818 | case when the source RTL template is not matched against the | |
10819 | input-template of the @code{define_subst}. In such case the copy is | |
10820 | deleted. | |
10821 | ||
10822 | @code{define_subst} can be used only in @code{define_insn} and | |
630ba2fd | 10823 | @code{define_expand}, it cannot be used in other expressions (e.g.@: in |
477c104e MK |
10824 | @code{define_insn_and_split}). |
10825 | ||
10826 | @menu | |
10827 | * Define Subst Example:: Example of @code{define_subst} work. | |
10828 | * Define Subst Pattern Matching:: Process of template comparison. | |
10829 | * Define Subst Output Template:: Generation of output template. | |
10830 | @end menu | |
10831 | ||
10832 | @node Define Subst Example | |
10833 | @subsection @code{define_subst} Example | |
10834 | @cindex define_subst | |
10835 | ||
10836 | To illustrate how @code{define_subst} works, let us examine a simple | |
10837 | template transformation. | |
10838 | ||
10839 | Suppose there are two kinds of instructions: one that touches flags and | |
10840 | the other that does not. The instructions of the second type could be | |
10841 | generated with the following @code{define_subst}: | |
10842 | ||
10843 | @smallexample | |
10844 | (define_subst "add_clobber_subst" | |
10845 | [(set (match_operand:SI 0 "" "") | |
10846 | (match_operand:SI 1 "" ""))] | |
10847 | "" | |
10848 | [(set (match_dup 0) | |
10849 | (match_dup 1)) | |
339ab27a | 10850 | (clobber (reg:CC FLAGS_REG))]) |
477c104e MK |
10851 | @end smallexample |
10852 | ||
10853 | This @code{define_subst} can be applied to any RTL pattern containing | |
10854 | @code{set} of mode SI and generates a copy with clobber when it is | |
10855 | applied. | |
10856 | ||
10857 | Assume there is an RTL template for a @code{max} instruction to be used | |
10858 | in @code{define_subst} mentioned above: | |
10859 | ||
10860 | @smallexample | |
10861 | (define_insn "maxsi" | |
10862 | [(set (match_operand:SI 0 "register_operand" "=r") | |
10863 | (max:SI | |
10864 | (match_operand:SI 1 "register_operand" "r") | |
10865 | (match_operand:SI 2 "register_operand" "r")))] | |
10866 | "" | |
10867 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
10868 | [@dots{}]) | |
10869 | @end smallexample | |
10870 | ||
10871 | To mark the RTL template for @code{define_subst} application, | |
10872 | subst-attributes are used. They should be declared in advance: | |
10873 | ||
10874 | @smallexample | |
10875 | (define_subst_attr "add_clobber_name" "add_clobber_subst" "_noclobber" "_clobber") | |
10876 | @end smallexample | |
10877 | ||
10878 | Here @samp{add_clobber_name} is the attribute name, | |
10879 | @samp{add_clobber_subst} is the name of the corresponding | |
10880 | @code{define_subst}, the third argument (@samp{_noclobber}) is the | |
10881 | attribute value that would be substituted into the unchanged version of | |
10882 | the source RTL template, and the last argument (@samp{_clobber}) is the | |
10883 | value that would be substituted into the second, transformed, | |
10884 | version of the RTL template. | |
10885 | ||
10886 | Once the subst-attribute has been defined, it should be used in RTL | |
10887 | templates which need to be processed by the @code{define_subst}. So, | |
10888 | the original RTL template should be changed: | |
10889 | ||
10890 | @smallexample | |
10891 | (define_insn "maxsi<add_clobber_name>" | |
10892 | [(set (match_operand:SI 0 "register_operand" "=r") | |
10893 | (max:SI | |
10894 | (match_operand:SI 1 "register_operand" "r") | |
10895 | (match_operand:SI 2 "register_operand" "r")))] | |
10896 | "" | |
10897 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
10898 | [@dots{}]) | |
10899 | @end smallexample | |
10900 | ||
10901 | The result of the @code{define_subst} usage would look like the following: | |
10902 | ||
10903 | @smallexample | |
10904 | (define_insn "maxsi_noclobber" | |
10905 | [(set (match_operand:SI 0 "register_operand" "=r") | |
10906 | (max:SI | |
10907 | (match_operand:SI 1 "register_operand" "r") | |
10908 | (match_operand:SI 2 "register_operand" "r")))] | |
10909 | "" | |
10910 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
10911 | [@dots{}]) | |
10912 | (define_insn "maxsi_clobber" | |
10913 | [(set (match_operand:SI 0 "register_operand" "=r") | |
10914 | (max:SI | |
10915 | (match_operand:SI 1 "register_operand" "r") | |
10916 | (match_operand:SI 2 "register_operand" "r"))) | |
10917 | (clobber (reg:CC FLAGS_REG))] | |
10918 | "" | |
10919 | "max\t@{%2, %1, %0|%0, %1, %2@}" | |
10920 | [@dots{}]) | |
10921 | @end smallexample | |
10922 | ||
10923 | @node Define Subst Pattern Matching | |
10924 | @subsection Pattern Matching in @code{define_subst} | |
10925 | @cindex define_subst | |
10926 | ||
10927 | All expressions, allowed in @code{define_insn} or @code{define_expand}, | |
10928 | are allowed in the input-template of @code{define_subst}, except | |
10929 | @code{match_par_dup}, @code{match_scratch}, @code{match_parallel}. The | |
10930 | meanings of expressions in the input-template were changed: | |
10931 | ||
10932 | @code{match_operand} matches any expression (possibly, a subtree in | |
10933 | RTL-template), if modes of the @code{match_operand} and this expression | |
10934 | are the same, or mode of the @code{match_operand} is @code{VOIDmode}, or | |
10935 | this expression is @code{match_dup}, @code{match_op_dup}. If the | |
10936 | expression is @code{match_operand} too, and predicate of | |
10937 | @code{match_operand} from the input pattern is not empty, then the | |
10938 | predicates are compared. That can be used for more accurate filtering | |
10939 | of accepted RTL-templates. | |
10940 | ||
10941 | @code{match_operator} matches common operators (like @code{plus}, | |
10942 | @code{minus}), @code{unspec}, @code{unspec_volatile} operators and | |
10943 | @code{match_operator}s from the original pattern if the modes match and | |
10944 | @code{match_operator} from the input pattern has the same number of | |
10945 | operands as the operator from the original pattern. | |
10946 | ||
10947 | @node Define Subst Output Template | |
10948 | @subsection Generation of output template in @code{define_subst} | |
10949 | @cindex define_subst | |
10950 | ||
10951 | If all necessary checks for @code{define_subst} application pass, a new | |
10952 | RTL-pattern, based on the output-template, is created to replace the old | |
10953 | template. Like in input-patterns, meanings of some RTL expressions are | |
10954 | changed when they are used in output-patterns of a @code{define_subst}. | |
10955 | Thus, @code{match_dup} is used for copying the whole expression from the | |
10956 | original pattern, which matched corresponding @code{match_operand} from | |
10957 | the input pattern. | |
10958 | ||
10959 | @code{match_dup N} is used in the output template to be replaced with | |
10960 | the expression from the original pattern, which matched | |
10961 | @code{match_operand N} from the input pattern. As a consequence, | |
10962 | @code{match_dup} cannot be used to point to @code{match_operand}s from | |
10963 | the output pattern, it should always refer to a @code{match_operand} | |
8245edf3 PK |
10964 | from the input pattern. If a @code{match_dup N} occurs more than once |
10965 | in the output template, its first occurrence is replaced with the | |
10966 | expression from the original pattern, and the subsequent expressions | |
10967 | are replaced with @code{match_dup N}, i.e., a reference to the first | |
10968 | expression. | |
477c104e MK |
10969 | |
10970 | In the output template one can refer to the expressions from the | |
10971 | original pattern and create new ones. For instance, some operands could | |
10972 | be added by means of standard @code{match_operand}. | |
10973 | ||
10974 | After replacing @code{match_dup} with some RTL-subtree from the original | |
10975 | pattern, it could happen that several @code{match_operand}s in the | |
10976 | output pattern have the same indexes. It is unknown, how many and what | |
10977 | indexes would be used in the expression which would replace | |
10978 | @code{match_dup}, so such conflicts in indexes are inevitable. To | |
10979 | overcome this issue, @code{match_operands} and @code{match_operators}, | |
10980 | which were introduced into the output pattern, are renumerated when all | |
10981 | @code{match_dup}s are replaced. | |
10982 | ||
10983 | Number of alternatives in @code{match_operand}s introduced into the | |
10984 | output template @code{M} could differ from the number of alternatives in | |
10985 | the original pattern @code{N}, so in the resultant pattern there would | |
10986 | be @code{N*M} alternatives. Thus, constraints from the original pattern | |
10987 | would be duplicated @code{N} times, constraints from the output pattern | |
10988 | would be duplicated @code{M} times, producing all possible combinations. | |
10989 | @end ifset | |
10990 | ||
a5249a21 | 10991 | @ifset INTERNALS |
c25c12b8 R |
10992 | @node Constant Definitions |
10993 | @section Constant Definitions | |
10994 | @cindex constant definitions | |
10995 | @findex define_constants | |
10996 | ||
10997 | Using literal constants inside instruction patterns reduces legibility and | |
10998 | can be a maintenance problem. | |
10999 | ||
11000 | To overcome this problem, you may use the @code{define_constants} | |
11001 | expression. It contains a vector of name-value pairs. From that | |
11002 | point on, wherever any of the names appears in the MD file, it is as | |
11003 | if the corresponding value had been written instead. You may use | |
11004 | @code{define_constants} multiple times; each appearance adds more | |
11005 | constants to the table. It is an error to redefine a constant with | |
11006 | a different value. | |
11007 | ||
11008 | To come back to the a29k load multiple example, instead of | |
11009 | ||
11010 | @smallexample | |
11011 | (define_insn "" | |
11012 | [(match_parallel 0 "load_multiple_operation" | |
11013 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
11014 | (match_operand:SI 2 "memory_operand" "m")) | |
11015 | (use (reg:SI 179)) | |
11016 | (clobber (reg:SI 179))])] | |
11017 | "" | |
11018 | "loadm 0,0,%1,%2") | |
11019 | @end smallexample | |
11020 | ||
11021 | You could write: | |
11022 | ||
11023 | @smallexample | |
11024 | (define_constants [ | |
11025 | (R_BP 177) | |
11026 | (R_FC 178) | |
11027 | (R_CR 179) | |
11028 | (R_Q 180) | |
11029 | ]) | |
11030 | ||
11031 | (define_insn "" | |
11032 | [(match_parallel 0 "load_multiple_operation" | |
11033 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
11034 | (match_operand:SI 2 "memory_operand" "m")) | |
11035 | (use (reg:SI R_CR)) | |
11036 | (clobber (reg:SI R_CR))])] | |
11037 | "" | |
11038 | "loadm 0,0,%1,%2") | |
11039 | @end smallexample | |
11040 | ||
11041 | The constants that are defined with a define_constant are also output | |
11042 | in the insn-codes.h header file as #defines. | |
24609606 RS |
11043 | |
11044 | @cindex enumerations | |
11045 | @findex define_c_enum | |
11046 | You can also use the machine description file to define enumerations. | |
11047 | Like the constants defined by @code{define_constant}, these enumerations | |
11048 | are visible to both the machine description file and the main C code. | |
11049 | ||
11050 | The syntax is as follows: | |
11051 | ||
11052 | @smallexample | |
11053 | (define_c_enum "@var{name}" [ | |
11054 | @var{value0} | |
11055 | @var{value1} | |
7c922606 YS |
11056 | (@var{value32} 32) |
11057 | @var{value33} | |
24609606 RS |
11058 | @dots{} |
11059 | @var{valuen} | |
11060 | ]) | |
11061 | @end smallexample | |
11062 | ||
11063 | This definition causes the equivalent of the following C code to appear | |
11064 | in @file{insn-constants.h}: | |
11065 | ||
11066 | @smallexample | |
11067 | enum @var{name} @{ | |
11068 | @var{value0} = 0, | |
11069 | @var{value1} = 1, | |
7c922606 YS |
11070 | @var{value32} = 32, |
11071 | @var{value33} = 33, | |
24609606 RS |
11072 | @dots{} |
11073 | @var{valuen} = @var{n} | |
11074 | @}; | |
11075 | #define NUM_@var{cname}_VALUES (@var{n} + 1) | |
11076 | @end smallexample | |
11077 | ||
11078 | where @var{cname} is the capitalized form of @var{name}. | |
11079 | It also makes each @var{valuei} available in the machine description | |
11080 | file, just as if it had been declared with: | |
11081 | ||
11082 | @smallexample | |
11083 | (define_constants [(@var{valuei} @var{i})]) | |
11084 | @end smallexample | |
11085 | ||
11086 | Each @var{valuei} is usually an upper-case identifier and usually | |
11087 | begins with @var{cname}. | |
11088 | ||
11089 | You can split the enumeration definition into as many statements as | |
11090 | you like. The above example is directly equivalent to: | |
11091 | ||
11092 | @smallexample | |
11093 | (define_c_enum "@var{name}" [@var{value0}]) | |
11094 | (define_c_enum "@var{name}" [@var{value1}]) | |
11095 | @dots{} | |
11096 | (define_c_enum "@var{name}" [@var{valuen}]) | |
11097 | @end smallexample | |
11098 | ||
11099 | Splitting the enumeration helps to improve the modularity of each | |
11100 | individual @code{.md} file. For example, if a port defines its | |
11101 | synchronization instructions in a separate @file{sync.md} file, | |
11102 | it is convenient to define all synchronization-specific enumeration | |
11103 | values in @file{sync.md} rather than in the main @file{.md} file. | |
11104 | ||
0fe60a1b RS |
11105 | Some enumeration names have special significance to GCC: |
11106 | ||
11107 | @table @code | |
11108 | @item unspecv | |
11109 | @findex unspec_volatile | |
11110 | If an enumeration called @code{unspecv} is defined, GCC will use it | |
11111 | when printing out @code{unspec_volatile} expressions. For example: | |
11112 | ||
11113 | @smallexample | |
11114 | (define_c_enum "unspecv" [ | |
11115 | UNSPECV_BLOCKAGE | |
11116 | ]) | |
11117 | @end smallexample | |
11118 | ||
11119 | causes GCC to print @samp{(unspec_volatile @dots{} 0)} as: | |
11120 | ||
11121 | @smallexample | |
11122 | (unspec_volatile ... UNSPECV_BLOCKAGE) | |
11123 | @end smallexample | |
11124 | ||
11125 | @item unspec | |
11126 | @findex unspec | |
11127 | If an enumeration called @code{unspec} is defined, GCC will use | |
11128 | it when printing out @code{unspec} expressions. GCC will also use | |
11129 | it when printing out @code{unspec_volatile} expressions unless an | |
11130 | @code{unspecv} enumeration is also defined. You can therefore | |
11131 | decide whether to keep separate enumerations for volatile and | |
11132 | non-volatile expressions or whether to use the same enumeration | |
11133 | for both. | |
11134 | @end table | |
11135 | ||
24609606 | 11136 | @findex define_enum |
8f4fe86c | 11137 | @anchor{define_enum} |
24609606 RS |
11138 | Another way of defining an enumeration is to use @code{define_enum}: |
11139 | ||
11140 | @smallexample | |
11141 | (define_enum "@var{name}" [ | |
11142 | @var{value0} | |
11143 | @var{value1} | |
11144 | @dots{} | |
11145 | @var{valuen} | |
11146 | ]) | |
11147 | @end smallexample | |
11148 | ||
11149 | This directive implies: | |
11150 | ||
11151 | @smallexample | |
11152 | (define_c_enum "@var{name}" [ | |
11153 | @var{cname}_@var{cvalue0} | |
11154 | @var{cname}_@var{cvalue1} | |
11155 | @dots{} | |
11156 | @var{cname}_@var{cvaluen} | |
11157 | ]) | |
11158 | @end smallexample | |
11159 | ||
8f4fe86c | 11160 | @findex define_enum_attr |
24609606 | 11161 | where @var{cvaluei} is the capitalized form of @var{valuei}. |
8f4fe86c RS |
11162 | However, unlike @code{define_c_enum}, the enumerations defined |
11163 | by @code{define_enum} can be used in attribute specifications | |
11164 | (@pxref{define_enum_attr}). | |
b11cc610 | 11165 | @end ifset |
032e8348 | 11166 | @ifset INTERNALS |
3abcb3a7 HPN |
11167 | @node Iterators |
11168 | @section Iterators | |
11169 | @cindex iterators in @file{.md} files | |
032e8348 RS |
11170 | |
11171 | Ports often need to define similar patterns for more than one machine | |
3abcb3a7 | 11172 | mode or for more than one rtx code. GCC provides some simple iterator |
032e8348 RS |
11173 | facilities to make this process easier. |
11174 | ||
11175 | @menu | |
3abcb3a7 HPN |
11176 | * Mode Iterators:: Generating variations of patterns for different modes. |
11177 | * Code Iterators:: Doing the same for codes. | |
57a4717b | 11178 | * Int Iterators:: Doing the same for integers. |
477c104e | 11179 | * Subst Iterators:: Generating variations of patterns for define_subst. |
0016d8d9 | 11180 | * Parameterized Names:: Specifying iterator values in C++ code. |
032e8348 RS |
11181 | @end menu |
11182 | ||
3abcb3a7 HPN |
11183 | @node Mode Iterators |
11184 | @subsection Mode Iterators | |
11185 | @cindex mode iterators in @file{.md} files | |
032e8348 RS |
11186 | |
11187 | Ports often need to define similar patterns for two or more different modes. | |
11188 | For example: | |
11189 | ||
11190 | @itemize @bullet | |
11191 | @item | |
11192 | If a processor has hardware support for both single and double | |
11193 | floating-point arithmetic, the @code{SFmode} patterns tend to be | |
11194 | very similar to the @code{DFmode} ones. | |
11195 | ||
11196 | @item | |
11197 | If a port uses @code{SImode} pointers in one configuration and | |
11198 | @code{DImode} pointers in another, it will usually have very similar | |
11199 | @code{SImode} and @code{DImode} patterns for manipulating pointers. | |
11200 | @end itemize | |
11201 | ||
3abcb3a7 | 11202 | Mode iterators allow several patterns to be instantiated from one |
032e8348 RS |
11203 | @file{.md} file template. They can be used with any type of |
11204 | rtx-based construct, such as a @code{define_insn}, | |
11205 | @code{define_split}, or @code{define_peephole2}. | |
11206 | ||
11207 | @menu | |
3abcb3a7 | 11208 | * Defining Mode Iterators:: Defining a new mode iterator. |
6ccde948 RW |
11209 | * Substitutions:: Combining mode iterators with substitutions |
11210 | * Examples:: Examples | |
032e8348 RS |
11211 | @end menu |
11212 | ||
3abcb3a7 HPN |
11213 | @node Defining Mode Iterators |
11214 | @subsubsection Defining Mode Iterators | |
11215 | @findex define_mode_iterator | |
032e8348 | 11216 | |
3abcb3a7 | 11217 | The syntax for defining a mode iterator is: |
032e8348 RS |
11218 | |
11219 | @smallexample | |
923158be | 11220 | (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")]) |
032e8348 RS |
11221 | @end smallexample |
11222 | ||
11223 | This allows subsequent @file{.md} file constructs to use the mode suffix | |
11224 | @code{:@var{name}}. Every construct that does so will be expanded | |
11225 | @var{n} times, once with every use of @code{:@var{name}} replaced by | |
11226 | @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}}, | |
11227 | and so on. In the expansion for a particular @var{modei}, every | |
11228 | C condition will also require that @var{condi} be true. | |
11229 | ||
11230 | For example: | |
11231 | ||
11232 | @smallexample | |
3abcb3a7 | 11233 | (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) |
032e8348 RS |
11234 | @end smallexample |
11235 | ||
11236 | defines a new mode suffix @code{:P}. Every construct that uses | |
11237 | @code{:P} will be expanded twice, once with every @code{:P} replaced | |
11238 | by @code{:SI} and once with every @code{:P} replaced by @code{:DI}. | |
11239 | The @code{:SI} version will only apply if @code{Pmode == SImode} and | |
11240 | the @code{:DI} version will only apply if @code{Pmode == DImode}. | |
11241 | ||
11242 | As with other @file{.md} conditions, an empty string is treated | |
11243 | as ``always true''. @code{(@var{mode} "")} can also be abbreviated | |
11244 | to @code{@var{mode}}. For example: | |
11245 | ||
11246 | @smallexample | |
3abcb3a7 | 11247 | (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) |
032e8348 RS |
11248 | @end smallexample |
11249 | ||
11250 | means that the @code{:DI} expansion only applies if @code{TARGET_64BIT} | |
11251 | but that the @code{:SI} expansion has no such constraint. | |
11252 | ||
3abcb3a7 HPN |
11253 | Iterators are applied in the order they are defined. This can be |
11254 | significant if two iterators are used in a construct that requires | |
f30990b2 | 11255 | substitutions. @xref{Substitutions}. |
032e8348 | 11256 | |
f30990b2 | 11257 | @node Substitutions |
3abcb3a7 | 11258 | @subsubsection Substitution in Mode Iterators |
032e8348 RS |
11259 | @findex define_mode_attr |
11260 | ||
3abcb3a7 | 11261 | If an @file{.md} file construct uses mode iterators, each version of the |
f30990b2 ILT |
11262 | construct will often need slightly different strings or modes. For |
11263 | example: | |
032e8348 RS |
11264 | |
11265 | @itemize @bullet | |
11266 | @item | |
11267 | When a @code{define_expand} defines several @code{add@var{m}3} patterns | |
11268 | (@pxref{Standard Names}), each expander will need to use the | |
11269 | appropriate mode name for @var{m}. | |
11270 | ||
11271 | @item | |
11272 | When a @code{define_insn} defines several instruction patterns, | |
11273 | each instruction will often use a different assembler mnemonic. | |
f30990b2 ILT |
11274 | |
11275 | @item | |
11276 | When a @code{define_insn} requires operands with different modes, | |
3abcb3a7 | 11277 | using an iterator for one of the operand modes usually requires a specific |
f30990b2 | 11278 | mode for the other operand(s). |
032e8348 RS |
11279 | @end itemize |
11280 | ||
11281 | GCC supports such variations through a system of ``mode attributes''. | |
11282 | There are two standard attributes: @code{mode}, which is the name of | |
11283 | the mode in lower case, and @code{MODE}, which is the same thing in | |
11284 | upper case. You can define other attributes using: | |
11285 | ||
11286 | @smallexample | |
923158be | 11287 | (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")]) |
032e8348 RS |
11288 | @end smallexample |
11289 | ||
11290 | where @var{name} is the name of the attribute and @var{valuei} | |
11291 | is the value associated with @var{modei}. | |
11292 | ||
3abcb3a7 | 11293 | When GCC replaces some @var{:iterator} with @var{:mode}, it will scan |
f30990b2 | 11294 | each string and mode in the pattern for sequences of the form |
3abcb3a7 | 11295 | @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a |
f30990b2 | 11296 | mode attribute. If the attribute is defined for @var{mode}, the whole |
923158be | 11297 | @code{<@dots{}>} sequence will be replaced by the appropriate attribute |
f30990b2 | 11298 | value. |
032e8348 RS |
11299 | |
11300 | For example, suppose an @file{.md} file has: | |
11301 | ||
11302 | @smallexample | |
3abcb3a7 | 11303 | (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) |
032e8348 RS |
11304 | (define_mode_attr load [(SI "lw") (DI "ld")]) |
11305 | @end smallexample | |
11306 | ||
11307 | If one of the patterns that uses @code{:P} contains the string | |
11308 | @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern | |
11309 | will use @code{"lw\t%0,%1"} and the @code{DI} version will use | |
11310 | @code{"ld\t%0,%1"}. | |
11311 | ||
f30990b2 ILT |
11312 | Here is an example of using an attribute for a mode: |
11313 | ||
11314 | @smallexample | |
3abcb3a7 | 11315 | (define_mode_iterator LONG [SI DI]) |
f30990b2 | 11316 | (define_mode_attr SHORT [(SI "HI") (DI "SI")]) |
923158be RW |
11317 | (define_insn @dots{} |
11318 | (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{}) | |
f30990b2 ILT |
11319 | @end smallexample |
11320 | ||
3abcb3a7 HPN |
11321 | The @code{@var{iterator}:} prefix may be omitted, in which case the |
11322 | substitution will be attempted for every iterator expansion. | |
032e8348 RS |
11323 | |
11324 | @node Examples | |
3abcb3a7 | 11325 | @subsubsection Mode Iterator Examples |
032e8348 RS |
11326 | |
11327 | Here is an example from the MIPS port. It defines the following | |
11328 | modes and attributes (among others): | |
11329 | ||
11330 | @smallexample | |
3abcb3a7 | 11331 | (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) |
032e8348 RS |
11332 | (define_mode_attr d [(SI "") (DI "d")]) |
11333 | @end smallexample | |
11334 | ||
11335 | and uses the following template to define both @code{subsi3} | |
11336 | and @code{subdi3}: | |
11337 | ||
11338 | @smallexample | |
11339 | (define_insn "sub<mode>3" | |
11340 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
11341 | (minus:GPR (match_operand:GPR 1 "register_operand" "d") | |
11342 | (match_operand:GPR 2 "register_operand" "d")))] | |
11343 | "" | |
11344 | "<d>subu\t%0,%1,%2" | |
11345 | [(set_attr "type" "arith") | |
11346 | (set_attr "mode" "<MODE>")]) | |
11347 | @end smallexample | |
11348 | ||
11349 | This is exactly equivalent to: | |
11350 | ||
11351 | @smallexample | |
11352 | (define_insn "subsi3" | |
11353 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11354 | (minus:SI (match_operand:SI 1 "register_operand" "d") | |
11355 | (match_operand:SI 2 "register_operand" "d")))] | |
11356 | "" | |
11357 | "subu\t%0,%1,%2" | |
11358 | [(set_attr "type" "arith") | |
11359 | (set_attr "mode" "SI")]) | |
11360 | ||
11361 | (define_insn "subdi3" | |
11362 | [(set (match_operand:DI 0 "register_operand" "=d") | |
11363 | (minus:DI (match_operand:DI 1 "register_operand" "d") | |
11364 | (match_operand:DI 2 "register_operand" "d")))] | |
79b9d839 | 11365 | "TARGET_64BIT" |
032e8348 RS |
11366 | "dsubu\t%0,%1,%2" |
11367 | [(set_attr "type" "arith") | |
11368 | (set_attr "mode" "DI")]) | |
11369 | @end smallexample | |
11370 | ||
3abcb3a7 HPN |
11371 | @node Code Iterators |
11372 | @subsection Code Iterators | |
11373 | @cindex code iterators in @file{.md} files | |
11374 | @findex define_code_iterator | |
032e8348 RS |
11375 | @findex define_code_attr |
11376 | ||
3abcb3a7 | 11377 | Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}. |
032e8348 RS |
11378 | |
11379 | The construct: | |
11380 | ||
11381 | @smallexample | |
923158be | 11382 | (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")]) |
032e8348 RS |
11383 | @end smallexample |
11384 | ||
11385 | defines a pseudo rtx code @var{name} that can be instantiated as | |
11386 | @var{codei} if condition @var{condi} is true. Each @var{codei} | |
11387 | must have the same rtx format. @xref{RTL Classes}. | |
11388 | ||
3abcb3a7 | 11389 | As with mode iterators, each pattern that uses @var{name} will be |
032e8348 RS |
11390 | expanded @var{n} times, once with all uses of @var{name} replaced by |
11391 | @var{code1}, once with all uses replaced by @var{code2}, and so on. | |
3abcb3a7 | 11392 | @xref{Defining Mode Iterators}. |
032e8348 RS |
11393 | |
11394 | It is possible to define attributes for codes as well as for modes. | |
11395 | There are two standard code attributes: @code{code}, the name of the | |
11396 | code in lower case, and @code{CODE}, the name of the code in upper case. | |
11397 | Other attributes are defined using: | |
11398 | ||
11399 | @smallexample | |
923158be | 11400 | (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")]) |
032e8348 RS |
11401 | @end smallexample |
11402 | ||
75df257b RS |
11403 | Instruction patterns can use code attributes as rtx codes, which can be |
11404 | useful if two sets of codes act in tandem. For example, the following | |
11405 | @code{define_insn} defines two patterns, one calculating a signed absolute | |
11406 | difference and another calculating an unsigned absolute difference: | |
11407 | ||
11408 | @smallexample | |
11409 | (define_code_iterator any_max [smax umax]) | |
11410 | (define_code_attr paired_min [(smax "smin") (umax "umin")]) | |
11411 | (define_insn @dots{} | |
11412 | [(set (match_operand:SI 0 @dots{}) | |
11413 | (minus:SI (any_max:SI (match_operand:SI 1 @dots{}) | |
11414 | (match_operand:SI 2 @dots{})) | |
11415 | (<paired_min>:SI (match_dup 1) (match_dup 2))))] | |
11416 | @dots{}) | |
11417 | @end smallexample | |
11418 | ||
11419 | The signed version of the instruction uses @code{smax} and @code{smin} | |
11420 | while the unsigned version uses @code{umax} and @code{umin}. There | |
11421 | are no versions that pair @code{smax} with @code{umin} or @code{umax} | |
11422 | with @code{smin}. | |
11423 | ||
3abcb3a7 | 11424 | Here's an example of code iterators in action, taken from the MIPS port: |
032e8348 RS |
11425 | |
11426 | @smallexample | |
3abcb3a7 HPN |
11427 | (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt |
11428 | eq ne gt ge lt le gtu geu ltu leu]) | |
032e8348 RS |
11429 | |
11430 | (define_expand "b<code>" | |
11431 | [(set (pc) | |
11432 | (if_then_else (any_cond:CC (cc0) | |
11433 | (const_int 0)) | |
11434 | (label_ref (match_operand 0 "")) | |
11435 | (pc)))] | |
11436 | "" | |
11437 | @{ | |
11438 | gen_conditional_branch (operands, <CODE>); | |
11439 | DONE; | |
11440 | @}) | |
11441 | @end smallexample | |
11442 | ||
11443 | This is equivalent to: | |
11444 | ||
11445 | @smallexample | |
11446 | (define_expand "bunordered" | |
11447 | [(set (pc) | |
11448 | (if_then_else (unordered:CC (cc0) | |
11449 | (const_int 0)) | |
11450 | (label_ref (match_operand 0 "")) | |
11451 | (pc)))] | |
11452 | "" | |
11453 | @{ | |
11454 | gen_conditional_branch (operands, UNORDERED); | |
11455 | DONE; | |
11456 | @}) | |
11457 | ||
11458 | (define_expand "bordered" | |
11459 | [(set (pc) | |
11460 | (if_then_else (ordered:CC (cc0) | |
11461 | (const_int 0)) | |
11462 | (label_ref (match_operand 0 "")) | |
11463 | (pc)))] | |
11464 | "" | |
11465 | @{ | |
11466 | gen_conditional_branch (operands, ORDERED); | |
11467 | DONE; | |
11468 | @}) | |
11469 | ||
923158be | 11470 | @dots{} |
032e8348 RS |
11471 | @end smallexample |
11472 | ||
57a4717b TB |
11473 | @node Int Iterators |
11474 | @subsection Int Iterators | |
11475 | @cindex int iterators in @file{.md} files | |
11476 | @findex define_int_iterator | |
11477 | @findex define_int_attr | |
11478 | ||
11479 | Int iterators operate in a similar way to code iterators. @xref{Code Iterators}. | |
11480 | ||
11481 | The construct: | |
11482 | ||
11483 | @smallexample | |
11484 | (define_int_iterator @var{name} [(@var{int1} "@var{cond1}") @dots{} (@var{intn} "@var{condn}")]) | |
11485 | @end smallexample | |
11486 | ||
11487 | defines a pseudo integer constant @var{name} that can be instantiated as | |
da749b98 MR |
11488 | @var{inti} if condition @var{condi} is true. Each @var{int} must have the |
11489 | same rtx format. @xref{RTL Classes}. Int iterators can appear in only | |
11490 | those rtx fields that have 'i', 'n', 'w', or 'p' as the specifier. This | |
11491 | means that each @var{int} has to be a constant defined using define_constant | |
11492 | or define_c_enum. | |
57a4717b TB |
11493 | |
11494 | As with mode and code iterators, each pattern that uses @var{name} will be | |
11495 | expanded @var{n} times, once with all uses of @var{name} replaced by | |
11496 | @var{int1}, once with all uses replaced by @var{int2}, and so on. | |
11497 | @xref{Defining Mode Iterators}. | |
11498 | ||
11499 | It is possible to define attributes for ints as well as for codes and modes. | |
11500 | Attributes are defined using: | |
11501 | ||
11502 | @smallexample | |
11503 | (define_int_attr @var{name} [(@var{int1} "@var{value1}") @dots{} (@var{intn} "@var{valuen}")]) | |
11504 | @end smallexample | |
11505 | ||
11506 | Here's an example of int iterators in action, taken from the ARM port: | |
11507 | ||
11508 | @smallexample | |
11509 | (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG]) | |
11510 | ||
11511 | (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")]) | |
11512 | ||
11513 | (define_insn "neon_vq<absneg><mode>" | |
11514 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
11515 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
11516 | (match_operand:SI 2 "immediate_operand" "i")] | |
11517 | QABSNEG))] | |
11518 | "TARGET_NEON" | |
11519 | "vq<absneg>.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
003bb7f3 | 11520 | [(set_attr "type" "neon_vqneg_vqabs")] |
57a4717b TB |
11521 | ) |
11522 | ||
11523 | @end smallexample | |
11524 | ||
11525 | This is equivalent to: | |
11526 | ||
11527 | @smallexample | |
11528 | (define_insn "neon_vqabs<mode>" | |
11529 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
11530 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
11531 | (match_operand:SI 2 "immediate_operand" "i")] | |
11532 | UNSPEC_VQABS))] | |
11533 | "TARGET_NEON" | |
11534 | "vqabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
003bb7f3 | 11535 | [(set_attr "type" "neon_vqneg_vqabs")] |
57a4717b TB |
11536 | ) |
11537 | ||
11538 | (define_insn "neon_vqneg<mode>" | |
11539 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
11540 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
11541 | (match_operand:SI 2 "immediate_operand" "i")] | |
11542 | UNSPEC_VQNEG))] | |
11543 | "TARGET_NEON" | |
11544 | "vqneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1" | |
003bb7f3 | 11545 | [(set_attr "type" "neon_vqneg_vqabs")] |
57a4717b TB |
11546 | ) |
11547 | ||
11548 | @end smallexample | |
11549 | ||
477c104e MK |
11550 | @node Subst Iterators |
11551 | @subsection Subst Iterators | |
11552 | @cindex subst iterators in @file{.md} files | |
11553 | @findex define_subst | |
11554 | @findex define_subst_attr | |
11555 | ||
11556 | Subst iterators are special type of iterators with the following | |
11557 | restrictions: they could not be declared explicitly, they always have | |
11558 | only two values, and they do not have explicit dedicated name. | |
11559 | Subst-iterators are triggered only when corresponding subst-attribute is | |
11560 | used in RTL-pattern. | |
11561 | ||
11562 | Subst iterators transform templates in the following way: the templates | |
11563 | are duplicated, the subst-attributes in these templates are replaced | |
11564 | with the corresponding values, and a new attribute is implicitly added | |
11565 | to the given @code{define_insn}/@code{define_expand}. The name of the | |
11566 | added attribute matches the name of @code{define_subst}. Such | |
11567 | attributes are declared implicitly, and it is not allowed to have a | |
11568 | @code{define_attr} named as a @code{define_subst}. | |
11569 | ||
11570 | Each subst iterator is linked to a @code{define_subst}. It is declared | |
11571 | implicitly by the first appearance of the corresponding | |
11572 | @code{define_subst_attr}, and it is not allowed to define it explicitly. | |
11573 | ||
11574 | Declarations of subst-attributes have the following syntax: | |
11575 | ||
11576 | @findex define_subst_attr | |
11577 | @smallexample | |
11578 | (define_subst_attr "@var{name}" | |
11579 | "@var{subst-name}" | |
11580 | "@var{no-subst-value}" | |
11581 | "@var{subst-applied-value}") | |
11582 | @end smallexample | |
11583 | ||
11584 | @var{name} is a string with which the given subst-attribute could be | |
11585 | referred to. | |
11586 | ||
11587 | @var{subst-name} shows which @code{define_subst} should be applied to an | |
11588 | RTL-template if the given subst-attribute is present in the | |
11589 | RTL-template. | |
11590 | ||
11591 | @var{no-subst-value} is a value with which subst-attribute would be | |
11592 | replaced in the first copy of the original RTL-template. | |
11593 | ||
11594 | @var{subst-applied-value} is a value with which subst-attribute would be | |
11595 | replaced in the second copy of the original RTL-template. | |
11596 | ||
0016d8d9 RS |
11597 | @node Parameterized Names |
11598 | @subsection Parameterized Names | |
11599 | @cindex @samp{@@} in instruction pattern names | |
11600 | Ports sometimes need to apply iterators using C++ code, in order to | |
11601 | get the code or RTL pattern for a specific instruction. For example, | |
11602 | suppose we have the @samp{neon_vq<absneg><mode>} pattern given above: | |
11603 | ||
11604 | @smallexample | |
11605 | (define_int_iterator QABSNEG [UNSPEC_VQABS UNSPEC_VQNEG]) | |
11606 | ||
11607 | (define_int_attr absneg [(UNSPEC_VQABS "abs") (UNSPEC_VQNEG "neg")]) | |
11608 | ||
11609 | (define_insn "neon_vq<absneg><mode>" | |
11610 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
11611 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
11612 | (match_operand:SI 2 "immediate_operand" "i")] | |
11613 | QABSNEG))] | |
11614 | @dots{} | |
11615 | ) | |
11616 | @end smallexample | |
11617 | ||
11618 | A port might need to generate this pattern for a variable | |
11619 | @samp{QABSNEG} value and a variable @samp{VDQIW} mode. There are two | |
11620 | ways of doing this. The first is to build the rtx for the pattern | |
11621 | directly from C++ code; this is a valid technique and avoids any risk | |
11622 | of combinatorial explosion. The second is to prefix the instruction | |
11623 | name with the special character @samp{@@}, which tells GCC to generate | |
11624 | the four additional functions below. In each case, @var{name} is the | |
11625 | name of the instruction without the leading @samp{@@} character, | |
11626 | without the @samp{<@dots{}>} placeholders, and with any underscore | |
11627 | before a @samp{<@dots{}>} placeholder removed if keeping it would | |
11628 | lead to a double or trailing underscore. | |
11629 | ||
11630 | @table @samp | |
11631 | @item insn_code maybe_code_for_@var{name} (@var{i1}, @var{i2}, @dots{}) | |
11632 | See whether replacing the first @samp{<@dots{}>} placeholder with | |
11633 | iterator value @var{i1}, the second with iterator value @var{i2}, and | |
11634 | so on, gives a valid instruction. Return its code if so, otherwise | |
11635 | return @code{CODE_FOR_nothing}. | |
11636 | ||
11637 | @item insn_code code_for_@var{name} (@var{i1}, @var{i2}, @dots{}) | |
11638 | Same, but abort the compiler if the requested instruction does not exist. | |
11639 | ||
11640 | @item rtx maybe_gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{}) | |
11641 | Check for a valid instruction in the same way as | |
11642 | @code{maybe_code_for_@var{name}}. If the instruction exists, | |
11643 | generate an instance of it using the operand values given by @var{op0}, | |
11644 | @var{op1}, and so on, otherwise return null. | |
11645 | ||
11646 | @item rtx gen_@var{name} (@var{i1}, @var{i2}, @dots{}, @var{op0}, @var{op1}, @dots{}) | |
11647 | Same, but abort the compiler if the requested instruction does not exist, | |
11648 | or if the instruction generator invoked the @code{FAIL} macro. | |
11649 | @end table | |
11650 | ||
11651 | For example, changing the pattern above to: | |
11652 | ||
11653 | @smallexample | |
11654 | (define_insn "@@neon_vq<absneg><mode>" | |
11655 | [(set (match_operand:VDQIW 0 "s_register_operand" "=w") | |
11656 | (unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w") | |
11657 | (match_operand:SI 2 "immediate_operand" "i")] | |
11658 | QABSNEG))] | |
11659 | @dots{} | |
11660 | ) | |
11661 | @end smallexample | |
11662 | ||
11663 | would define the same patterns as before, but in addition would generate | |
11664 | the four functions below: | |
11665 | ||
11666 | @smallexample | |
11667 | insn_code maybe_code_for_neon_vq (int, machine_mode); | |
11668 | insn_code code_for_neon_vq (int, machine_mode); | |
11669 | rtx maybe_gen_neon_vq (int, machine_mode, rtx, rtx, rtx); | |
11670 | rtx gen_neon_vq (int, machine_mode, rtx, rtx, rtx); | |
11671 | @end smallexample | |
11672 | ||
11673 | Calling @samp{code_for_neon_vq (UNSPEC_VQABS, V8QImode)} | |
11674 | would then give @code{CODE_FOR_neon_vqabsv8qi}. | |
11675 | ||
11676 | It is possible to have multiple @samp{@@} patterns with the same | |
11677 | name and same types of iterator. For example: | |
11678 | ||
11679 | @smallexample | |
11680 | (define_insn "@@some_arithmetic_op<mode>" | |
11681 | [(set (match_operand:INTEGER_MODES 0 "register_operand") @dots{})] | |
11682 | @dots{} | |
11683 | ) | |
11684 | ||
11685 | (define_insn "@@some_arithmetic_op<mode>" | |
11686 | [(set (match_operand:FLOAT_MODES 0 "register_operand") @dots{})] | |
11687 | @dots{} | |
11688 | ) | |
11689 | @end smallexample | |
11690 | ||
11691 | would produce a single set of functions that handles both | |
11692 | @code{INTEGER_MODES} and @code{FLOAT_MODES}. | |
11693 | ||
d281492d RS |
11694 | It is also possible for these @samp{@@} patterns to have different |
11695 | numbers of operands from each other. For example, patterns with | |
11696 | a binary rtl code might take three operands (one output and two inputs) | |
11697 | while patterns with a ternary rtl code might take four operands (one | |
11698 | output and three inputs). This combination would produce separate | |
11699 | @samp{maybe_gen_@var{name}} and @samp{gen_@var{name}} functions for | |
11700 | each operand count, but it would still produce a single | |
11701 | @samp{maybe_code_for_@var{name}} and a single @samp{code_for_@var{name}}. | |
11702 | ||
032e8348 | 11703 | @end ifset |