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6207bd2c 1/* Sets (bit vectors) of hard registers, and operations on them.
fbd26352 2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
6207bd2c 3
f12b58b3 4This file is part of GCC
6207bd2c 5
f12b58b3 6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8c4c00c1 8Software Foundation; either version 3, or (at your option) any later
f12b58b3 9version.
6207bd2c 10
f12b58b3 11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
6207bd2c 15
16You should have received a copy of the GNU General Public License
8c4c00c1 17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
6207bd2c 19
2a281353 20#ifndef GCC_HARD_REG_SET_H
48e1416a 21#define GCC_HARD_REG_SET_H
6207bd2c 22
23/* Define the type of a set of hard registers. */
24
c7a2b3e5 25/* HARD_REG_ELT_TYPE is a typedef of the unsigned integral type which
26 will be used for hard reg sets, either alone or in an array.
27
28 If HARD_REG_SET is a macro, its definition is HARD_REG_ELT_TYPE,
29 and it has enough bits to represent all the target machine's hard
30 registers. Otherwise, it is a typedef for a suitably sized array
31 of HARD_REG_ELT_TYPEs. HARD_REG_SET_LONGS is defined as how many.
6207bd2c 32
33 Note that lots of code assumes that the first part of a regset is
34 the same format as a HARD_REG_SET. To help make sure this is true,
3f28a032 35 we only try the widest fast integer mode (HOST_WIDEST_FAST_INT)
36 instead of all the smaller types. This approach loses only if
91275768 37 there are very few registers and then only in the few cases where
3f28a032 38 we have an array of HARD_REG_SETs, so it needn't be as complex as
39 it used to be. */
c7a2b3e5 40
3f28a032 41typedef unsigned HOST_WIDEST_FAST_INT HARD_REG_ELT_TYPE;
6207bd2c 42
3f28a032 43#if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDEST_FAST_INT
c7a2b3e5 44
45#define HARD_REG_SET HARD_REG_ELT_TYPE
6207bd2c 46
47#else
48
49#define HARD_REG_SET_LONGS \
3f28a032 50 ((FIRST_PSEUDO_REGISTER + HOST_BITS_PER_WIDEST_FAST_INT - 1) \
51 / HOST_BITS_PER_WIDEST_FAST_INT)
c7a2b3e5 52typedef HARD_REG_ELT_TYPE HARD_REG_SET[HARD_REG_SET_LONGS];
6207bd2c 53
54#endif
55
2e851bb8 56/* HARD_REG_SET wrapped into a structure, to make it possible to
57 use HARD_REG_SET even in APIs that should not include
58 hard-reg-set.h. */
59struct hard_reg_set_container
60{
61 HARD_REG_SET set;
62};
63
c7a2b3e5 64/* HARD_CONST is used to cast a constant to the appropriate type
65 for use with a HARD_REG_SET. */
6207bd2c 66
c7a2b3e5 67#define HARD_CONST(X) ((HARD_REG_ELT_TYPE) (X))
6207bd2c 68
69/* Define macros SET_HARD_REG_BIT, CLEAR_HARD_REG_BIT and TEST_HARD_REG_BIT
70 to set, clear or test one bit in a hard reg set of type HARD_REG_SET.
71 All three take two arguments: the set and the register number.
72
73 In the case where sets are arrays of longs, the first argument
74 is actually a pointer to a long.
75
76 Define two macros for initializing a set:
77 CLEAR_HARD_REG_SET and SET_HARD_REG_SET.
78 These take just one argument.
79
80 Also define macros for copying hard reg sets:
81 COPY_HARD_REG_SET and COMPL_HARD_REG_SET.
82 These take two arguments TO and FROM; they read from FROM
83 and store into TO. COMPL_HARD_REG_SET complements each bit.
84
85 Also define macros for combining hard reg sets:
86 IOR_HARD_REG_SET and AND_HARD_REG_SET.
87 These take two arguments TO and FROM; they read from FROM
88 and combine bitwise into TO. Define also two variants
89 IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET
90 which use the complement of the set FROM.
91
ddc556d1 92 Also define:
93
94 hard_reg_set_subset_p (X, Y), which returns true if X is a subset of Y.
95 hard_reg_set_equal_p (X, Y), which returns true if X and Y are equal.
96 hard_reg_set_intersect_p (X, Y), which returns true if X and Y intersect.
97 hard_reg_set_empty_p (X), which returns true if X is empty. */
6207bd2c 98
e1ab7874 99#define UHOST_BITS_PER_WIDE_INT ((unsigned) HOST_BITS_PER_WIDEST_FAST_INT)
100
6207bd2c 101#ifdef HARD_REG_SET
102
103#define SET_HARD_REG_BIT(SET, BIT) \
104 ((SET) |= HARD_CONST (1) << (BIT))
105#define CLEAR_HARD_REG_BIT(SET, BIT) \
106 ((SET) &= ~(HARD_CONST (1) << (BIT)))
107#define TEST_HARD_REG_BIT(SET, BIT) \
42339e9b 108 (!!((SET) & (HARD_CONST (1) << (BIT))))
6207bd2c 109
110#define CLEAR_HARD_REG_SET(TO) ((TO) = HARD_CONST (0))
c7a2b3e5 111#define SET_HARD_REG_SET(TO) ((TO) = ~ HARD_CONST (0))
6207bd2c 112
113#define COPY_HARD_REG_SET(TO, FROM) ((TO) = (FROM))
114#define COMPL_HARD_REG_SET(TO, FROM) ((TO) = ~(FROM))
115
116#define IOR_HARD_REG_SET(TO, FROM) ((TO) |= (FROM))
117#define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM))
118#define AND_HARD_REG_SET(TO, FROM) ((TO) &= (FROM))
119#define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM))
120
ddc556d1 121static inline bool
122hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
123{
124 return (x & ~y) == HARD_CONST (0);
125}
126
127static inline bool
128hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
129{
130 return x == y;
131}
132
133static inline bool
134hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
135{
136 return (x & y) != HARD_CONST (0);
137}
138
139static inline bool
140hard_reg_set_empty_p (const HARD_REG_SET x)
141{
142 return x == HARD_CONST (0);
143}
c7a2b3e5 144
6207bd2c 145#else
146
6207bd2c 147#define SET_HARD_REG_BIT(SET, BIT) \
148 ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \
c7a2b3e5 149 |= HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))
6207bd2c 150
151#define CLEAR_HARD_REG_BIT(SET, BIT) \
152 ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \
c7a2b3e5 153 &= ~(HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT)))
6207bd2c 154
155#define TEST_HARD_REG_BIT(SET, BIT) \
42339e9b 156 (!!((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \
157 & (HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))))
6207bd2c 158
3f28a032 159#if FIRST_PSEUDO_REGISTER <= 2*HOST_BITS_PER_WIDEST_FAST_INT
f9bc9bee 160#define CLEAR_HARD_REG_SET(TO) \
19cb6b50 161do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
f9bc9bee 162 scan_tp_[0] = 0; \
163 scan_tp_[1] = 0; } while (0)
164
165#define SET_HARD_REG_SET(TO) \
19cb6b50 166do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
f9bc9bee 167 scan_tp_[0] = -1; \
168 scan_tp_[1] = -1; } while (0)
169
170#define COPY_HARD_REG_SET(TO, FROM) \
4e42e615 171do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
172 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 173 scan_tp_[0] = scan_fp_[0]; \
174 scan_tp_[1] = scan_fp_[1]; } while (0)
175
176#define COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 177do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
178 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 179 scan_tp_[0] = ~ scan_fp_[0]; \
180 scan_tp_[1] = ~ scan_fp_[1]; } while (0)
181
182#define AND_HARD_REG_SET(TO, FROM) \
4e42e615 183do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
184 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 185 scan_tp_[0] &= scan_fp_[0]; \
f9bc9bee 186 scan_tp_[1] &= scan_fp_[1]; } while (0)
187
188#define AND_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 189do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
190 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 191 scan_tp_[0] &= ~ scan_fp_[0]; \
192 scan_tp_[1] &= ~ scan_fp_[1]; } while (0)
193
194#define IOR_HARD_REG_SET(TO, FROM) \
4e42e615 195do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
196 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 197 scan_tp_[0] |= scan_fp_[0]; \
198 scan_tp_[1] |= scan_fp_[1]; } while (0)
199
200#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 201do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
202 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 203 scan_tp_[0] |= ~ scan_fp_[0]; \
204 scan_tp_[1] |= ~ scan_fp_[1]; } while (0)
205
ddc556d1 206static inline bool
207hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
208{
209 return (x[0] & ~y[0]) == 0 && (x[1] & ~y[1]) == 0;
210}
211
212static inline bool
213hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
214{
215 return x[0] == y[0] && x[1] == y[1];
216}
217
218static inline bool
219hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
220{
221 return (x[0] & y[0]) != 0 || (x[1] & y[1]) != 0;
222}
223
224static inline bool
225hard_reg_set_empty_p (const HARD_REG_SET x)
226{
227 return x[0] == 0 && x[1] == 0;
228}
f9bc9bee 229
230#else
6a5b7d12 231#if FIRST_PSEUDO_REGISTER <= 3*HOST_BITS_PER_WIDEST_FAST_INT
f9bc9bee 232#define CLEAR_HARD_REG_SET(TO) \
19cb6b50 233do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
f9bc9bee 234 scan_tp_[0] = 0; \
235 scan_tp_[1] = 0; \
236 scan_tp_[2] = 0; } while (0)
237
238#define SET_HARD_REG_SET(TO) \
19cb6b50 239do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
f9bc9bee 240 scan_tp_[0] = -1; \
241 scan_tp_[1] = -1; \
242 scan_tp_[2] = -1; } while (0)
243
244#define COPY_HARD_REG_SET(TO, FROM) \
4e42e615 245do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
246 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 247 scan_tp_[0] = scan_fp_[0]; \
248 scan_tp_[1] = scan_fp_[1]; \
249 scan_tp_[2] = scan_fp_[2]; } while (0)
250
251#define COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 252do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
253 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 254 scan_tp_[0] = ~ scan_fp_[0]; \
255 scan_tp_[1] = ~ scan_fp_[1]; \
256 scan_tp_[2] = ~ scan_fp_[2]; } while (0)
257
258#define AND_HARD_REG_SET(TO, FROM) \
4e42e615 259do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
260 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 261 scan_tp_[0] &= scan_fp_[0]; \
262 scan_tp_[1] &= scan_fp_[1]; \
f9bc9bee 263 scan_tp_[2] &= scan_fp_[2]; } while (0)
264
265#define AND_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 266do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
267 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 268 scan_tp_[0] &= ~ scan_fp_[0]; \
269 scan_tp_[1] &= ~ scan_fp_[1]; \
270 scan_tp_[2] &= ~ scan_fp_[2]; } while (0)
271
272#define IOR_HARD_REG_SET(TO, FROM) \
4e42e615 273do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
274 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 275 scan_tp_[0] |= scan_fp_[0]; \
276 scan_tp_[1] |= scan_fp_[1]; \
277 scan_tp_[2] |= scan_fp_[2]; } while (0)
278
279#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 280do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
281 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 282 scan_tp_[0] |= ~ scan_fp_[0]; \
283 scan_tp_[1] |= ~ scan_fp_[1]; \
284 scan_tp_[2] |= ~ scan_fp_[2]; } while (0)
285
ddc556d1 286static inline bool
287hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
288{
289 return ((x[0] & ~y[0]) == 0
290 && (x[1] & ~y[1]) == 0
291 && (x[2] & ~y[2]) == 0);
292}
293
294static inline bool
295hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
296{
297 return x[0] == y[0] && x[1] == y[1] && x[2] == y[2];
298}
299
300static inline bool
301hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
302{
303 return ((x[0] & y[0]) != 0
304 || (x[1] & y[1]) != 0
305 || (x[2] & y[2]) != 0);
306}
307
308static inline bool
309hard_reg_set_empty_p (const HARD_REG_SET x)
310{
311 return x[0] == 0 && x[1] == 0 && x[2] == 0;
312}
f9bc9bee 313
314#else
3f28a032 315#if FIRST_PSEUDO_REGISTER <= 4*HOST_BITS_PER_WIDEST_FAST_INT
f9bc9bee 316#define CLEAR_HARD_REG_SET(TO) \
19cb6b50 317do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
f9bc9bee 318 scan_tp_[0] = 0; \
319 scan_tp_[1] = 0; \
320 scan_tp_[2] = 0; \
321 scan_tp_[3] = 0; } while (0)
322
323#define SET_HARD_REG_SET(TO) \
19cb6b50 324do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
f9bc9bee 325 scan_tp_[0] = -1; \
326 scan_tp_[1] = -1; \
327 scan_tp_[2] = -1; \
328 scan_tp_[3] = -1; } while (0)
329
330#define COPY_HARD_REG_SET(TO, FROM) \
4e42e615 331do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
332 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 333 scan_tp_[0] = scan_fp_[0]; \
334 scan_tp_[1] = scan_fp_[1]; \
335 scan_tp_[2] = scan_fp_[2]; \
336 scan_tp_[3] = scan_fp_[3]; } while (0)
337
338#define COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 339do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
340 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 341 scan_tp_[0] = ~ scan_fp_[0]; \
342 scan_tp_[1] = ~ scan_fp_[1]; \
343 scan_tp_[2] = ~ scan_fp_[2]; \
344 scan_tp_[3] = ~ scan_fp_[3]; } while (0)
345
346#define AND_HARD_REG_SET(TO, FROM) \
4e42e615 347do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
348 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 349 scan_tp_[0] &= scan_fp_[0]; \
350 scan_tp_[1] &= scan_fp_[1]; \
351 scan_tp_[2] &= scan_fp_[2]; \
f9bc9bee 352 scan_tp_[3] &= scan_fp_[3]; } while (0)
353
354#define AND_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 355do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
356 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 357 scan_tp_[0] &= ~ scan_fp_[0]; \
358 scan_tp_[1] &= ~ scan_fp_[1]; \
359 scan_tp_[2] &= ~ scan_fp_[2]; \
360 scan_tp_[3] &= ~ scan_fp_[3]; } while (0)
361
362#define IOR_HARD_REG_SET(TO, FROM) \
4e42e615 363do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
364 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 365 scan_tp_[0] |= scan_fp_[0]; \
366 scan_tp_[1] |= scan_fp_[1]; \
367 scan_tp_[2] |= scan_fp_[2]; \
368 scan_tp_[3] |= scan_fp_[3]; } while (0)
369
370#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 371do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
372 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
f9bc9bee 373 scan_tp_[0] |= ~ scan_fp_[0]; \
374 scan_tp_[1] |= ~ scan_fp_[1]; \
375 scan_tp_[2] |= ~ scan_fp_[2]; \
376 scan_tp_[3] |= ~ scan_fp_[3]; } while (0)
377
ddc556d1 378static inline bool
379hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
380{
381 return ((x[0] & ~y[0]) == 0
382 && (x[1] & ~y[1]) == 0
383 && (x[2] & ~y[2]) == 0
384 && (x[3] & ~y[3]) == 0);
385}
386
387static inline bool
388hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
389{
390 return x[0] == y[0] && x[1] == y[1] && x[2] == y[2] && x[3] == y[3];
391}
392
393static inline bool
394hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
395{
396 return ((x[0] & y[0]) != 0
397 || (x[1] & y[1]) != 0
398 || (x[2] & y[2]) != 0
399 || (x[3] & y[3]) != 0);
400}
401
402static inline bool
403hard_reg_set_empty_p (const HARD_REG_SET x)
404{
405 return x[0] == 0 && x[1] == 0 && x[2] == 0 && x[3] == 0;
406}
f9bc9bee 407
dea7b504 408#else /* FIRST_PSEUDO_REGISTER > 4*HOST_BITS_PER_WIDEST_FAST_INT */
f9bc9bee 409
6207bd2c 410#define CLEAR_HARD_REG_SET(TO) \
19cb6b50 411do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
412 int i; \
6207bd2c 413 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
414 *scan_tp_++ = 0; } while (0)
415
416#define SET_HARD_REG_SET(TO) \
19cb6b50 417do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
418 int i; \
6207bd2c 419 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
420 *scan_tp_++ = -1; } while (0)
421
422#define COPY_HARD_REG_SET(TO, FROM) \
4e42e615 423do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
424 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 425 int i; \
6207bd2c 426 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
427 *scan_tp_++ = *scan_fp_++; } while (0)
428
429#define COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 430do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
431 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 432 int i; \
6207bd2c 433 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
434 *scan_tp_++ = ~ *scan_fp_++; } while (0)
435
436#define AND_HARD_REG_SET(TO, FROM) \
4e42e615 437do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
438 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 439 int i; \
6207bd2c 440 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
441 *scan_tp_++ &= *scan_fp_++; } while (0)
442
443#define AND_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 444do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
445 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 446 int i; \
6207bd2c 447 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
448 *scan_tp_++ &= ~ *scan_fp_++; } while (0)
449
450#define IOR_HARD_REG_SET(TO, FROM) \
4e42e615 451do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
452 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 453 int i; \
6207bd2c 454 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
455 *scan_tp_++ |= *scan_fp_++; } while (0)
456
457#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
4e42e615 458do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
459 const HARD_REG_ELT_TYPE *scan_fp_ = (FROM); \
19cb6b50 460 int i; \
6207bd2c 461 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
462 *scan_tp_++ |= ~ *scan_fp_++; } while (0)
463
ddc556d1 464static inline bool
465hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
466{
467 int i;
468
469 for (i = 0; i < HARD_REG_SET_LONGS; i++)
470 if ((x[i] & ~y[i]) != 0)
471 return false;
472 return true;
473}
474
475static inline bool
476hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
477{
478 int i;
479
480 for (i = 0; i < HARD_REG_SET_LONGS; i++)
481 if (x[i] != y[i])
482 return false;
483 return true;
484}
485
486static inline bool
487hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
488{
489 int i;
490
491 for (i = 0; i < HARD_REG_SET_LONGS; i++)
492 if ((x[i] & y[i]) != 0)
493 return true;
494 return false;
495}
496
497static inline bool
498hard_reg_set_empty_p (const HARD_REG_SET x)
499{
500 int i;
501
502 for (i = 0; i < HARD_REG_SET_LONGS; i++)
503 if (x[i] != 0)
504 return false;
505 return true;
506}
6207bd2c 507
508#endif
f9bc9bee 509#endif
510#endif
511#endif
6207bd2c 512
e1ab7874 513/* Iterator for hard register sets. */
514
b3e7c666 515struct hard_reg_set_iterator
e1ab7874 516{
517 /* Pointer to the current element. */
518 HARD_REG_ELT_TYPE *pelt;
519
520 /* The length of the set. */
521 unsigned short length;
522
523 /* Word within the current element. */
524 unsigned short word_no;
525
526 /* Contents of the actually processed word. When finding next bit
527 it is shifted right, so that the actual bit is always the least
528 significant bit of ACTUAL. */
529 HARD_REG_ELT_TYPE bits;
b3e7c666 530};
e1ab7874 531
532#define HARD_REG_ELT_BITS UHOST_BITS_PER_WIDE_INT
533
48e1416a 534/* The implementation of the iterator functions is fully analogous to
e1ab7874 535 the bitmap iterators. */
536static inline void
48e1416a 537hard_reg_set_iter_init (hard_reg_set_iterator *iter, HARD_REG_SET set,
e1ab7874 538 unsigned min, unsigned *regno)
539{
540#ifdef HARD_REG_SET_LONGS
541 iter->pelt = set;
542 iter->length = HARD_REG_SET_LONGS;
543#else
544 iter->pelt = &set;
545 iter->length = 1;
546#endif
547 iter->word_no = min / HARD_REG_ELT_BITS;
548 if (iter->word_no < iter->length)
549 {
550 iter->bits = iter->pelt[iter->word_no];
551 iter->bits >>= min % HARD_REG_ELT_BITS;
552
553 /* This is required for correct search of the next bit. */
554 min += !iter->bits;
555 }
556 *regno = min;
557}
558
48e1416a 559static inline bool
e1ab7874 560hard_reg_set_iter_set (hard_reg_set_iterator *iter, unsigned *regno)
561{
562 while (1)
563 {
564 /* Return false when we're advanced past the end of the set. */
565 if (iter->word_no >= iter->length)
566 return false;
567
568 if (iter->bits)
569 {
570 /* Find the correct bit and return it. */
571 while (!(iter->bits & 1))
572 {
573 iter->bits >>= 1;
574 *regno += 1;
575 }
576 return (*regno < FIRST_PSEUDO_REGISTER);
577 }
48e1416a 578
e1ab7874 579 /* Round to the beginning of the next word. */
580 *regno = (*regno + HARD_REG_ELT_BITS - 1);
581 *regno -= *regno % HARD_REG_ELT_BITS;
582
583 /* Find the next non-zero word. */
584 while (++iter->word_no < iter->length)
585 {
586 iter->bits = iter->pelt[iter->word_no];
587 if (iter->bits)
588 break;
589 *regno += HARD_REG_ELT_BITS;
590 }
591 }
592}
593
594static inline void
595hard_reg_set_iter_next (hard_reg_set_iterator *iter, unsigned *regno)
596{
597 iter->bits >>= 1;
598 *regno += 1;
599}
600
601#define EXECUTE_IF_SET_IN_HARD_REG_SET(SET, MIN, REGNUM, ITER) \
602 for (hard_reg_set_iter_init (&(ITER), (SET), (MIN), &(REGNUM)); \
603 hard_reg_set_iter_set (&(ITER), &(REGNUM)); \
604 hard_reg_set_iter_next (&(ITER), &(REGNUM)))
605
606
6207bd2c 607/* Define some standard sets of registers. */
608
6207bd2c 609/* Indexed by hard register number, contains 1 for registers
610 that are being used for global register decls.
611 These must be exempt from ordinary flow analysis
612 and are also considered fixed. */
613
614extern char global_regs[FIRST_PSEUDO_REGISTER];
615
9969c043 616struct simplifiable_subreg;
617struct subreg_shape;
618
770ff93b 619struct simplifiable_subregs_hasher : nofree_ptr_hash <simplifiable_subreg>
9969c043 620{
9969c043 621 typedef const subreg_shape *compare_type;
622
623 static inline hashval_t hash (const simplifiable_subreg *);
624 static inline bool equal (const simplifiable_subreg *, const subreg_shape *);
625};
18d9a614 626
6d0eb0c4 627struct target_hard_regs {
18d9a614 628 void finalize ();
629
9fbe2159 630 /* The set of registers that actually exist on the current target. */
631 HARD_REG_SET x_accessible_reg_set;
632
633 /* The set of registers that should be considered to be register
634 operands. It is a subset of x_accessible_reg_set. */
635 HARD_REG_SET x_operand_reg_set;
636
6d0eb0c4 637 /* Indexed by hard register number, contains 1 for registers
638 that are fixed use (stack pointer, pc, frame pointer, etc.;.
639 These are the registers that cannot be used to allocate
640 a pseudo reg whose life does not cross calls. */
641 char x_fixed_regs[FIRST_PSEUDO_REGISTER];
6207bd2c 642
6d0eb0c4 643 /* The same info as a HARD_REG_SET. */
644 HARD_REG_SET x_fixed_reg_set;
fbf51e51 645
6d0eb0c4 646 /* Indexed by hard register number, contains 1 for registers
647 that are fixed use or are clobbered by function calls.
648 These are the registers that cannot be used to allocate
649 a pseudo reg whose life crosses calls. */
650 char x_call_used_regs[FIRST_PSEUDO_REGISTER];
fbf51e51 651
6d0eb0c4 652 char x_call_really_used_regs[FIRST_PSEUDO_REGISTER];
653
654 /* The same info as a HARD_REG_SET. */
655 HARD_REG_SET x_call_used_reg_set;
6207bd2c 656
6d0eb0c4 657 /* Contains registers that are fixed use -- i.e. in fixed_reg_set -- or
658 a function value return register or TARGET_STRUCT_VALUE_RTX or
659 STATIC_CHAIN_REGNUM. These are the registers that cannot hold quantities
660 across calls even if we are willing to save and restore them. */
661 HARD_REG_SET x_call_fixed_reg_set;
6207bd2c 662
69105acc 663 /* Contains registers that are fixed use -- i.e. in fixed_reg_set -- but
664 only if they are not merely part of that set because they are global
665 regs. Global regs that are not otherwise fixed can still take part
666 in register allocation. */
667 HARD_REG_SET x_fixed_nonglobal_reg_set;
668
6d0eb0c4 669 /* Contains 1 for registers that are set or clobbered by calls. */
670 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
671 for someone's bright idea to have call_used_regs strictly include
672 fixed_regs. Which leaves us guessing as to the set of fixed_regs
673 that are actually preserved. We know for sure that those associated
674 with the local stack frame are safe, but scant others. */
675 HARD_REG_SET x_regs_invalidated_by_call;
6207bd2c 676
f4d3c071 677 /* Call used hard registers which cannot be saved because there is no
c3997e3d 678 insn for this. */
679 HARD_REG_SET x_no_caller_save_reg_set;
680
6d0eb0c4 681 /* Table of register numbers in the order in which to try to use them. */
682 int x_reg_alloc_order[FIRST_PSEUDO_REGISTER];
bccb5444 683
6d0eb0c4 684 /* The inverse of reg_alloc_order. */
685 int x_inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
6207bd2c 686
6d0eb0c4 687 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
688 HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
6207bd2c 689
6d0eb0c4 690 /* For each reg class, a boolean saying whether the class contains only
691 fixed registers. */
692 bool x_class_only_fixed_regs[N_REG_CLASSES];
47dd2e78 693
6d0eb0c4 694 /* For each reg class, number of regs it contains. */
695 unsigned int x_reg_class_size[N_REG_CLASSES];
47dd2e78 696
6d0eb0c4 697 /* For each reg class, table listing all the classes contained in it. */
698 enum reg_class x_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
6207bd2c 699
6d0eb0c4 700 /* For each pair of reg classes,
701 a largest reg class contained in their union. */
702 enum reg_class x_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
6207bd2c 703
6d0eb0c4 704 /* For each pair of reg classes,
705 the smallest reg class that contains their union. */
706 enum reg_class x_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
6207bd2c 707
6d0eb0c4 708 /* Vector indexed by hardware reg giving its name. */
709 const char *x_reg_names[FIRST_PSEUDO_REGISTER];
18d9a614 710
711 /* Records which registers can form a particular subreg, with the subreg
712 being identified by its outer mode, inner mode and offset. */
713 hash_table <simplifiable_subregs_hasher> *x_simplifiable_subregs;
6d0eb0c4 714};
6207bd2c 715
6d0eb0c4 716extern struct target_hard_regs default_target_hard_regs;
717#if SWITCHABLE_TARGET
718extern struct target_hard_regs *this_target_hard_regs;
719#else
720#define this_target_hard_regs (&default_target_hard_regs)
721#endif
6207bd2c 722
9fbe2159 723#define accessible_reg_set \
724 (this_target_hard_regs->x_accessible_reg_set)
725#define operand_reg_set \
726 (this_target_hard_regs->x_operand_reg_set)
6d0eb0c4 727#define fixed_regs \
728 (this_target_hard_regs->x_fixed_regs)
729#define fixed_reg_set \
730 (this_target_hard_regs->x_fixed_reg_set)
69105acc 731#define fixed_nonglobal_reg_set \
732 (this_target_hard_regs->x_fixed_nonglobal_reg_set)
6d0eb0c4 733#define call_used_regs \
734 (this_target_hard_regs->x_call_used_regs)
735#define call_really_used_regs \
736 (this_target_hard_regs->x_call_really_used_regs)
737#define call_used_reg_set \
738 (this_target_hard_regs->x_call_used_reg_set)
739#define call_fixed_reg_set \
740 (this_target_hard_regs->x_call_fixed_reg_set)
741#define regs_invalidated_by_call \
742 (this_target_hard_regs->x_regs_invalidated_by_call)
c3997e3d 743#define no_caller_save_reg_set \
744 (this_target_hard_regs->x_no_caller_save_reg_set)
6d0eb0c4 745#define reg_alloc_order \
746 (this_target_hard_regs->x_reg_alloc_order)
747#define inv_reg_alloc_order \
748 (this_target_hard_regs->x_inv_reg_alloc_order)
749#define reg_class_contents \
750 (this_target_hard_regs->x_reg_class_contents)
751#define class_only_fixed_regs \
752 (this_target_hard_regs->x_class_only_fixed_regs)
753#define reg_class_size \
754 (this_target_hard_regs->x_reg_class_size)
755#define reg_class_subclasses \
756 (this_target_hard_regs->x_reg_class_subclasses)
757#define reg_class_subunion \
758 (this_target_hard_regs->x_reg_class_subunion)
759#define reg_class_superunion \
760 (this_target_hard_regs->x_reg_class_superunion)
761#define reg_names \
762 (this_target_hard_regs->x_reg_names)
89e8d34f 763
ada8adad 764/* Vector indexed by reg class giving its name. */
765
766extern const char * reg_class_names[];
767
b56a9dbc 768/* Given a hard REGN a FROM mode and a TO mode, return true if
769 REGN can change from mode FROM to mode TO. */
770#define REG_CAN_CHANGE_MODE_P(REGN, FROM, TO) \
771 (targetm.can_change_mode_class (FROM, TO, REGNO_REG_CLASS (REGN)))
897118e8 772
2a281353 773#endif /* ! GCC_HARD_REG_SET_H */