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55a2c322 | 1 | /* LRA (local register allocator) driver and LRA utilities. |
8d9254fc | 2 | Copyright (C) 2010-2020 Free Software Foundation, Inc. |
55a2c322 VM |
3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* The Local Register Allocator (LRA) is a replacement of former | |
23 | reload pass. It is focused to simplify code solving the reload | |
24 | pass tasks, to make the code maintenance easier, and to implement new | |
25 | perspective optimizations. | |
26 | ||
27 | The major LRA design solutions are: | |
28 | o division small manageable, separated sub-tasks | |
29 | o reflection of all transformations and decisions in RTL as more | |
30 | as possible | |
31 | o insn constraints as a primary source of the info (minimizing | |
32 | number of target-depended macros/hooks) | |
33 | ||
34 | In brief LRA works by iterative insn process with the final goal is | |
35 | to satisfy all insn and address constraints: | |
36 | o New reload insns (in brief reloads) and reload pseudos might be | |
37 | generated; | |
38 | o Some pseudos might be spilled to assign hard registers to | |
39 | new reload pseudos; | |
d9cf932c | 40 | o Recalculating spilled pseudo values (rematerialization); |
55a2c322 VM |
41 | o Changing spilled pseudos to stack memory or their equivalences; |
42 | o Allocation stack memory changes the address displacement and | |
43 | new iteration is needed. | |
44 | ||
45 | Here is block diagram of LRA passes: | |
46 | ||
2b778c9d VM |
47 | ------------------------ |
48 | --------------- | Undo inheritance for | --------------- | |
49 | | Memory-memory | | spilled pseudos, | | New (and old) | | |
50 | | move coalesce |<---| splits for pseudos got |<-- | pseudos | | |
51 | --------------- | the same hard regs, | | assignment | | |
52 | Start | | and optional reloads | --------------- | |
53 | | | ------------------------ ^ | |
f38e1b0a VM |
54 | V | ---------------- | |
55 | ----------- V | Update virtual | | | |
56 | | Remove |----> ------------>| register | | | |
57 | | scratches | ^ | displacements | | | |
58 | ----------- | ---------------- | | |
59 | | | | | |
60 | | V New | | |
d9cf932c VM |
61 | | ------------ pseudos ------------------- |
62 | | |Constraints:| or insns | Inheritance/split | | |
63 | | | RTL |--------->| transformations | | |
64 | | | transfor- | | in EBB scope | | |
65 | | substi- | mations | ------------------- | |
66 | | tutions ------------ | |
67 | | | No change | |
68 | ---------------- V | |
69 | | Spilled pseudo | ------------------- | |
70 | | to memory |<----| Rematerialization | | |
71 | | substitution | ------------------- | |
72 | ---------------- | |
73 | | No susbtitions | |
74 | V | |
75 | ------------------------- | |
76 | | Hard regs substitution, | | |
77 | | devirtalization, and |------> Finish | |
78 | | restoring scratches got | | |
79 | | memory | | |
80 | ------------------------- | |
55a2c322 VM |
81 | |
82 | To speed up the process: | |
83 | o We process only insns affected by changes on previous | |
84 | iterations; | |
85 | o We don't use DFA-infrastructure because it results in much slower | |
86 | compiler speed than a special IR described below does; | |
87 | o We use a special insn representation for quick access to insn | |
88 | info which is always *synchronized* with the current RTL; | |
89 | o Insn IR is minimized by memory. It is divided on three parts: | |
90 | o one specific for each insn in RTL (only operand locations); | |
91 | o one common for all insns in RTL with the same insn code | |
92 | (different operand attributes from machine descriptions); | |
93 | o one oriented for maintenance of live info (list of pseudos). | |
94 | o Pseudo data: | |
95 | o all insns where the pseudo is referenced; | |
96 | o live info (conflicting hard regs, live ranges, # of | |
97 | references etc); | |
98 | o data used for assigning (preferred hard regs, costs etc). | |
99 | ||
100 | This file contains LRA driver, LRA utility functions and data, and | |
101 | code for dealing with scratches. */ | |
102 | ||
103 | #include "config.h" | |
104 | #include "system.h" | |
105 | #include "coretypes.h" | |
c7131fb2 | 106 | #include "backend.h" |
957060b5 | 107 | #include "target.h" |
55a2c322 | 108 | #include "rtl.h" |
957060b5 AM |
109 | #include "tree.h" |
110 | #include "predict.h" | |
c7131fb2 | 111 | #include "df.h" |
4d0cdd0c | 112 | #include "memmodel.h" |
55a2c322 | 113 | #include "tm_p.h" |
957060b5 | 114 | #include "optabs.h" |
55a2c322 | 115 | #include "regs.h" |
957060b5 | 116 | #include "ira.h" |
55a2c322 | 117 | #include "recog.h" |
55a2c322 | 118 | #include "expr.h" |
60393bbc AM |
119 | #include "cfgrtl.h" |
120 | #include "cfgbuild.h" | |
c7131fb2 | 121 | #include "lra.h" |
55a2c322 | 122 | #include "lra-int.h" |
013a8899 | 123 | #include "print-rtl.h" |
a1e6ee38 | 124 | #include "function-abi.h" |
55a2c322 | 125 | |
8160cd3e VM |
126 | /* Dump bitmap SET with TITLE and BB INDEX. */ |
127 | void | |
128 | lra_dump_bitmap_with_title (const char *title, bitmap set, int index) | |
129 | { | |
130 | unsigned int i; | |
131 | int count; | |
132 | bitmap_iterator bi; | |
133 | static const int max_nums_on_line = 10; | |
134 | ||
135 | if (bitmap_empty_p (set)) | |
136 | return; | |
137 | fprintf (lra_dump_file, " %s %d:", title, index); | |
138 | fprintf (lra_dump_file, "\n"); | |
139 | count = max_nums_on_line + 1; | |
140 | EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi) | |
141 | { | |
142 | if (count > max_nums_on_line) | |
143 | { | |
144 | fprintf (lra_dump_file, "\n "); | |
145 | count = 0; | |
146 | } | |
147 | fprintf (lra_dump_file, " %4u", i); | |
148 | count++; | |
149 | } | |
150 | fprintf (lra_dump_file, "\n"); | |
151 | } | |
152 | ||
55a2c322 VM |
153 | /* Hard registers currently not available for allocation. It can |
154 | changed after some hard registers become not eliminable. */ | |
155 | HARD_REG_SET lra_no_alloc_regs; | |
156 | ||
157 | static int get_new_reg_value (void); | |
158 | static void expand_reg_info (void); | |
159 | static void invalidate_insn_recog_data (int); | |
cfa434f6 DM |
160 | static int get_insn_freq (rtx_insn *); |
161 | static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, | |
162 | rtx_insn *, int); | |
2713e5db | 163 | static void remove_scratches_1 (rtx_insn *); |
55a2c322 VM |
164 | |
165 | /* Expand all regno related info needed for LRA. */ | |
166 | static void | |
a2d0d374 | 167 | expand_reg_data (int old) |
55a2c322 VM |
168 | { |
169 | resize_reg_info (); | |
170 | expand_reg_info (); | |
171 | ira_expand_reg_equiv (); | |
a2d0d374 VM |
172 | for (int i = (int) max_reg_num () - 1; i >= old; i--) |
173 | lra_change_class (i, ALL_REGS, " Set", true); | |
55a2c322 VM |
174 | } |
175 | ||
176 | /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL | |
177 | or of VOIDmode, use MD_MODE for the new reg. Initialize its | |
178 | register class to RCLASS. Print message about assigning class | |
179 | RCLASS containing new register name TITLE unless it is NULL. Use | |
180 | attributes of ORIGINAL if it is a register. The created register | |
181 | will have unique held value. */ | |
182 | rtx | |
ef4bddc2 | 183 | lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original, |
55a2c322 VM |
184 | enum reg_class rclass, const char *title) |
185 | { | |
ef4bddc2 | 186 | machine_mode mode; |
55a2c322 VM |
187 | rtx new_reg; |
188 | ||
189 | if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode) | |
190 | mode = md_mode; | |
191 | lra_assert (mode != VOIDmode); | |
192 | new_reg = gen_reg_rtx (mode); | |
193 | if (original == NULL_RTX || ! REG_P (original)) | |
194 | { | |
195 | if (lra_dump_file != NULL) | |
196 | fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)); | |
197 | } | |
198 | else | |
199 | { | |
200 | if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER) | |
201 | ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original); | |
202 | REG_USERVAR_P (new_reg) = REG_USERVAR_P (original); | |
203 | REG_POINTER (new_reg) = REG_POINTER (original); | |
204 | REG_ATTRS (new_reg) = REG_ATTRS (original); | |
205 | if (lra_dump_file != NULL) | |
206 | fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i", | |
207 | REGNO (new_reg), REGNO (original)); | |
208 | } | |
209 | if (lra_dump_file != NULL) | |
210 | { | |
211 | if (title != NULL) | |
212 | fprintf (lra_dump_file, ", assigning class %s to%s%s r%d", | |
213 | reg_class_names[rclass], *title == '\0' ? "" : " ", | |
214 | title, REGNO (new_reg)); | |
215 | fprintf (lra_dump_file, "\n"); | |
216 | } | |
a2d0d374 | 217 | expand_reg_data (max_reg_num ()); |
55a2c322 VM |
218 | setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); |
219 | return new_reg; | |
220 | } | |
221 | ||
222 | /* Analogous to the previous function but also inherits value of | |
223 | ORIGINAL. */ | |
224 | rtx | |
ef4bddc2 | 225 | lra_create_new_reg (machine_mode md_mode, rtx original, |
55a2c322 VM |
226 | enum reg_class rclass, const char *title) |
227 | { | |
228 | rtx new_reg; | |
229 | ||
230 | new_reg | |
231 | = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title); | |
232 | if (original != NULL_RTX && REG_P (original)) | |
d70a81dd | 233 | lra_assign_reg_val (REGNO (original), REGNO (new_reg)); |
55a2c322 VM |
234 | return new_reg; |
235 | } | |
236 | ||
237 | /* Set up for REGNO unique hold value. */ | |
238 | void | |
239 | lra_set_regno_unique_value (int regno) | |
240 | { | |
241 | lra_reg_info[regno].val = get_new_reg_value (); | |
242 | } | |
243 | ||
8d49e7ef VM |
244 | /* Invalidate INSN related info used by LRA. The info should never be |
245 | used after that. */ | |
55a2c322 | 246 | void |
cfa434f6 | 247 | lra_invalidate_insn_data (rtx_insn *insn) |
55a2c322 VM |
248 | { |
249 | lra_invalidate_insn_regno_info (insn); | |
250 | invalidate_insn_recog_data (INSN_UID (insn)); | |
251 | } | |
252 | ||
253 | /* Mark INSN deleted and invalidate the insn related info used by | |
254 | LRA. */ | |
255 | void | |
cfa434f6 | 256 | lra_set_insn_deleted (rtx_insn *insn) |
55a2c322 VM |
257 | { |
258 | lra_invalidate_insn_data (insn); | |
259 | SET_INSN_DELETED (insn); | |
260 | } | |
261 | ||
262 | /* Delete an unneeded INSN and any previous insns who sole purpose is | |
263 | loading data that is dead in INSN. */ | |
264 | void | |
cfa434f6 | 265 | lra_delete_dead_insn (rtx_insn *insn) |
55a2c322 | 266 | { |
cfa434f6 | 267 | rtx_insn *prev = prev_real_insn (insn); |
55a2c322 VM |
268 | rtx prev_dest; |
269 | ||
270 | /* If the previous insn sets a register that dies in our insn, | |
271 | delete it too. */ | |
272 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
273 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) | |
274 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
275 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) | |
276 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
277 | lra_delete_dead_insn (prev); | |
278 | ||
279 | lra_set_insn_deleted (insn); | |
280 | } | |
281 | ||
11f5b71a VM |
282 | /* Emit insn x = y + z. Return NULL if we failed to do it. |
283 | Otherwise, return the insn. We don't use gen_add3_insn as it might | |
284 | clobber CC. */ | |
e67d1102 | 285 | static rtx_insn * |
11f5b71a VM |
286 | emit_add3_insn (rtx x, rtx y, rtx z) |
287 | { | |
fee3e72c | 288 | rtx_insn *last; |
11f5b71a VM |
289 | |
290 | last = get_last_insn (); | |
72a4ddf2 AK |
291 | |
292 | if (have_addptr3_insn (x, y, z)) | |
293 | { | |
e67d1102 | 294 | rtx_insn *insn = gen_addptr3_insn (x, y, z); |
72a4ddf2 AK |
295 | |
296 | /* If the target provides an "addptr" pattern it hopefully does | |
297 | for a reason. So falling back to the normal add would be | |
298 | a bug. */ | |
299 | lra_assert (insn != NULL_RTX); | |
300 | emit_insn (insn); | |
301 | return insn; | |
302 | } | |
303 | ||
f7df4a84 RS |
304 | rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y), |
305 | y, z))); | |
11f5b71a VM |
306 | if (recog_memoized (insn) < 0) |
307 | { | |
308 | delete_insns_since (last); | |
647d790d | 309 | insn = NULL; |
11f5b71a VM |
310 | } |
311 | return insn; | |
312 | } | |
313 | ||
314 | /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the | |
315 | last resort. */ | |
e67d1102 | 316 | static rtx_insn * |
11f5b71a VM |
317 | emit_add2_insn (rtx x, rtx y) |
318 | { | |
e67d1102 | 319 | rtx_insn *insn = emit_add3_insn (x, x, y); |
11f5b71a VM |
320 | if (insn == NULL_RTX) |
321 | { | |
322 | insn = gen_add2_insn (x, y); | |
323 | if (insn != NULL_RTX) | |
324 | emit_insn (insn); | |
325 | } | |
326 | return insn; | |
327 | } | |
328 | ||
55a2c322 VM |
329 | /* Target checks operands through operand predicates to recognize an |
330 | insn. We should have a special precaution to generate add insns | |
331 | which are frequent results of elimination. | |
332 | ||
333 | Emit insns for x = y + z. X can be used to store intermediate | |
334 | values and should be not in Y and Z when we use X to store an | |
335 | intermediate value. Y + Z should form [base] [+ index[ * scale]] [ | |
336 | + disp] where base and index are registers, disp and scale are | |
337 | constants. Y should contain base if it is present, Z should | |
338 | contain disp if any. index[*scale] can be part of Y or Z. */ | |
339 | void | |
340 | lra_emit_add (rtx x, rtx y, rtx z) | |
341 | { | |
342 | int old; | |
fee3e72c | 343 | rtx_insn *last; |
55a2c322 VM |
344 | rtx a1, a2, base, index, disp, scale, index_scale; |
345 | bool ok_p; | |
346 | ||
e67d1102 | 347 | rtx_insn *add3_insn = emit_add3_insn (x, y, z); |
55a2c322 | 348 | old = max_reg_num (); |
647d790d | 349 | if (add3_insn != NULL) |
11f5b71a | 350 | ; |
55a2c322 VM |
351 | else |
352 | { | |
353 | disp = a2 = NULL_RTX; | |
354 | if (GET_CODE (y) == PLUS) | |
355 | { | |
356 | a1 = XEXP (y, 0); | |
357 | a2 = XEXP (y, 1); | |
358 | disp = z; | |
359 | } | |
360 | else | |
361 | { | |
362 | a1 = y; | |
363 | if (CONSTANT_P (z)) | |
364 | disp = z; | |
365 | else | |
366 | a2 = z; | |
367 | } | |
368 | index_scale = scale = NULL_RTX; | |
369 | if (GET_CODE (a1) == MULT) | |
370 | { | |
371 | index_scale = a1; | |
372 | index = XEXP (a1, 0); | |
373 | scale = XEXP (a1, 1); | |
374 | base = a2; | |
375 | } | |
376 | else if (a2 != NULL_RTX && GET_CODE (a2) == MULT) | |
377 | { | |
378 | index_scale = a2; | |
379 | index = XEXP (a2, 0); | |
380 | scale = XEXP (a2, 1); | |
381 | base = a1; | |
382 | } | |
383 | else | |
384 | { | |
385 | base = a1; | |
386 | index = a2; | |
387 | } | |
0b87be09 | 388 | if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG)) |
93aaa05d VM |
389 | || (index != NULL_RTX |
390 | && ! (REG_P (index) || GET_CODE (index) == SUBREG)) | |
55a2c322 VM |
391 | || (disp != NULL_RTX && ! CONSTANT_P (disp)) |
392 | || (scale != NULL_RTX && ! CONSTANT_P (scale))) | |
393 | { | |
11f5b71a VM |
394 | /* Probably we have no 3 op add. Last chance is to use 2-op |
395 | add insn. To succeed, don't move Z to X as an address | |
396 | segment always comes in Y. Otherwise, we might fail when | |
397 | adding the address segment to register. */ | |
55a2c322 | 398 | lra_assert (x != y && x != z); |
ed52a84e | 399 | emit_move_insn (x, y); |
e67d1102 | 400 | rtx_insn *insn = emit_add2_insn (x, z); |
11f5b71a | 401 | lra_assert (insn != NULL_RTX); |
55a2c322 VM |
402 | } |
403 | else | |
404 | { | |
405 | if (index_scale == NULL_RTX) | |
406 | index_scale = index; | |
407 | if (disp == NULL_RTX) | |
408 | { | |
409 | /* Generate x = index_scale; x = x + base. */ | |
410 | lra_assert (index_scale != NULL_RTX && base != NULL_RTX); | |
411 | emit_move_insn (x, index_scale); | |
e67d1102 | 412 | rtx_insn *insn = emit_add2_insn (x, base); |
11f5b71a | 413 | lra_assert (insn != NULL_RTX); |
55a2c322 VM |
414 | } |
415 | else if (scale == NULL_RTX) | |
416 | { | |
417 | /* Try x = base + disp. */ | |
418 | lra_assert (base != NULL_RTX); | |
419 | last = get_last_insn (); | |
647d790d DM |
420 | rtx_insn *move_insn = |
421 | emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp)); | |
422 | if (recog_memoized (move_insn) < 0) | |
55a2c322 VM |
423 | { |
424 | delete_insns_since (last); | |
425 | /* Generate x = disp; x = x + base. */ | |
426 | emit_move_insn (x, disp); | |
e67d1102 | 427 | rtx_insn *add2_insn = emit_add2_insn (x, base); |
647d790d | 428 | lra_assert (add2_insn != NULL_RTX); |
55a2c322 VM |
429 | } |
430 | /* Generate x = x + index. */ | |
431 | if (index != NULL_RTX) | |
432 | { | |
e67d1102 | 433 | rtx_insn *insn = emit_add2_insn (x, index); |
11f5b71a | 434 | lra_assert (insn != NULL_RTX); |
55a2c322 VM |
435 | } |
436 | } | |
437 | else | |
438 | { | |
439 | /* Try x = index_scale; x = x + disp; x = x + base. */ | |
440 | last = get_last_insn (); | |
647d790d | 441 | rtx_insn *move_insn = emit_move_insn (x, index_scale); |
55a2c322 | 442 | ok_p = false; |
647d790d | 443 | if (recog_memoized (move_insn) >= 0) |
55a2c322 | 444 | { |
e67d1102 | 445 | rtx_insn *insn = emit_add2_insn (x, disp); |
55a2c322 VM |
446 | if (insn != NULL_RTX) |
447 | { | |
0b87be09 | 448 | if (base == NULL_RTX) |
11f5b71a | 449 | ok_p = true; |
0b87be09 VM |
450 | else |
451 | { | |
452 | insn = emit_add2_insn (x, base); | |
453 | if (insn != NULL_RTX) | |
454 | ok_p = true; | |
455 | } | |
55a2c322 VM |
456 | } |
457 | } | |
458 | if (! ok_p) | |
459 | { | |
0b87be09 VM |
460 | rtx_insn *insn; |
461 | ||
55a2c322 VM |
462 | delete_insns_since (last); |
463 | /* Generate x = disp; x = x + base; x = x + index_scale. */ | |
464 | emit_move_insn (x, disp); | |
0b87be09 VM |
465 | if (base != NULL_RTX) |
466 | { | |
467 | insn = emit_add2_insn (x, base); | |
468 | lra_assert (insn != NULL_RTX); | |
469 | } | |
11f5b71a VM |
470 | insn = emit_add2_insn (x, index_scale); |
471 | lra_assert (insn != NULL_RTX); | |
55a2c322 VM |
472 | } |
473 | } | |
474 | } | |
475 | } | |
476 | /* Functions emit_... can create pseudos -- so expand the pseudo | |
477 | data. */ | |
478 | if (old != max_reg_num ()) | |
a2d0d374 | 479 | expand_reg_data (old); |
55a2c322 VM |
480 | } |
481 | ||
482 | /* The number of emitted reload insns so far. */ | |
483 | int lra_curr_reload_num; | |
484 | ||
485 | /* Emit x := y, processing special case when y = u + v or y = u + v * | |
486 | scale + w through emit_add (Y can be an address which is base + | |
487 | index reg * scale + displacement in general case). X may be used | |
488 | as intermediate result therefore it should be not in Y. */ | |
489 | void | |
490 | lra_emit_move (rtx x, rtx y) | |
491 | { | |
492 | int old; | |
493 | ||
494 | if (GET_CODE (y) != PLUS) | |
495 | { | |
496 | if (rtx_equal_p (x, y)) | |
497 | return; | |
498 | old = max_reg_num (); | |
2713e5db PB |
499 | rtx_insn *insn = emit_move_insn (x, y); |
500 | /* The move pattern may require scratch registers, so convert them | |
501 | into real registers now. */ | |
502 | if (insn != NULL_RTX) | |
503 | remove_scratches_1 (insn); | |
55a2c322 VM |
504 | if (REG_P (x)) |
505 | lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num; | |
506 | /* Function emit_move can create pseudos -- so expand the pseudo | |
507 | data. */ | |
508 | if (old != max_reg_num ()) | |
a2d0d374 | 509 | expand_reg_data (old); |
55a2c322 VM |
510 | return; |
511 | } | |
512 | lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); | |
513 | } | |
514 | ||
515 | /* Update insn operands which are duplication of operands whose | |
516 | numbers are in array of NOPS (with end marker -1). The insn is | |
517 | represented by its LRA internal representation ID. */ | |
518 | void | |
519 | lra_update_dups (lra_insn_recog_data_t id, signed char *nops) | |
520 | { | |
521 | int i, j, nop; | |
522 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
523 | ||
524 | for (i = 0; i < static_id->n_dups; i++) | |
525 | for (j = 0; (nop = nops[j]) >= 0; j++) | |
526 | if (static_id->dup_num[i] == nop) | |
527 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
528 | } | |
529 | ||
530 | \f | |
531 | ||
532 | /* This page contains code dealing with info about registers in the | |
533 | insns. */ | |
534 | ||
535 | /* Pools for insn reg info. */ | |
fcb87c50 | 536 | object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs"); |
55a2c322 | 537 | |
584898ee VM |
538 | /* Create LRA insn related info about a reference to REGNO in INSN |
539 | with TYPE (in/out/inout), biggest reference mode MODE, flag that it | |
a25f3e8e | 540 | is reference through subreg (SUBREG_P), and reference to the next |
584898ee VM |
541 | insn reg info (NEXT). If REGNO can be early clobbered, |
542 | alternatives in which it can be early clobbered are given by | |
17d184e5 | 543 | EARLY_CLOBBER_ALTS. */ |
55a2c322 | 544 | static struct lra_insn_reg * |
cfa434f6 | 545 | new_insn_reg (rtx_insn *insn, int regno, enum op_type type, |
a25f3e8e | 546 | machine_mode mode, bool subreg_p, |
584898ee | 547 | alternative_mask early_clobber_alts, |
17d184e5 | 548 | struct lra_insn_reg *next) |
55a2c322 | 549 | { |
fb0b2914 | 550 | lra_insn_reg *ir = lra_insn_reg_pool.allocate (); |
55a2c322 VM |
551 | ir->type = type; |
552 | ir->biggest_mode = mode; | |
bd4288c0 RS |
553 | if (NONDEBUG_INSN_P (insn) |
554 | && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode)) | |
b28ece32 | 555 | lra_reg_info[regno].biggest_mode = mode; |
55a2c322 | 556 | ir->subreg_p = subreg_p; |
584898ee | 557 | ir->early_clobber_alts = early_clobber_alts; |
55a2c322 VM |
558 | ir->regno = regno; |
559 | ir->next = next; | |
560 | return ir; | |
561 | } | |
562 | ||
55a2c322 VM |
563 | /* Free insn reg info list IR. */ |
564 | static void | |
565 | free_insn_regs (struct lra_insn_reg *ir) | |
566 | { | |
567 | struct lra_insn_reg *next_ir; | |
568 | ||
569 | for (; ir != NULL; ir = next_ir) | |
570 | { | |
571 | next_ir = ir->next; | |
fb0b2914 | 572 | lra_insn_reg_pool.remove (ir); |
55a2c322 VM |
573 | } |
574 | } | |
575 | ||
576 | /* Finish pool for insn reg info. */ | |
577 | static void | |
578 | finish_insn_regs (void) | |
579 | { | |
fb0b2914 | 580 | lra_insn_reg_pool.release (); |
55a2c322 VM |
581 | } |
582 | ||
583 | \f | |
584 | ||
585 | /* This page contains code dealing LRA insn info (or in other words | |
586 | LRA internal insn representation). */ | |
587 | ||
55a2c322 VM |
588 | /* Map INSN_CODE -> the static insn data. This info is valid during |
589 | all translation unit. */ | |
523ba738 | 590 | struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES]; |
55a2c322 VM |
591 | |
592 | /* Debug insns are represented as a special insn with one input | |
593 | operand which is RTL expression in var_location. */ | |
594 | ||
595 | /* The following data are used as static insn operand data for all | |
596 | debug insns. If structure lra_operand_data is changed, the | |
597 | initializer should be changed too. */ | |
598 | static struct lra_operand_data debug_operand_data = | |
599 | { | |
600 | NULL, /* alternative */ | |
584898ee | 601 | 0, /* early_clobber_alts */ |
0d4a1197 | 602 | E_VOIDmode, /* We are not interesting in the operand mode. */ |
55a2c322 | 603 | OP_IN, |
a25f3e8e | 604 | 0, 0, 0 |
55a2c322 VM |
605 | }; |
606 | ||
607 | /* The following data are used as static insn data for all debug | |
96a95ac1 | 608 | bind insns. If structure lra_static_insn_data is changed, the |
55a2c322 | 609 | initializer should be changed too. */ |
96a95ac1 | 610 | static struct lra_static_insn_data debug_bind_static_data = |
55a2c322 VM |
611 | { |
612 | &debug_operand_data, | |
613 | 0, /* Duplication operands #. */ | |
614 | -1, /* Commutative operand #. */ | |
615 | 1, /* Operands #. There is only one operand which is debug RTL | |
616 | expression. */ | |
617 | 0, /* Duplications #. */ | |
618 | 0, /* Alternatives #. We are not interesting in alternatives | |
619 | because we does not proceed debug_insns for reloads. */ | |
620 | NULL, /* Hard registers referenced in machine description. */ | |
621 | NULL /* Descriptions of operands in alternatives. */ | |
622 | }; | |
623 | ||
96a95ac1 AO |
624 | /* The following data are used as static insn data for all debug |
625 | marker insns. If structure lra_static_insn_data is changed, the | |
626 | initializer should be changed too. */ | |
627 | static struct lra_static_insn_data debug_marker_static_data = | |
628 | { | |
629 | &debug_operand_data, | |
630 | 0, /* Duplication operands #. */ | |
631 | -1, /* Commutative operand #. */ | |
632 | 0, /* Operands #. There isn't any operand. */ | |
633 | 0, /* Duplications #. */ | |
634 | 0, /* Alternatives #. We are not interesting in alternatives | |
635 | because we does not proceed debug_insns for reloads. */ | |
636 | NULL, /* Hard registers referenced in machine description. */ | |
637 | NULL /* Descriptions of operands in alternatives. */ | |
638 | }; | |
639 | ||
55a2c322 VM |
640 | /* Called once per compiler work to initialize some LRA data related |
641 | to insns. */ | |
642 | static void | |
643 | init_insn_code_data_once (void) | |
644 | { | |
645 | memset (insn_code_data, 0, sizeof (insn_code_data)); | |
55a2c322 VM |
646 | } |
647 | ||
648 | /* Called once per compiler work to finalize some LRA data related to | |
649 | insns. */ | |
650 | static void | |
651 | finish_insn_code_data_once (void) | |
652 | { | |
523ba738 | 653 | for (unsigned int i = 0; i < NUM_INSN_CODES; i++) |
55a2c322 VM |
654 | { |
655 | if (insn_code_data[i] != NULL) | |
3809bcd6 DM |
656 | { |
657 | free (insn_code_data[i]); | |
658 | insn_code_data[i] = NULL; | |
659 | } | |
55a2c322 VM |
660 | } |
661 | } | |
662 | ||
55a2c322 VM |
663 | /* Return static insn data, allocate and setup if necessary. Although |
664 | dup_num is static data (it depends only on icode), to set it up we | |
665 | need to extract insn first. So recog_data should be valid for | |
666 | normal insn (ICODE >= 0) before the call. */ | |
667 | static struct lra_static_insn_data * | |
668 | get_static_insn_data (int icode, int nop, int ndup, int nalt) | |
669 | { | |
670 | struct lra_static_insn_data *data; | |
671 | size_t n_bytes; | |
672 | ||
523ba738 | 673 | lra_assert (icode < (int) NUM_INSN_CODES); |
55a2c322 VM |
674 | if (icode >= 0 && (data = insn_code_data[icode]) != NULL) |
675 | return data; | |
676 | lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0); | |
677 | n_bytes = sizeof (struct lra_static_insn_data) | |
678 | + sizeof (struct lra_operand_data) * nop | |
679 | + sizeof (int) * ndup; | |
680 | data = XNEWVAR (struct lra_static_insn_data, n_bytes); | |
0c331756 | 681 | data->operand_alternative = NULL; |
55a2c322 VM |
682 | data->n_operands = nop; |
683 | data->n_dups = ndup; | |
684 | data->n_alternatives = nalt; | |
685 | data->operand = ((struct lra_operand_data *) | |
686 | ((char *) data + sizeof (struct lra_static_insn_data))); | |
687 | data->dup_num = ((int *) ((char *) data->operand | |
688 | + sizeof (struct lra_operand_data) * nop)); | |
689 | if (icode >= 0) | |
690 | { | |
691 | int i; | |
692 | ||
693 | insn_code_data[icode] = data; | |
694 | for (i = 0; i < nop; i++) | |
695 | { | |
696 | data->operand[i].constraint | |
697 | = insn_data[icode].operand[i].constraint; | |
698 | data->operand[i].mode = insn_data[icode].operand[i].mode; | |
699 | data->operand[i].strict_low = insn_data[icode].operand[i].strict_low; | |
700 | data->operand[i].is_operator | |
701 | = insn_data[icode].operand[i].is_operator; | |
702 | data->operand[i].type | |
703 | = (data->operand[i].constraint[0] == '=' ? OP_OUT | |
704 | : data->operand[i].constraint[0] == '+' ? OP_INOUT | |
705 | : OP_IN); | |
706 | data->operand[i].is_address = false; | |
707 | } | |
708 | for (i = 0; i < ndup; i++) | |
709 | data->dup_num[i] = recog_data.dup_num[i]; | |
710 | } | |
711 | return data; | |
712 | } | |
713 | ||
714 | /* The current length of the following array. */ | |
715 | int lra_insn_recog_data_len; | |
716 | ||
717 | /* Map INSN_UID -> the insn recog data (NULL if unknown). */ | |
718 | lra_insn_recog_data_t *lra_insn_recog_data; | |
719 | ||
033bd26e RB |
720 | /* Alloc pool we allocate entries for lra_insn_recog_data from. */ |
721 | static object_allocator<class lra_insn_recog_data> | |
722 | lra_insn_recog_data_pool ("insn recog data pool"); | |
723 | ||
55a2c322 VM |
724 | /* Initialize LRA data about insns. */ |
725 | static void | |
726 | init_insn_recog_data (void) | |
727 | { | |
728 | lra_insn_recog_data_len = 0; | |
729 | lra_insn_recog_data = NULL; | |
55a2c322 VM |
730 | } |
731 | ||
732 | /* Expand, if necessary, LRA data about insns. */ | |
733 | static void | |
734 | check_and_expand_insn_recog_data (int index) | |
735 | { | |
736 | int i, old; | |
737 | ||
738 | if (lra_insn_recog_data_len > index) | |
739 | return; | |
740 | old = lra_insn_recog_data_len; | |
741 | lra_insn_recog_data_len = index * 3 / 2 + 1; | |
742 | lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t, | |
743 | lra_insn_recog_data, | |
744 | lra_insn_recog_data_len); | |
745 | for (i = old; i < lra_insn_recog_data_len; i++) | |
746 | lra_insn_recog_data[i] = NULL; | |
747 | } | |
748 | ||
749 | /* Finish LRA DATA about insn. */ | |
750 | static void | |
751 | free_insn_recog_data (lra_insn_recog_data_t data) | |
752 | { | |
753 | if (data->operand_loc != NULL) | |
754 | free (data->operand_loc); | |
755 | if (data->dup_loc != NULL) | |
756 | free (data->dup_loc); | |
757 | if (data->arg_hard_regs != NULL) | |
758 | free (data->arg_hard_regs); | |
55a2c322 VM |
759 | if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)) |
760 | { | |
761 | if (data->insn_static_data->operand_alternative != NULL) | |
0c331756 RS |
762 | free (const_cast <operand_alternative *> |
763 | (data->insn_static_data->operand_alternative)); | |
55a2c322 VM |
764 | free_insn_regs (data->insn_static_data->hard_regs); |
765 | free (data->insn_static_data); | |
766 | } | |
767 | free_insn_regs (data->regs); | |
768 | data->regs = NULL; | |
033bd26e | 769 | lra_insn_recog_data_pool.remove (data); |
55a2c322 VM |
770 | } |
771 | ||
fb0b2914 | 772 | /* Pools for copies. */ |
fcb87c50 | 773 | static object_allocator<lra_copy> lra_copy_pool ("lra copies"); |
fb0b2914 | 774 | |
55a2c322 VM |
775 | /* Finish LRA data about all insns. */ |
776 | static void | |
777 | finish_insn_recog_data (void) | |
778 | { | |
779 | int i; | |
780 | lra_insn_recog_data_t data; | |
781 | ||
782 | for (i = 0; i < lra_insn_recog_data_len; i++) | |
783 | if ((data = lra_insn_recog_data[i]) != NULL) | |
784 | free_insn_recog_data (data); | |
785 | finish_insn_regs (); | |
fb0b2914 ML |
786 | lra_copy_pool.release (); |
787 | lra_insn_reg_pool.release (); | |
033bd26e | 788 | lra_insn_recog_data_pool.release (); |
55a2c322 VM |
789 | free (lra_insn_recog_data); |
790 | } | |
791 | ||
792 | /* Setup info about operands in alternatives of LRA DATA of insn. */ | |
793 | static void | |
0c331756 RS |
794 | setup_operand_alternative (lra_insn_recog_data_t data, |
795 | const operand_alternative *op_alt) | |
55a2c322 | 796 | { |
0c331756 | 797 | int i, j, nop, nalt; |
55a2c322 VM |
798 | int icode = data->icode; |
799 | struct lra_static_insn_data *static_data = data->insn_static_data; | |
800 | ||
55a2c322 VM |
801 | static_data->commutative = -1; |
802 | nop = static_data->n_operands; | |
55a2c322 | 803 | nalt = static_data->n_alternatives; |
0c331756 | 804 | static_data->operand_alternative = op_alt; |
55a2c322 VM |
805 | for (i = 0; i < nop; i++) |
806 | { | |
584898ee | 807 | static_data->operand[i].early_clobber_alts = 0; |
0c331756 RS |
808 | static_data->operand[i].is_address = false; |
809 | if (static_data->operand[i].constraint[0] == '%') | |
55a2c322 | 810 | { |
0c331756 RS |
811 | /* We currently only support one commutative pair of operands. */ |
812 | if (static_data->commutative < 0) | |
813 | static_data->commutative = i; | |
814 | else | |
815 | lra_assert (icode < 0); /* Asm */ | |
816 | /* The last operand should not be marked commutative. */ | |
817 | lra_assert (i != nop - 1); | |
55a2c322 VM |
818 | } |
819 | } | |
0c331756 RS |
820 | for (j = 0; j < nalt; j++) |
821 | for (i = 0; i < nop; i++, op_alt++) | |
822 | { | |
584898ee VM |
823 | if (op_alt->earlyclobber) |
824 | static_data->operand[i].early_clobber_alts |= (alternative_mask) 1 << j; | |
0c331756 RS |
825 | static_data->operand[i].is_address |= op_alt->is_address; |
826 | } | |
55a2c322 VM |
827 | } |
828 | ||
829 | /* Recursively process X and collect info about registers, which are | |
830 | not the insn operands, in X with TYPE (in/out/inout) and flag that | |
831 | it is early clobbered in the insn (EARLY_CLOBBER) and add the info | |
832 | to LIST. X is a part of insn given by DATA. Return the result | |
17d184e5 | 833 | list. */ |
55a2c322 | 834 | static struct lra_insn_reg * |
561c58b4 VM |
835 | collect_non_operand_hard_regs (rtx_insn *insn, rtx *x, |
836 | lra_insn_recog_data_t data, | |
55a2c322 | 837 | struct lra_insn_reg *list, |
17d184e5 | 838 | enum op_type type, bool early_clobber) |
55a2c322 VM |
839 | { |
840 | int i, j, regno, last; | |
841 | bool subreg_p; | |
ef4bddc2 | 842 | machine_mode mode; |
55a2c322 VM |
843 | struct lra_insn_reg *curr; |
844 | rtx op = *x; | |
845 | enum rtx_code code = GET_CODE (op); | |
846 | const char *fmt = GET_RTX_FORMAT (code); | |
847 | ||
848 | for (i = 0; i < data->insn_static_data->n_operands; i++) | |
2de3d3c6 VM |
849 | if (! data->insn_static_data->operand[i].is_operator |
850 | && x == data->operand_loc[i]) | |
55a2c322 VM |
851 | /* It is an operand loc. Stop here. */ |
852 | return list; | |
853 | for (i = 0; i < data->insn_static_data->n_dups; i++) | |
854 | if (x == data->dup_loc[i]) | |
855 | /* It is a dup loc. Stop here. */ | |
856 | return list; | |
857 | mode = GET_MODE (op); | |
858 | subreg_p = false; | |
859 | if (code == SUBREG) | |
860 | { | |
bd5a2c67 | 861 | mode = wider_subreg_mode (op); |
9eaf97d6 RS |
862 | if (read_modify_subreg_p (op)) |
863 | subreg_p = true; | |
55a2c322 VM |
864 | op = SUBREG_REG (op); |
865 | code = GET_CODE (op); | |
55a2c322 VM |
866 | } |
867 | if (REG_P (op)) | |
868 | { | |
869 | if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER) | |
870 | return list; | |
d9cf932c VM |
871 | /* Process all regs even unallocatable ones as we need info |
872 | about all regs for rematerialization pass. */ | |
4edd6298 | 873 | for (last = end_hard_regno (mode, regno); regno < last; regno++) |
d9cf932c VM |
874 | { |
875 | for (curr = list; curr != NULL; curr = curr->next) | |
876 | if (curr->regno == regno && curr->subreg_p == subreg_p | |
877 | && curr->biggest_mode == mode) | |
55a2c322 | 878 | { |
d9cf932c VM |
879 | if (curr->type != type) |
880 | curr->type = OP_INOUT; | |
584898ee | 881 | if (early_clobber) |
a25f3e8e | 882 | curr->early_clobber_alts = ALL_ALTERNATIVES; |
d9cf932c VM |
883 | break; |
884 | } | |
885 | if (curr == NULL) | |
886 | { | |
67914693 | 887 | /* This is a new hard regno or the info cannot be |
d9cf932c | 888 | integrated into the found structure. */ |
55a2c322 | 889 | #ifdef STACK_REGS |
d9cf932c VM |
890 | early_clobber |
891 | = (early_clobber | |
892 | /* This clobber is to inform popping floating | |
893 | point stack only. */ | |
894 | && ! (FIRST_STACK_REG <= regno | |
895 | && regno <= LAST_STACK_REG)); | |
55a2c322 | 896 | #endif |
d9cf932c | 897 | list = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
17d184e5 | 898 | early_clobber ? ALL_ALTERNATIVES : 0, list); |
d9cf932c VM |
899 | } |
900 | } | |
55a2c322 VM |
901 | return list; |
902 | } | |
903 | switch (code) | |
904 | { | |
905 | case SET: | |
561c58b4 | 906 | list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data, |
17d184e5 | 907 | list, OP_OUT, false); |
561c58b4 | 908 | list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data, |
17d184e5 | 909 | list, OP_IN, false); |
55a2c322 VM |
910 | break; |
911 | case CLOBBER: | |
80850da1 SB |
912 | /* We treat clobber of non-operand hard registers as early clobber. */ |
913 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, | |
17d184e5 | 914 | list, OP_OUT, true); |
80850da1 | 915 | break; |
55a2c322 | 916 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: |
561c58b4 | 917 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, |
17d184e5 | 918 | list, OP_INOUT, false); |
55a2c322 VM |
919 | break; |
920 | case PRE_MODIFY: case POST_MODIFY: | |
561c58b4 | 921 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, |
17d184e5 | 922 | list, OP_INOUT, false); |
561c58b4 | 923 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data, |
17d184e5 | 924 | list, OP_IN, false); |
55a2c322 VM |
925 | break; |
926 | default: | |
927 | fmt = GET_RTX_FORMAT (code); | |
928 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
929 | { | |
930 | if (fmt[i] == 'e') | |
561c58b4 | 931 | list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data, |
17d184e5 | 932 | list, OP_IN, false); |
55a2c322 VM |
933 | else if (fmt[i] == 'E') |
934 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
561c58b4 | 935 | list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j), |
17d184e5 | 936 | data, list, OP_IN, false); |
55a2c322 VM |
937 | } |
938 | } | |
939 | return list; | |
940 | } | |
941 | ||
942 | /* Set up and return info about INSN. Set up the info if it is not set up | |
943 | yet. */ | |
944 | lra_insn_recog_data_t | |
cfa434f6 | 945 | lra_set_insn_recog_data (rtx_insn *insn) |
55a2c322 VM |
946 | { |
947 | lra_insn_recog_data_t data; | |
948 | int i, n, icode; | |
949 | rtx **locs; | |
950 | unsigned int uid = INSN_UID (insn); | |
951 | struct lra_static_insn_data *insn_static_data; | |
952 | ||
953 | check_and_expand_insn_recog_data (uid); | |
954 | if (DEBUG_INSN_P (insn)) | |
955 | icode = -1; | |
956 | else | |
957 | { | |
958 | icode = INSN_CODE (insn); | |
959 | if (icode < 0) | |
960 | /* It might be a new simple insn which is not recognized yet. */ | |
961 | INSN_CODE (insn) = icode = recog_memoized (insn); | |
962 | } | |
033bd26e | 963 | data = lra_insn_recog_data_pool.allocate (); |
55a2c322 VM |
964 | lra_insn_recog_data[uid] = data; |
965 | data->insn = insn; | |
7874b7c5 | 966 | data->used_insn_alternative = LRA_UNKNOWN_ALT; |
55a2c322 VM |
967 | data->icode = icode; |
968 | data->regs = NULL; | |
969 | if (DEBUG_INSN_P (insn)) | |
970 | { | |
55a2c322 VM |
971 | data->dup_loc = NULL; |
972 | data->arg_hard_regs = NULL; | |
9840b2fa | 973 | data->preferred_alternatives = ALL_ALTERNATIVES; |
96a95ac1 AO |
974 | if (DEBUG_BIND_INSN_P (insn)) |
975 | { | |
976 | data->insn_static_data = &debug_bind_static_data; | |
977 | data->operand_loc = XNEWVEC (rtx *, 1); | |
978 | data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); | |
979 | } | |
980 | else if (DEBUG_MARKER_INSN_P (insn)) | |
981 | { | |
982 | data->insn_static_data = &debug_marker_static_data; | |
983 | data->operand_loc = NULL; | |
984 | } | |
55a2c322 VM |
985 | return data; |
986 | } | |
987 | if (icode < 0) | |
988 | { | |
0c331756 | 989 | int nop, nalt; |
ef4bddc2 | 990 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
991 | const char *constraints[MAX_RECOG_OPERANDS]; |
992 | ||
993 | nop = asm_noperands (PATTERN (insn)); | |
994 | data->operand_loc = data->dup_loc = NULL; | |
0c331756 | 995 | nalt = 1; |
55a2c322 | 996 | if (nop < 0) |
91c5ee5b | 997 | { |
0e9e0a21 | 998 | /* It is a special insn like USE or CLOBBER. We should |
91c5ee5b VM |
999 | recognize any regular insn otherwise LRA can do nothing |
1000 | with this insn. */ | |
1001 | gcc_assert (GET_CODE (PATTERN (insn)) == USE | |
1002 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
1003 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
1004 | data->insn_static_data = insn_static_data | |
0c331756 | 1005 | = get_static_insn_data (-1, 0, 0, nalt); |
91c5ee5b | 1006 | } |
55a2c322 VM |
1007 | else |
1008 | { | |
1009 | /* expand_asm_operands makes sure there aren't too many | |
1010 | operands. */ | |
1011 | lra_assert (nop <= MAX_RECOG_OPERANDS); | |
1012 | if (nop != 0) | |
1013 | data->operand_loc = XNEWVEC (rtx *, nop); | |
1014 | /* Now get the operand values and constraints out of the | |
1015 | insn. */ | |
1016 | decode_asm_operands (PATTERN (insn), NULL, | |
1017 | data->operand_loc, | |
1018 | constraints, operand_mode, NULL); | |
55a2c322 | 1019 | if (nop > 0) |
ef874db6 ML |
1020 | for (const char *p =constraints[0]; *p; p++) |
1021 | nalt += *p == ','; | |
55a2c322 | 1022 | data->insn_static_data = insn_static_data |
0c331756 | 1023 | = get_static_insn_data (-1, nop, 0, nalt); |
55a2c322 VM |
1024 | for (i = 0; i < nop; i++) |
1025 | { | |
1026 | insn_static_data->operand[i].mode = operand_mode[i]; | |
1027 | insn_static_data->operand[i].constraint = constraints[i]; | |
1028 | insn_static_data->operand[i].strict_low = false; | |
1029 | insn_static_data->operand[i].is_operator = false; | |
1030 | insn_static_data->operand[i].is_address = false; | |
1031 | } | |
1032 | } | |
1033 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1034 | insn_static_data->operand[i].type | |
1035 | = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1036 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1037 | : OP_IN); | |
9840b2fa | 1038 | data->preferred_alternatives = ALL_ALTERNATIVES; |
0c331756 RS |
1039 | if (nop > 0) |
1040 | { | |
1041 | operand_alternative *op_alt = XCNEWVEC (operand_alternative, | |
1042 | nalt * nop); | |
998fd141 AO |
1043 | preprocess_constraints (nop, nalt, constraints, op_alt, |
1044 | data->operand_loc); | |
0c331756 RS |
1045 | setup_operand_alternative (data, op_alt); |
1046 | } | |
55a2c322 VM |
1047 | } |
1048 | else | |
1049 | { | |
1050 | insn_extract (insn); | |
1051 | data->insn_static_data = insn_static_data | |
1052 | = get_static_insn_data (icode, insn_data[icode].n_operands, | |
1053 | insn_data[icode].n_dups, | |
1054 | insn_data[icode].n_alternatives); | |
1055 | n = insn_static_data->n_operands; | |
1056 | if (n == 0) | |
1057 | locs = NULL; | |
1058 | else | |
1059 | { | |
1060 | locs = XNEWVEC (rtx *, n); | |
1061 | memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *)); | |
1062 | } | |
1063 | data->operand_loc = locs; | |
1064 | n = insn_static_data->n_dups; | |
1065 | if (n == 0) | |
1066 | locs = NULL; | |
1067 | else | |
1068 | { | |
1069 | locs = XNEWVEC (rtx *, n); | |
1070 | memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *)); | |
1071 | } | |
1072 | data->dup_loc = locs; | |
9840b2fa | 1073 | data->preferred_alternatives = get_preferred_alternatives (insn); |
0c331756 RS |
1074 | const operand_alternative *op_alt = preprocess_insn_constraints (icode); |
1075 | if (!insn_static_data->operand_alternative) | |
1076 | setup_operand_alternative (data, op_alt); | |
1077 | else if (op_alt != insn_static_data->operand_alternative) | |
1078 | insn_static_data->operand_alternative = op_alt; | |
55a2c322 VM |
1079 | } |
1080 | if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) | |
1081 | insn_static_data->hard_regs = NULL; | |
1082 | else | |
1083 | insn_static_data->hard_regs | |
561c58b4 | 1084 | = collect_non_operand_hard_regs (insn, &PATTERN (insn), data, |
17d184e5 | 1085 | NULL, OP_IN, false); |
55a2c322 VM |
1086 | data->arg_hard_regs = NULL; |
1087 | if (CALL_P (insn)) | |
1088 | { | |
9d86e84e | 1089 | bool use_p; |
55a2c322 VM |
1090 | rtx link; |
1091 | int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER]; | |
1092 | ||
1093 | n_hard_regs = 0; | |
1094 | /* Finding implicit hard register usage. We believe it will be | |
1095 | not changed whatever transformations are used. Call insns | |
1096 | are such example. */ | |
1097 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1098 | link != NULL_RTX; | |
1099 | link = XEXP (link, 1)) | |
9d86e84e VM |
1100 | if (((use_p = GET_CODE (XEXP (link, 0)) == USE) |
1101 | || GET_CODE (XEXP (link, 0)) == CLOBBER) | |
55a2c322 VM |
1102 | && REG_P (XEXP (XEXP (link, 0), 0))) |
1103 | { | |
1104 | regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
1105 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
1106 | /* It is an argument register. */ | |
dc8afb70 | 1107 | for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--) |
9d86e84e VM |
1108 | arg_hard_regs[n_hard_regs++] |
1109 | = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER); | |
55a2c322 | 1110 | } |
30dc1902 | 1111 | |
55a2c322 VM |
1112 | if (n_hard_regs != 0) |
1113 | { | |
1114 | arg_hard_regs[n_hard_regs++] = -1; | |
1115 | data->arg_hard_regs = XNEWVEC (int, n_hard_regs); | |
1116 | memcpy (data->arg_hard_regs, arg_hard_regs, | |
1117 | sizeof (int) * n_hard_regs); | |
1118 | } | |
1119 | } | |
1120 | /* Some output operand can be recognized only from the context not | |
1121 | from the constraints which are empty in this case. Call insn may | |
1122 | contain a hard register in set destination with empty constraint | |
1123 | and extract_insn treats them as an input. */ | |
1124 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1125 | { | |
1126 | int j; | |
1127 | rtx pat, set; | |
1128 | struct lra_operand_data *operand = &insn_static_data->operand[i]; | |
1129 | ||
1130 | /* ??? Should we treat 'X' the same way. It looks to me that | |
1131 | 'X' means anything and empty constraint means we do not | |
1132 | care. */ | |
1133 | if (operand->type != OP_IN || *operand->constraint != '\0' | |
1134 | || operand->is_operator) | |
1135 | continue; | |
1136 | pat = PATTERN (insn); | |
1137 | if (GET_CODE (pat) == SET) | |
1138 | { | |
1139 | if (data->operand_loc[i] != &SET_DEST (pat)) | |
1140 | continue; | |
1141 | } | |
1142 | else if (GET_CODE (pat) == PARALLEL) | |
1143 | { | |
1144 | for (j = XVECLEN (pat, 0) - 1; j >= 0; j--) | |
1145 | { | |
1146 | set = XVECEXP (PATTERN (insn), 0, j); | |
1147 | if (GET_CODE (set) == SET | |
1148 | && &SET_DEST (set) == data->operand_loc[i]) | |
1149 | break; | |
1150 | } | |
1151 | if (j < 0) | |
1152 | continue; | |
1153 | } | |
1154 | else | |
1155 | continue; | |
1156 | operand->type = OP_OUT; | |
1157 | } | |
1158 | return data; | |
1159 | } | |
1160 | ||
1161 | /* Return info about insn give by UID. The info should be already set | |
1162 | up. */ | |
1163 | static lra_insn_recog_data_t | |
1164 | get_insn_recog_data_by_uid (int uid) | |
1165 | { | |
1166 | lra_insn_recog_data_t data; | |
1167 | ||
1168 | data = lra_insn_recog_data[uid]; | |
1169 | lra_assert (data != NULL); | |
1170 | return data; | |
1171 | } | |
1172 | ||
1173 | /* Invalidate all info about insn given by its UID. */ | |
1174 | static void | |
1175 | invalidate_insn_recog_data (int uid) | |
1176 | { | |
1177 | lra_insn_recog_data_t data; | |
1178 | ||
1179 | data = lra_insn_recog_data[uid]; | |
1180 | lra_assert (data != NULL); | |
1181 | free_insn_recog_data (data); | |
1182 | lra_insn_recog_data[uid] = NULL; | |
1183 | } | |
1184 | ||
1185 | /* Update all the insn info about INSN. It is usually called when | |
1186 | something in the insn was changed. Return the updated info. */ | |
1187 | lra_insn_recog_data_t | |
cfa434f6 | 1188 | lra_update_insn_recog_data (rtx_insn *insn) |
55a2c322 VM |
1189 | { |
1190 | lra_insn_recog_data_t data; | |
1191 | int n; | |
1192 | unsigned int uid = INSN_UID (insn); | |
1193 | struct lra_static_insn_data *insn_static_data; | |
73ca989c | 1194 | poly_int64 sp_offset = 0; |
f4eafc30 | 1195 | |
55a2c322 VM |
1196 | check_and_expand_insn_recog_data (uid); |
1197 | if ((data = lra_insn_recog_data[uid]) != NULL | |
1198 | && data->icode != INSN_CODE (insn)) | |
1199 | { | |
8d49e7ef | 1200 | sp_offset = data->sp_offset; |
55a2c322 VM |
1201 | invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn)); |
1202 | invalidate_insn_recog_data (uid); | |
1203 | data = NULL; | |
1204 | } | |
1205 | if (data == NULL) | |
8d49e7ef VM |
1206 | { |
1207 | data = lra_get_insn_recog_data (insn); | |
1208 | /* Initiate or restore SP offset. */ | |
1209 | data->sp_offset = sp_offset; | |
1210 | return data; | |
1211 | } | |
55a2c322 | 1212 | insn_static_data = data->insn_static_data; |
7874b7c5 | 1213 | data->used_insn_alternative = LRA_UNKNOWN_ALT; |
55a2c322 VM |
1214 | if (DEBUG_INSN_P (insn)) |
1215 | return data; | |
1216 | if (data->icode < 0) | |
1217 | { | |
1218 | int nop; | |
ef4bddc2 | 1219 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
55a2c322 VM |
1220 | const char *constraints[MAX_RECOG_OPERANDS]; |
1221 | ||
1222 | nop = asm_noperands (PATTERN (insn)); | |
1223 | if (nop >= 0) | |
1224 | { | |
1225 | lra_assert (nop == data->insn_static_data->n_operands); | |
1226 | /* Now get the operand values and constraints out of the | |
1227 | insn. */ | |
1228 | decode_asm_operands (PATTERN (insn), NULL, | |
1229 | data->operand_loc, | |
1230 | constraints, operand_mode, NULL); | |
55a2c322 | 1231 | |
b2b29377 MM |
1232 | if (flag_checking) |
1233 | for (int i = 0; i < nop; i++) | |
55a2c322 VM |
1234 | lra_assert |
1235 | (insn_static_data->operand[i].mode == operand_mode[i] | |
1236 | && insn_static_data->operand[i].constraint == constraints[i] | |
1237 | && ! insn_static_data->operand[i].is_operator); | |
55a2c322 | 1238 | } |
55a2c322 | 1239 | |
b2b29377 MM |
1240 | if (flag_checking) |
1241 | for (int i = 0; i < insn_static_data->n_operands; i++) | |
55a2c322 VM |
1242 | lra_assert |
1243 | (insn_static_data->operand[i].type | |
1244 | == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1245 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1246 | : OP_IN)); | |
55a2c322 VM |
1247 | } |
1248 | else | |
1249 | { | |
1250 | insn_extract (insn); | |
1251 | n = insn_static_data->n_operands; | |
1252 | if (n != 0) | |
1253 | memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *)); | |
1254 | n = insn_static_data->n_dups; | |
1255 | if (n != 0) | |
1256 | memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *)); | |
9840b2fa | 1257 | lra_assert (check_bool_attrs (insn)); |
55a2c322 VM |
1258 | } |
1259 | return data; | |
1260 | } | |
1261 | ||
1262 | /* Set up that INSN is using alternative ALT now. */ | |
1263 | void | |
cfa434f6 | 1264 | lra_set_used_insn_alternative (rtx_insn *insn, int alt) |
55a2c322 VM |
1265 | { |
1266 | lra_insn_recog_data_t data; | |
1267 | ||
1268 | data = lra_get_insn_recog_data (insn); | |
1269 | data->used_insn_alternative = alt; | |
1270 | } | |
1271 | ||
1272 | /* Set up that insn with UID is using alternative ALT now. The insn | |
1273 | info should be already set up. */ | |
1274 | void | |
1275 | lra_set_used_insn_alternative_by_uid (int uid, int alt) | |
1276 | { | |
1277 | lra_insn_recog_data_t data; | |
1278 | ||
1279 | check_and_expand_insn_recog_data (uid); | |
1280 | data = lra_insn_recog_data[uid]; | |
1281 | lra_assert (data != NULL); | |
1282 | data->used_insn_alternative = alt; | |
1283 | } | |
1284 | ||
1285 | \f | |
1286 | ||
1287 | /* This page contains code dealing with common register info and | |
1288 | pseudo copies. */ | |
1289 | ||
1290 | /* The size of the following array. */ | |
1291 | static int reg_info_size; | |
1292 | /* Common info about each register. */ | |
99b1c316 | 1293 | class lra_reg *lra_reg_info; |
55a2c322 | 1294 | |
54178a01 TV |
1295 | HARD_REG_SET hard_regs_spilled_into; |
1296 | ||
55a2c322 VM |
1297 | /* Last register value. */ |
1298 | static int last_reg_value; | |
1299 | ||
1300 | /* Return new register value. */ | |
1301 | static int | |
1302 | get_new_reg_value (void) | |
1303 | { | |
1304 | return ++last_reg_value; | |
1305 | } | |
1306 | ||
55a2c322 | 1307 | /* Vec referring to pseudo copies. */ |
9771b263 | 1308 | static vec<lra_copy_t> copy_vec; |
55a2c322 VM |
1309 | |
1310 | /* Initialize I-th element of lra_reg_info. */ | |
1311 | static inline void | |
1312 | initialize_lra_reg_info_element (int i) | |
1313 | { | |
1314 | bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack); | |
1315 | #ifdef STACK_REGS | |
1316 | lra_reg_info[i].no_stack_p = false; | |
1317 | #endif | |
1318 | CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs); | |
1319 | lra_reg_info[i].preferred_hard_regno1 = -1; | |
1320 | lra_reg_info[i].preferred_hard_regno2 = -1; | |
1321 | lra_reg_info[i].preferred_hard_regno_profit1 = 0; | |
1322 | lra_reg_info[i].preferred_hard_regno_profit2 = 0; | |
b28ece32 | 1323 | lra_reg_info[i].biggest_mode = VOIDmode; |
55a2c322 VM |
1324 | lra_reg_info[i].live_ranges = NULL; |
1325 | lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0; | |
1326 | lra_reg_info[i].last_reload = 0; | |
8a8330b7 | 1327 | lra_reg_info[i].restore_rtx = NULL_RTX; |
55a2c322 | 1328 | lra_reg_info[i].val = get_new_reg_value (); |
d70a81dd | 1329 | lra_reg_info[i].offset = 0; |
55a2c322 VM |
1330 | lra_reg_info[i].copies = NULL; |
1331 | } | |
1332 | ||
1333 | /* Initialize common reg info and copies. */ | |
1334 | static void | |
1335 | init_reg_info (void) | |
1336 | { | |
1337 | int i; | |
1338 | ||
1339 | last_reg_value = 0; | |
1340 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
99b1c316 | 1341 | lra_reg_info = XNEWVEC (class lra_reg, reg_info_size); |
55a2c322 VM |
1342 | for (i = 0; i < reg_info_size; i++) |
1343 | initialize_lra_reg_info_element (i); | |
ff569744 | 1344 | copy_vec.truncate (0); |
54178a01 | 1345 | CLEAR_HARD_REG_SET (hard_regs_spilled_into); |
55a2c322 VM |
1346 | } |
1347 | ||
1348 | ||
1349 | /* Finish common reg info and copies. */ | |
1350 | static void | |
1351 | finish_reg_info (void) | |
1352 | { | |
1353 | int i; | |
1354 | ||
1355 | for (i = 0; i < reg_info_size; i++) | |
1356 | bitmap_clear (&lra_reg_info[i].insn_bitmap); | |
1357 | free (lra_reg_info); | |
1358 | reg_info_size = 0; | |
55a2c322 VM |
1359 | } |
1360 | ||
1361 | /* Expand common reg info if it is necessary. */ | |
1362 | static void | |
1363 | expand_reg_info (void) | |
1364 | { | |
1365 | int i, old = reg_info_size; | |
1366 | ||
1367 | if (reg_info_size > max_reg_num ()) | |
1368 | return; | |
1369 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
99b1c316 | 1370 | lra_reg_info = XRESIZEVEC (class lra_reg, lra_reg_info, reg_info_size); |
55a2c322 VM |
1371 | for (i = old; i < reg_info_size; i++) |
1372 | initialize_lra_reg_info_element (i); | |
1373 | } | |
1374 | ||
1375 | /* Free all copies. */ | |
1376 | void | |
1377 | lra_free_copies (void) | |
1378 | { | |
1379 | lra_copy_t cp; | |
1380 | ||
9771b263 | 1381 | while (copy_vec.length () != 0) |
55a2c322 | 1382 | { |
9771b263 | 1383 | cp = copy_vec.pop (); |
55a2c322 | 1384 | lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL; |
fb0b2914 | 1385 | lra_copy_pool.remove (cp); |
55a2c322 VM |
1386 | } |
1387 | } | |
1388 | ||
1389 | /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution | |
1390 | frequency is FREQ. */ | |
1391 | void | |
1392 | lra_create_copy (int regno1, int regno2, int freq) | |
1393 | { | |
1394 | bool regno1_dest_p; | |
1395 | lra_copy_t cp; | |
1396 | ||
1397 | lra_assert (regno1 != regno2); | |
1398 | regno1_dest_p = true; | |
1399 | if (regno1 > regno2) | |
1400 | { | |
6b4db501 | 1401 | std::swap (regno1, regno2); |
55a2c322 | 1402 | regno1_dest_p = false; |
55a2c322 | 1403 | } |
fb0b2914 | 1404 | cp = lra_copy_pool.allocate (); |
9771b263 | 1405 | copy_vec.safe_push (cp); |
55a2c322 VM |
1406 | cp->regno1_dest_p = regno1_dest_p; |
1407 | cp->freq = freq; | |
1408 | cp->regno1 = regno1; | |
1409 | cp->regno2 = regno2; | |
1410 | cp->regno1_next = lra_reg_info[regno1].copies; | |
1411 | lra_reg_info[regno1].copies = cp; | |
1412 | cp->regno2_next = lra_reg_info[regno2].copies; | |
1413 | lra_reg_info[regno2].copies = cp; | |
1414 | if (lra_dump_file != NULL) | |
1415 | fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n", | |
1416 | regno1, regno1_dest_p ? "<-" : "->", regno2, freq); | |
1417 | } | |
1418 | ||
1419 | /* Return N-th (0, 1, ...) copy. If there is no copy, return | |
1420 | NULL. */ | |
1421 | lra_copy_t | |
1422 | lra_get_copy (int n) | |
1423 | { | |
9771b263 | 1424 | if (n >= (int) copy_vec.length ()) |
55a2c322 | 1425 | return NULL; |
9771b263 | 1426 | return copy_vec[n]; |
55a2c322 VM |
1427 | } |
1428 | ||
1429 | \f | |
1430 | ||
1431 | /* This page contains code dealing with info about registers in | |
1432 | insns. */ | |
1433 | ||
a25f3e8e RS |
1434 | /* Process X of INSN recursively and add info (operand type is given |
1435 | by TYPE) about registers in X to the insn DATA. If X can be early | |
1436 | clobbered, alternatives in which it can be early clobbered are given | |
1437 | by EARLY_CLOBBER_ALTS. */ | |
55a2c322 | 1438 | static void |
561c58b4 | 1439 | add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, |
a25f3e8e | 1440 | rtx_insn *insn, enum op_type type, |
584898ee | 1441 | alternative_mask early_clobber_alts) |
55a2c322 VM |
1442 | { |
1443 | int i, j, regno; | |
1444 | bool subreg_p; | |
ef4bddc2 | 1445 | machine_mode mode; |
55a2c322 VM |
1446 | const char *fmt; |
1447 | enum rtx_code code; | |
1448 | struct lra_insn_reg *curr; | |
1449 | ||
1450 | code = GET_CODE (x); | |
1451 | mode = GET_MODE (x); | |
1452 | subreg_p = false; | |
1453 | if (GET_CODE (x) == SUBREG) | |
1454 | { | |
bd5a2c67 | 1455 | mode = wider_subreg_mode (x); |
9eaf97d6 RS |
1456 | if (read_modify_subreg_p (x)) |
1457 | subreg_p = true; | |
55a2c322 VM |
1458 | x = SUBREG_REG (x); |
1459 | code = GET_CODE (x); | |
55a2c322 VM |
1460 | } |
1461 | if (REG_P (x)) | |
1462 | { | |
1463 | regno = REGNO (x); | |
d9cf932c VM |
1464 | /* Process all regs even unallocatable ones as we need info about |
1465 | all regs for rematerialization pass. */ | |
55a2c322 | 1466 | expand_reg_info (); |
561c58b4 | 1467 | if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn))) |
55a2c322 | 1468 | { |
c34c46dd | 1469 | data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
17d184e5 | 1470 | early_clobber_alts, data->regs); |
55a2c322 VM |
1471 | return; |
1472 | } | |
1473 | else | |
1474 | { | |
1475 | for (curr = data->regs; curr != NULL; curr = curr->next) | |
1476 | if (curr->regno == regno) | |
1477 | { | |
1478 | if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) | |
67914693 | 1479 | /* The info cannot be integrated into the found |
55a2c322 | 1480 | structure. */ |
c34c46dd | 1481 | data->regs = new_insn_reg (data->insn, regno, type, mode, |
a25f3e8e | 1482 | subreg_p, early_clobber_alts, |
17d184e5 | 1483 | data->regs); |
55a2c322 VM |
1484 | else |
1485 | { | |
1486 | if (curr->type != type) | |
1487 | curr->type = OP_INOUT; | |
584898ee | 1488 | curr->early_clobber_alts |= early_clobber_alts; |
55a2c322 VM |
1489 | } |
1490 | return; | |
1491 | } | |
1492 | gcc_unreachable (); | |
1493 | } | |
1494 | } | |
1495 | ||
1496 | switch (code) | |
1497 | { | |
1498 | case SET: | |
a25f3e8e RS |
1499 | add_regs_to_insn_regno_info (data, SET_DEST (x), insn, OP_OUT, 0); |
1500 | add_regs_to_insn_regno_info (data, SET_SRC (x), insn, OP_IN, 0); | |
55a2c322 VM |
1501 | break; |
1502 | case CLOBBER: | |
75214935 VM |
1503 | /* We treat clobber of non-operand hard registers as early |
1504 | clobber. */ | |
1505 | add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_OUT, | |
a25f3e8e | 1506 | ALL_ALTERNATIVES); |
75214935 | 1507 | break; |
55a2c322 | 1508 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: |
a25f3e8e | 1509 | add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, 0); |
55a2c322 VM |
1510 | break; |
1511 | case PRE_MODIFY: case POST_MODIFY: | |
a25f3e8e RS |
1512 | add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, 0); |
1513 | add_regs_to_insn_regno_info (data, XEXP (x, 1), insn, OP_IN, 0); | |
55a2c322 VM |
1514 | break; |
1515 | default: | |
1516 | if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) | |
1517 | /* Some targets place small structures in registers for return | |
1518 | values of functions, and those registers are wrapped in | |
1519 | PARALLEL that we may see as the destination of a SET. Here | |
1520 | is an example: | |
1521 | ||
1522 | (call_insn 13 12 14 2 (set (parallel:BLK [ | |
1523 | (expr_list:REG_DEP_TRUE (reg:DI 0 ax) | |
1524 | (const_int 0 [0])) | |
1525 | (expr_list:REG_DEP_TRUE (reg:DI 1 dx) | |
1526 | (const_int 8 [0x8])) | |
1527 | ]) | |
1528 | (call (mem:QI (symbol_ref:DI (... */ | |
1529 | type = OP_IN; | |
1530 | fmt = GET_RTX_FORMAT (code); | |
1531 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1532 | { | |
1533 | if (fmt[i] == 'e') | |
a25f3e8e | 1534 | add_regs_to_insn_regno_info (data, XEXP (x, i), insn, type, 0); |
55a2c322 VM |
1535 | else if (fmt[i] == 'E') |
1536 | { | |
1537 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
561c58b4 | 1538 | add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), insn, |
a25f3e8e | 1539 | type, 0); |
55a2c322 VM |
1540 | } |
1541 | } | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | /* Return execution frequency of INSN. */ | |
1546 | static int | |
cfa434f6 | 1547 | get_insn_freq (rtx_insn *insn) |
55a2c322 | 1548 | { |
39718607 | 1549 | basic_block bb = BLOCK_FOR_INSN (insn); |
55a2c322 | 1550 | |
39718607 SB |
1551 | gcc_checking_assert (bb != NULL); |
1552 | return REG_FREQ_FROM_BB (bb); | |
55a2c322 VM |
1553 | } |
1554 | ||
1555 | /* Invalidate all reg info of INSN with DATA and execution frequency | |
1556 | FREQ. Update common info about the invalidated registers. */ | |
1557 | static void | |
cfa434f6 | 1558 | invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn, |
55a2c322 VM |
1559 | int freq) |
1560 | { | |
1561 | int uid; | |
1562 | bool debug_p; | |
1563 | unsigned int i; | |
1564 | struct lra_insn_reg *ir, *next_ir; | |
1565 | ||
1566 | uid = INSN_UID (insn); | |
1567 | debug_p = DEBUG_INSN_P (insn); | |
1568 | for (ir = data->regs; ir != NULL; ir = next_ir) | |
1569 | { | |
1570 | i = ir->regno; | |
1571 | next_ir = ir->next; | |
fb0b2914 | 1572 | lra_insn_reg_pool.remove (ir); |
55a2c322 VM |
1573 | bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid); |
1574 | if (i >= FIRST_PSEUDO_REGISTER && ! debug_p) | |
1575 | { | |
1576 | lra_reg_info[i].nrefs--; | |
1577 | lra_reg_info[i].freq -= freq; | |
1578 | lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0); | |
1579 | } | |
1580 | } | |
1581 | data->regs = NULL; | |
1582 | } | |
1583 | ||
1584 | /* Invalidate all reg info of INSN. Update common info about the | |
1585 | invalidated registers. */ | |
1586 | void | |
cfa434f6 | 1587 | lra_invalidate_insn_regno_info (rtx_insn *insn) |
55a2c322 VM |
1588 | { |
1589 | invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn, | |
1590 | get_insn_freq (insn)); | |
1591 | } | |
1592 | ||
1593 | /* Update common reg info from reg info of insn given by its DATA and | |
1594 | execution frequency FREQ. */ | |
1595 | static void | |
1596 | setup_insn_reg_info (lra_insn_recog_data_t data, int freq) | |
1597 | { | |
1598 | unsigned int i; | |
1599 | struct lra_insn_reg *ir; | |
1600 | ||
1601 | for (ir = data->regs; ir != NULL; ir = ir->next) | |
1602 | if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER) | |
1603 | { | |
1604 | lra_reg_info[i].nrefs++; | |
1605 | lra_reg_info[i].freq += freq; | |
1606 | } | |
1607 | } | |
1608 | ||
1609 | /* Set up insn reg info of INSN. Update common reg info from reg info | |
1610 | of INSN. */ | |
1611 | void | |
cfa434f6 | 1612 | lra_update_insn_regno_info (rtx_insn *insn) |
55a2c322 | 1613 | { |
561c58b4 | 1614 | int i, freq; |
55a2c322 VM |
1615 | lra_insn_recog_data_t data; |
1616 | struct lra_static_insn_data *static_data; | |
1617 | enum rtx_code code; | |
05f23918 VM |
1618 | rtx link; |
1619 | ||
55a2c322 VM |
1620 | if (! INSN_P (insn)) |
1621 | return; | |
1622 | data = lra_get_insn_recog_data (insn); | |
1623 | static_data = data->insn_static_data; | |
96a95ac1 | 1624 | freq = NONDEBUG_INSN_P (insn) ? get_insn_freq (insn) : 0; |
55a2c322 | 1625 | invalidate_insn_data_regno_info (data, insn, freq); |
55a2c322 | 1626 | for (i = static_data->n_operands - 1; i >= 0; i--) |
561c58b4 | 1627 | add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn, |
55a2c322 | 1628 | static_data->operand[i].type, |
584898ee | 1629 | static_data->operand[i].early_clobber_alts); |
55a2c322 | 1630 | if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) |
561c58b4 | 1631 | add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), insn, |
a25f3e8e | 1632 | code == USE ? OP_IN : OP_OUT, 0); |
05f23918 VM |
1633 | if (CALL_P (insn)) |
1634 | /* On some targets call insns can refer to pseudos in memory in | |
1635 | CALL_INSN_FUNCTION_USAGE list. Process them in order to | |
1636 | consider their occurrences in calls for different | |
1637 | transformations (e.g. inheritance) with given pseudos. */ | |
1638 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1639 | link != NULL_RTX; | |
1640 | link = XEXP (link, 1)) | |
30dc1902 AH |
1641 | { |
1642 | code = GET_CODE (XEXP (link, 0)); | |
30dc1902 AH |
1643 | if ((code == USE || code == CLOBBER) |
1644 | && MEM_P (XEXP (XEXP (link, 0), 0))) | |
1645 | add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), insn, | |
a25f3e8e | 1646 | code == USE ? OP_IN : OP_OUT, 0); |
30dc1902 | 1647 | } |
55a2c322 VM |
1648 | if (NONDEBUG_INSN_P (insn)) |
1649 | setup_insn_reg_info (data, freq); | |
1650 | } | |
1651 | ||
1652 | /* Return reg info of insn given by it UID. */ | |
1653 | struct lra_insn_reg * | |
1654 | lra_get_insn_regs (int uid) | |
1655 | { | |
1656 | lra_insn_recog_data_t data; | |
1657 | ||
1658 | data = get_insn_recog_data_by_uid (uid); | |
1659 | return data->regs; | |
1660 | } | |
1661 | ||
1662 | \f | |
1663 | ||
8a8330b7 VM |
1664 | /* Recursive hash function for RTL X. */ |
1665 | hashval_t | |
1666 | lra_rtx_hash (rtx x) | |
1667 | { | |
1668 | int i, j; | |
1669 | enum rtx_code code; | |
1670 | const char *fmt; | |
1671 | hashval_t val = 0; | |
1672 | ||
1673 | if (x == 0) | |
1674 | return val; | |
1675 | ||
1676 | code = GET_CODE (x); | |
1677 | val += (int) code + 4095; | |
1678 | ||
1679 | /* Some RTL can be compared nonrecursively. */ | |
1680 | switch (code) | |
1681 | { | |
1682 | case REG: | |
1683 | return val + REGNO (x); | |
1684 | ||
1685 | case LABEL_REF: | |
1686 | return iterative_hash_object (XEXP (x, 0), val); | |
1687 | ||
1688 | case SYMBOL_REF: | |
1689 | return iterative_hash_object (XSTR (x, 0), val); | |
1690 | ||
1691 | case SCRATCH: | |
1692 | case CONST_DOUBLE: | |
8a8330b7 VM |
1693 | case CONST_VECTOR: |
1694 | return val; | |
1695 | ||
f4caead0 RB |
1696 | case CONST_INT: |
1697 | return val + UINTVAL (x); | |
1698 | ||
8a8330b7 VM |
1699 | default: |
1700 | break; | |
1701 | } | |
1702 | ||
1703 | /* Hash the elements. */ | |
1704 | fmt = GET_RTX_FORMAT (code); | |
1705 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1706 | { | |
1707 | switch (fmt[i]) | |
1708 | { | |
1709 | case 'w': | |
1710 | val += XWINT (x, i); | |
1711 | break; | |
1712 | ||
1713 | case 'n': | |
1714 | case 'i': | |
1715 | val += XINT (x, i); | |
1716 | break; | |
1717 | ||
1718 | case 'V': | |
1719 | case 'E': | |
1720 | val += XVECLEN (x, i); | |
1721 | ||
1722 | for (j = 0; j < XVECLEN (x, i); j++) | |
1723 | val += lra_rtx_hash (XVECEXP (x, i, j)); | |
1724 | break; | |
1725 | ||
1726 | case 'e': | |
1727 | val += lra_rtx_hash (XEXP (x, i)); | |
1728 | break; | |
1729 | ||
1730 | case 'S': | |
1731 | case 's': | |
1732 | val += htab_hash_string (XSTR (x, i)); | |
1733 | break; | |
1734 | ||
1735 | case 'u': | |
1736 | case '0': | |
1737 | case 't': | |
1738 | break; | |
1739 | ||
1740 | /* It is believed that rtx's at this level will never | |
1741 | contain anything but integers and other rtx's, except for | |
1742 | within LABEL_REFs and SYMBOL_REFs. */ | |
1743 | default: | |
1744 | abort (); | |
1745 | } | |
1746 | } | |
1747 | return val; | |
1748 | } | |
1749 | ||
1750 | \f | |
1751 | ||
55a2c322 VM |
1752 | /* This page contains code dealing with stack of the insns which |
1753 | should be processed by the next constraint pass. */ | |
1754 | ||
1755 | /* Bitmap used to put an insn on the stack only in one exemplar. */ | |
1756 | static sbitmap lra_constraint_insn_stack_bitmap; | |
1757 | ||
1758 | /* The stack itself. */ | |
cfa434f6 | 1759 | vec<rtx_insn *> lra_constraint_insn_stack; |
55a2c322 VM |
1760 | |
1761 | /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg | |
1762 | info for INSN, otherwise only update it if INSN is not already on the | |
1763 | stack. */ | |
1764 | static inline void | |
cfa434f6 | 1765 | lra_push_insn_1 (rtx_insn *insn, bool always_update) |
55a2c322 VM |
1766 | { |
1767 | unsigned int uid = INSN_UID (insn); | |
1768 | if (always_update) | |
1769 | lra_update_insn_regno_info (insn); | |
1770 | if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)) | |
1771 | lra_constraint_insn_stack_bitmap = | |
1772 | sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0); | |
d7c028c0 | 1773 | if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid)) |
55a2c322 | 1774 | return; |
d7c028c0 | 1775 | bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid); |
55a2c322 VM |
1776 | if (! always_update) |
1777 | lra_update_insn_regno_info (insn); | |
9771b263 | 1778 | lra_constraint_insn_stack.safe_push (insn); |
55a2c322 VM |
1779 | } |
1780 | ||
1781 | /* Put INSN on the stack. */ | |
1782 | void | |
cfa434f6 | 1783 | lra_push_insn (rtx_insn *insn) |
55a2c322 VM |
1784 | { |
1785 | lra_push_insn_1 (insn, false); | |
1786 | } | |
1787 | ||
1788 | /* Put INSN on the stack and update its reg info. */ | |
1789 | void | |
cfa434f6 | 1790 | lra_push_insn_and_update_insn_regno_info (rtx_insn *insn) |
55a2c322 VM |
1791 | { |
1792 | lra_push_insn_1 (insn, true); | |
1793 | } | |
1794 | ||
1795 | /* Put insn with UID on the stack. */ | |
1796 | void | |
1797 | lra_push_insn_by_uid (unsigned int uid) | |
1798 | { | |
1799 | lra_push_insn (lra_insn_recog_data[uid]->insn); | |
1800 | } | |
1801 | ||
1802 | /* Take the last-inserted insns off the stack and return it. */ | |
cfa434f6 | 1803 | rtx_insn * |
55a2c322 VM |
1804 | lra_pop_insn (void) |
1805 | { | |
cfa434f6 | 1806 | rtx_insn *insn = lra_constraint_insn_stack.pop (); |
d7c028c0 | 1807 | bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn)); |
55a2c322 VM |
1808 | return insn; |
1809 | } | |
1810 | ||
1811 | /* Return the current size of the insn stack. */ | |
1812 | unsigned int | |
1813 | lra_insn_stack_length (void) | |
1814 | { | |
9771b263 | 1815 | return lra_constraint_insn_stack.length (); |
55a2c322 VM |
1816 | } |
1817 | ||
1818 | /* Push insns FROM to TO (excluding it) going in reverse order. */ | |
1819 | static void | |
cfa434f6 | 1820 | push_insns (rtx_insn *from, rtx_insn *to) |
55a2c322 | 1821 | { |
cfa434f6 | 1822 | rtx_insn *insn; |
55a2c322 VM |
1823 | |
1824 | if (from == NULL_RTX) | |
1825 | return; | |
1826 | for (insn = from; insn != to; insn = PREV_INSN (insn)) | |
1827 | if (INSN_P (insn)) | |
1828 | lra_push_insn (insn); | |
1829 | } | |
1830 | ||
8d49e7ef VM |
1831 | /* Set up sp offset for insn in range [FROM, LAST]. The offset is |
1832 | taken from the next BB insn after LAST or zero if there in such | |
1833 | insn. */ | |
1834 | static void | |
cfa434f6 | 1835 | setup_sp_offset (rtx_insn *from, rtx_insn *last) |
8d49e7ef | 1836 | { |
f40dd646 | 1837 | rtx_insn *before = next_nonnote_nondebug_insn_bb (last); |
73ca989c RS |
1838 | poly_int64 offset = (before == NULL_RTX || ! INSN_P (before) |
1839 | ? 0 : lra_get_insn_recog_data (before)->sp_offset); | |
8d49e7ef | 1840 | |
cfa434f6 | 1841 | for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) |
8d49e7ef VM |
1842 | lra_get_insn_recog_data (insn)->sp_offset = offset; |
1843 | } | |
1844 | ||
55a2c322 VM |
1845 | /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the |
1846 | insns onto the stack. Print about emitting the insns with | |
1847 | TITLE. */ | |
1848 | void | |
cfa434f6 DM |
1849 | lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after, |
1850 | const char *title) | |
55a2c322 | 1851 | { |
cfa434f6 | 1852 | rtx_insn *last; |
55a2c322 | 1853 | |
8d49e7ef VM |
1854 | if (before == NULL_RTX && after == NULL_RTX) |
1855 | return; | |
1856 | if (lra_dump_file != NULL) | |
55a2c322 | 1857 | { |
cfbeaedf | 1858 | dump_insn_slim (lra_dump_file, insn); |
55a2c322 VM |
1859 | if (before != NULL_RTX) |
1860 | { | |
1861 | fprintf (lra_dump_file," %s before:\n", title); | |
dc01c3d1 | 1862 | dump_rtl_slim (lra_dump_file, before, NULL, -1, 0); |
55a2c322 VM |
1863 | } |
1864 | if (after != NULL_RTX) | |
1865 | { | |
1866 | fprintf (lra_dump_file, " %s after:\n", title); | |
dc01c3d1 | 1867 | dump_rtl_slim (lra_dump_file, after, NULL, -1, 0); |
55a2c322 VM |
1868 | } |
1869 | fprintf (lra_dump_file, "\n"); | |
1870 | } | |
1871 | if (before != NULL_RTX) | |
1872 | { | |
de4fcb99 JJ |
1873 | if (cfun->can_throw_non_call_exceptions) |
1874 | copy_reg_eh_region_note_forward (insn, before, NULL); | |
55a2c322 VM |
1875 | emit_insn_before (before, insn); |
1876 | push_insns (PREV_INSN (insn), PREV_INSN (before)); | |
8d49e7ef | 1877 | setup_sp_offset (before, PREV_INSN (insn)); |
55a2c322 VM |
1878 | } |
1879 | if (after != NULL_RTX) | |
1880 | { | |
de4fcb99 JJ |
1881 | if (cfun->can_throw_non_call_exceptions) |
1882 | copy_reg_eh_region_note_forward (insn, after, NULL); | |
55a2c322 VM |
1883 | for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) |
1884 | ; | |
1885 | emit_insn_after (after, insn); | |
1886 | push_insns (last, insn); | |
8d49e7ef | 1887 | setup_sp_offset (after, last); |
55a2c322 | 1888 | } |
de4fcb99 JJ |
1889 | if (cfun->can_throw_non_call_exceptions) |
1890 | { | |
1891 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
1892 | if (note && !insn_could_throw_p (insn)) | |
1893 | remove_note (insn, note); | |
1894 | } | |
55a2c322 | 1895 | } |
55a2c322 VM |
1896 | \f |
1897 | ||
8160cd3e | 1898 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
ef87312e | 1899 | register NEW_REG. Try to simplify subreg of constant if SUBREG_P. |
33006d53 JJ |
1900 | DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any |
1901 | change was made. */ | |
8160cd3e | 1902 | bool |
33006d53 JJ |
1903 | lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p, |
1904 | bool debug_p) | |
8160cd3e VM |
1905 | { |
1906 | rtx x = *loc; | |
1907 | bool result = false; | |
1908 | enum rtx_code code; | |
1909 | const char *fmt; | |
1910 | int i, j; | |
1911 | ||
1912 | if (x == NULL_RTX) | |
1913 | return false; | |
1914 | ||
1915 | code = GET_CODE (x); | |
ef87312e | 1916 | if (code == SUBREG && subreg_p) |
8160cd3e | 1917 | { |
ef87312e VM |
1918 | rtx subst, inner = SUBREG_REG (x); |
1919 | /* Transform subreg of constant while we still have inner mode | |
1920 | of the subreg. The subreg internal should not be an insn | |
1921 | operand. */ | |
1922 | if (REG_P (inner) && (int) REGNO (inner) == old_regno | |
1923 | && CONSTANT_P (new_reg) | |
1924 | && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner), | |
1925 | SUBREG_BYTE (x))) != NULL_RTX) | |
1926 | { | |
1927 | *loc = subst; | |
1928 | return true; | |
1929 | } | |
1930 | ||
1931 | } | |
1932 | else if (code == REG && (int) REGNO (x) == old_regno) | |
1933 | { | |
1934 | machine_mode mode = GET_MODE (x); | |
8160cd3e VM |
1935 | machine_mode inner_mode = GET_MODE (new_reg); |
1936 | ||
eef7b18c | 1937 | if (mode != inner_mode |
59193b1b | 1938 | && ! (CONST_SCALAR_INT_P (new_reg) && SCALAR_INT_MODE_P (mode))) |
8160cd3e | 1939 | { |
33006d53 JJ |
1940 | poly_uint64 offset = 0; |
1941 | if (partial_subreg_p (mode, inner_mode) | |
1942 | && SCALAR_INT_MODE_P (inner_mode)) | |
1943 | offset = subreg_lowpart_offset (mode, inner_mode); | |
1944 | if (debug_p) | |
1945 | new_reg = gen_rtx_raw_SUBREG (mode, new_reg, offset); | |
8160cd3e | 1946 | else |
33006d53 | 1947 | new_reg = gen_rtx_SUBREG (mode, new_reg, offset); |
8160cd3e VM |
1948 | } |
1949 | *loc = new_reg; | |
1950 | return true; | |
1951 | } | |
1952 | ||
1953 | /* Scan all the operand sub-expressions. */ | |
1954 | fmt = GET_RTX_FORMAT (code); | |
1955 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1956 | { | |
1957 | if (fmt[i] == 'e') | |
1958 | { | |
ef87312e | 1959 | if (lra_substitute_pseudo (&XEXP (x, i), old_regno, |
33006d53 | 1960 | new_reg, subreg_p, debug_p)) |
8160cd3e VM |
1961 | result = true; |
1962 | } | |
1963 | else if (fmt[i] == 'E') | |
1964 | { | |
1965 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
ef87312e | 1966 | if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno, |
33006d53 | 1967 | new_reg, subreg_p, debug_p)) |
8160cd3e VM |
1968 | result = true; |
1969 | } | |
1970 | } | |
1971 | return result; | |
1972 | } | |
1973 | ||
ef87312e VM |
1974 | /* Call lra_substitute_pseudo within an insn. Try to simplify subreg |
1975 | of constant if SUBREG_P. This won't update the insn ptr, just the | |
1976 | contents of the insn. */ | |
8160cd3e | 1977 | bool |
ef87312e VM |
1978 | lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno, |
1979 | rtx new_reg, bool subreg_p) | |
8160cd3e VM |
1980 | { |
1981 | rtx loc = insn; | |
33006d53 JJ |
1982 | return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p, |
1983 | DEBUG_INSN_P (insn)); | |
8160cd3e VM |
1984 | } |
1985 | ||
1986 | \f | |
1987 | ||
55a2c322 VM |
1988 | /* This page contains code dealing with scratches (changing them onto |
1989 | pseudos and restoring them from the pseudos). | |
1990 | ||
1991 | We change scratches into pseudos at the beginning of LRA to | |
1992 | simplify dealing with them (conflicts, hard register assignments). | |
1993 | ||
1994 | If the pseudo denoting scratch was spilled it means that we do need | |
1995 | a hard register for it. Such pseudos are transformed back to | |
1996 | scratches at the end of LRA. */ | |
1997 | ||
1998 | /* Description of location of a former scratch operand. */ | |
926cd61f | 1999 | struct sloc |
55a2c322 | 2000 | { |
cfa434f6 | 2001 | rtx_insn *insn; /* Insn where the scratch was. */ |
55a2c322 | 2002 | int nop; /* Number of the operand which was a scratch. */ |
f961ec70 | 2003 | int icode; /* Original icode from which scratch was removed. */ |
55a2c322 VM |
2004 | }; |
2005 | ||
926cd61f | 2006 | typedef struct sloc *sloc_t; |
55a2c322 | 2007 | |
55a2c322 | 2008 | /* Locations of the former scratches. */ |
9771b263 | 2009 | static vec<sloc_t> scratches; |
55a2c322 VM |
2010 | |
2011 | /* Bitmap of scratch regnos. */ | |
2012 | static bitmap_head scratch_bitmap; | |
2013 | ||
2014 | /* Bitmap of scratch operands. */ | |
2015 | static bitmap_head scratch_operand_bitmap; | |
2016 | ||
2017 | /* Return true if pseudo REGNO is made of SCRATCH. */ | |
2018 | bool | |
2019 | lra_former_scratch_p (int regno) | |
2020 | { | |
2021 | return bitmap_bit_p (&scratch_bitmap, regno); | |
2022 | } | |
2023 | ||
2024 | /* Return true if the operand NOP of INSN is a former scratch. */ | |
2025 | bool | |
cfa434f6 | 2026 | lra_former_scratch_operand_p (rtx_insn *insn, int nop) |
55a2c322 VM |
2027 | { |
2028 | return bitmap_bit_p (&scratch_operand_bitmap, | |
2029 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0; | |
2030 | } | |
2031 | ||
892927b7 VM |
2032 | /* Register operand NOP in INSN as a former scratch. It will be |
2033 | changed to scratch back, if it is necessary, at the LRA end. */ | |
2034 | void | |
f961ec70 | 2035 | lra_register_new_scratch_op (rtx_insn *insn, int nop, int icode) |
892927b7 VM |
2036 | { |
2037 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); | |
2038 | rtx op = *id->operand_loc[nop]; | |
2039 | sloc_t loc = XNEW (struct sloc); | |
2040 | lra_assert (REG_P (op)); | |
2041 | loc->insn = insn; | |
2042 | loc->nop = nop; | |
f961ec70 | 2043 | loc->icode = icode; |
892927b7 VM |
2044 | scratches.safe_push (loc); |
2045 | bitmap_set_bit (&scratch_bitmap, REGNO (op)); | |
2046 | bitmap_set_bit (&scratch_operand_bitmap, | |
2047 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop); | |
2048 | add_reg_note (insn, REG_UNUSED, op); | |
2049 | } | |
2050 | ||
2713e5db | 2051 | /* Change INSN's scratches into pseudos and save their location. */ |
55a2c322 | 2052 | static void |
2713e5db | 2053 | remove_scratches_1 (rtx_insn *insn) |
55a2c322 VM |
2054 | { |
2055 | int i; | |
2056 | bool insn_changed_p; | |
cfa434f6 | 2057 | rtx reg; |
55a2c322 VM |
2058 | lra_insn_recog_data_t id; |
2059 | struct lra_static_insn_data *static_id; | |
2060 | ||
2713e5db PB |
2061 | id = lra_get_insn_recog_data (insn); |
2062 | static_id = id->insn_static_data; | |
2063 | insn_changed_p = false; | |
2064 | for (i = 0; i < static_id->n_operands; i++) | |
2065 | if (GET_CODE (*id->operand_loc[i]) == SCRATCH | |
2066 | && GET_MODE (*id->operand_loc[i]) != VOIDmode) | |
2067 | { | |
2068 | insn_changed_p = true; | |
2069 | *id->operand_loc[i] = reg | |
2070 | = lra_create_new_reg (static_id->operand[i].mode, | |
2071 | *id->operand_loc[i], ALL_REGS, NULL); | |
2072 | lra_register_new_scratch_op (insn, i, id->icode); | |
2073 | if (lra_dump_file != NULL) | |
2074 | fprintf (lra_dump_file, | |
2075 | "Removing SCRATCH in insn #%u (nop %d)\n", | |
2076 | INSN_UID (insn), i); | |
2077 | } | |
2078 | if (insn_changed_p) | |
2079 | /* Because we might use DF right after caller-saves sub-pass | |
2080 | we need to keep DF info up to date. */ | |
2081 | df_insn_rescan (insn); | |
2082 | } | |
2083 | ||
2084 | /* Change scratches into pseudos and save their location. */ | |
2085 | static void | |
2086 | remove_scratches (void) | |
2087 | { | |
2088 | basic_block bb; | |
2089 | rtx_insn *insn; | |
2090 | ||
9771b263 | 2091 | scratches.create (get_max_uid ()); |
55a2c322 VM |
2092 | bitmap_initialize (&scratch_bitmap, ®_obstack); |
2093 | bitmap_initialize (&scratch_operand_bitmap, ®_obstack); | |
11cd3bed | 2094 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2095 | FOR_BB_INSNS (bb, insn) |
2096 | if (INSN_P (insn)) | |
2713e5db | 2097 | remove_scratches_1 (insn); |
55a2c322 VM |
2098 | } |
2099 | ||
2100 | /* Changes pseudos created by function remove_scratches onto scratches. */ | |
2101 | static void | |
2102 | restore_scratches (void) | |
2103 | { | |
9771b263 DN |
2104 | int regno; |
2105 | unsigned i; | |
926cd61f | 2106 | sloc_t loc; |
cfa434f6 | 2107 | rtx_insn *last = NULL; |
55a2c322 VM |
2108 | lra_insn_recog_data_t id = NULL; |
2109 | ||
9771b263 | 2110 | for (i = 0; scratches.iterate (i, &loc); i++) |
55a2c322 | 2111 | { |
11b6a02e JJ |
2112 | /* Ignore already deleted insns. */ |
2113 | if (NOTE_P (loc->insn) | |
2114 | && NOTE_KIND (loc->insn) == NOTE_INSN_DELETED) | |
2115 | continue; | |
55a2c322 VM |
2116 | if (last != loc->insn) |
2117 | { | |
2118 | last = loc->insn; | |
2119 | id = lra_get_insn_recog_data (last); | |
2120 | } | |
f961ec70 AS |
2121 | if (loc->icode != id->icode) |
2122 | { | |
2123 | /* The icode doesn't match, which means the insn has been modified | |
2124 | (e.g. register elimination). The scratch cannot be restored. */ | |
2125 | continue; | |
2126 | } | |
55a2c322 VM |
2127 | if (REG_P (*id->operand_loc[loc->nop]) |
2128 | && ((regno = REGNO (*id->operand_loc[loc->nop])) | |
2129 | >= FIRST_PSEUDO_REGISTER) | |
2130 | && lra_get_regno_hard_regno (regno) < 0) | |
2131 | { | |
2132 | /* It should be only case when scratch register with chosen | |
2133 | constraint 'X' did not get memory or hard register. */ | |
2134 | lra_assert (lra_former_scratch_p (regno)); | |
2135 | *id->operand_loc[loc->nop] | |
2136 | = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop])); | |
2137 | lra_update_dup (id, loc->nop); | |
2138 | if (lra_dump_file != NULL) | |
2139 | fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n", | |
2140 | INSN_UID (loc->insn), loc->nop); | |
2141 | } | |
2142 | } | |
9771b263 | 2143 | for (i = 0; scratches.iterate (i, &loc); i++) |
55a2c322 | 2144 | free (loc); |
9771b263 | 2145 | scratches.release (); |
55a2c322 VM |
2146 | bitmap_clear (&scratch_bitmap); |
2147 | bitmap_clear (&scratch_operand_bitmap); | |
2148 | } | |
2149 | ||
2150 | \f | |
2151 | ||
55a2c322 VM |
2152 | /* Function checks RTL for correctness. If FINAL_P is true, it is |
2153 | done at the end of LRA and the check is more rigorous. */ | |
2154 | static void | |
2155 | check_rtl (bool final_p) | |
2156 | { | |
55a2c322 | 2157 | basic_block bb; |
cfa434f6 | 2158 | rtx_insn *insn; |
55a2c322 VM |
2159 | |
2160 | lra_assert (! final_p || reload_completed); | |
11cd3bed | 2161 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2162 | FOR_BB_INSNS (bb, insn) |
2163 | if (NONDEBUG_INSN_P (insn) | |
2164 | && GET_CODE (PATTERN (insn)) != USE | |
2165 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
55a2c322 VM |
2166 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
2167 | { | |
2168 | if (final_p) | |
2169 | { | |
75d25a02 | 2170 | extract_constrain_insn (insn); |
55a2c322 VM |
2171 | continue; |
2172 | } | |
a26891f4 VM |
2173 | /* LRA code is based on assumption that all addresses can be |
2174 | correctly decomposed. LRA can generate reloads for | |
2175 | decomposable addresses. The decomposition code checks the | |
2176 | correctness of the addresses. So we don't need to check | |
49f5efa5 VM |
2177 | the addresses here. Don't call insn_invalid_p here, it can |
2178 | change the code at this stage. */ | |
2179 | if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0) | |
55a2c322 | 2180 | fatal_insn_not_found (insn); |
55a2c322 VM |
2181 | } |
2182 | } | |
55a2c322 VM |
2183 | |
2184 | /* Determine if the current function has an exception receiver block | |
2185 | that reaches the exit block via non-exceptional edges */ | |
2186 | static bool | |
2187 | has_nonexceptional_receiver (void) | |
2188 | { | |
2189 | edge e; | |
2190 | edge_iterator ei; | |
2191 | basic_block *tos, *worklist, bb; | |
2192 | ||
2193 | /* If we're not optimizing, then just err on the safe side. */ | |
2194 | if (!optimize) | |
2195 | return true; | |
f4eafc30 | 2196 | |
55a2c322 | 2197 | /* First determine which blocks can reach exit via normal paths. */ |
0cae8d31 | 2198 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); |
55a2c322 | 2199 | |
11cd3bed | 2200 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2201 | bb->flags &= ~BB_REACHABLE; |
2202 | ||
2203 | /* Place the exit block on our worklist. */ | |
fefa31b5 DM |
2204 | EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; |
2205 | *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); | |
f4eafc30 | 2206 | |
55a2c322 VM |
2207 | /* Iterate: find everything reachable from what we've already seen. */ |
2208 | while (tos != worklist) | |
2209 | { | |
2210 | bb = *--tos; | |
2211 | ||
2212 | FOR_EACH_EDGE (e, ei, bb->preds) | |
2213 | if (e->flags & EDGE_ABNORMAL) | |
2214 | { | |
2215 | free (worklist); | |
2216 | return true; | |
2217 | } | |
2218 | else | |
2219 | { | |
2220 | basic_block src = e->src; | |
2221 | ||
2222 | if (!(src->flags & BB_REACHABLE)) | |
2223 | { | |
2224 | src->flags |= BB_REACHABLE; | |
2225 | *tos++ = src; | |
2226 | } | |
2227 | } | |
2228 | } | |
2229 | free (worklist); | |
2230 | /* No exceptional block reached exit unexceptionally. */ | |
2231 | return false; | |
2232 | } | |
2233 | ||
55a2c322 VM |
2234 | /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. |
2235 | We change pseudos by hard registers without notification of DF and | |
2236 | that can make the notes obsolete. DF-infrastructure does not deal | |
2237 | with REG_INC notes -- so we should regenerate them here. */ | |
2238 | static void | |
2239 | update_inc_notes (void) | |
2240 | { | |
2241 | rtx *pnote; | |
2242 | basic_block bb; | |
cfa434f6 | 2243 | rtx_insn *insn; |
55a2c322 | 2244 | |
11cd3bed | 2245 | FOR_EACH_BB_FN (bb, cfun) |
55a2c322 VM |
2246 | FOR_BB_INSNS (bb, insn) |
2247 | if (NONDEBUG_INSN_P (insn)) | |
2248 | { | |
2249 | pnote = ®_NOTES (insn); | |
2250 | while (*pnote != 0) | |
2251 | { | |
20f114a3 YR |
2252 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
2253 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
2254 | || REG_NOTE_KIND (*pnote) == REG_INC) | |
55a2c322 VM |
2255 | *pnote = XEXP (*pnote, 1); |
2256 | else | |
2257 | pnote = &XEXP (*pnote, 1); | |
2258 | } | |
760edf20 TS |
2259 | |
2260 | if (AUTO_INC_DEC) | |
2261 | add_auto_inc_notes (insn, PATTERN (insn)); | |
55a2c322 VM |
2262 | } |
2263 | } | |
2264 | ||
2265 | /* Set to 1 while in lra. */ | |
2266 | int lra_in_progress; | |
2267 | ||
f681cf95 VM |
2268 | /* Start of pseudo regnos before the LRA. */ |
2269 | int lra_new_regno_start; | |
2270 | ||
f4eafc30 | 2271 | /* Start of reload pseudo regnos before the new spill pass. */ |
55a2c322 VM |
2272 | int lra_constraint_new_regno_start; |
2273 | ||
8fd827b8 VM |
2274 | /* Avoid spilling pseudos with regno more than the following value if |
2275 | it is possible. */ | |
2276 | int lra_bad_spill_regno_start; | |
2277 | ||
f4eafc30 | 2278 | /* Inheritance pseudo regnos before the new spill pass. */ |
55a2c322 VM |
2279 | bitmap_head lra_inheritance_pseudos; |
2280 | ||
f4eafc30 | 2281 | /* Split regnos before the new spill pass. */ |
55a2c322 VM |
2282 | bitmap_head lra_split_regs; |
2283 | ||
5764ee3c JW |
2284 | /* Reload pseudo regnos before the new assignment pass which still can |
2285 | be spilled after the assignment pass as memory is also accepted in | |
2b778c9d | 2286 | insns for the reload pseudos. */ |
55a2c322 VM |
2287 | bitmap_head lra_optional_reload_pseudos; |
2288 | ||
2b778c9d | 2289 | /* Pseudo regnos used for subreg reloads before the new assignment |
5764ee3c | 2290 | pass. Such pseudos still can be spilled after the assignment |
2b778c9d VM |
2291 | pass. */ |
2292 | bitmap_head lra_subreg_reload_pseudos; | |
2293 | ||
55a2c322 VM |
2294 | /* File used for output of LRA debug information. */ |
2295 | FILE *lra_dump_file; | |
2296 | ||
11067dee VM |
2297 | /* True if we found an asm error. */ |
2298 | bool lra_asm_error_p; | |
2299 | ||
55a2c322 VM |
2300 | /* True if we should try spill into registers of different classes |
2301 | instead of memory. */ | |
2302 | bool lra_reg_spill_p; | |
2303 | ||
2304 | /* Set up value LRA_REG_SPILL_P. */ | |
2305 | static void | |
2306 | setup_reg_spill_flag (void) | |
2307 | { | |
2308 | int cl, mode; | |
2309 | ||
2310 | if (targetm.spill_class != NULL) | |
2311 | for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++) | |
2312 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
2313 | if (targetm.spill_class ((enum reg_class) cl, | |
ef4bddc2 | 2314 | (machine_mode) mode) != NO_REGS) |
55a2c322 VM |
2315 | { |
2316 | lra_reg_spill_p = true; | |
2317 | return; | |
2318 | } | |
2319 | lra_reg_spill_p = false; | |
2320 | } | |
2321 | ||
2322 | /* True if the current function is too big to use regular algorithms | |
2323 | in LRA. In other words, we should use simpler and faster algorithms | |
2324 | in LRA. It also means we should not worry about generation code | |
2325 | for caller saves. The value is set up in IRA. */ | |
2326 | bool lra_simple_p; | |
2327 | ||
2328 | /* Major LRA entry function. F is a file should be used to dump LRA | |
2329 | debug info. */ | |
2330 | void | |
2331 | lra (FILE *f) | |
2332 | { | |
2333 | int i; | |
15961e4a | 2334 | bool live_p, inserted_p; |
55a2c322 VM |
2335 | |
2336 | lra_dump_file = f; | |
11067dee VM |
2337 | lra_asm_error_p = false; |
2338 | ||
55a2c322 VM |
2339 | timevar_push (TV_LRA); |
2340 | ||
2c62cbaa VM |
2341 | /* Make sure that the last insn is a note. Some subsequent passes |
2342 | need it. */ | |
2343 | emit_note (NOTE_INSN_DELETED); | |
2344 | ||
6576d245 | 2345 | lra_no_alloc_regs = ira_no_alloc_regs; |
b28ece32 | 2346 | |
afa22e29 VM |
2347 | init_reg_info (); |
2348 | expand_reg_info (); | |
2349 | ||
55a2c322 VM |
2350 | init_insn_recog_data (); |
2351 | ||
49f5efa5 | 2352 | /* Some quick check on RTL generated by previous passes. */ |
b2b29377 MM |
2353 | if (flag_checking) |
2354 | check_rtl (false); | |
55a2c322 | 2355 | |
49f5efa5 VM |
2356 | lra_in_progress = 1; |
2357 | ||
f54437d5 VM |
2358 | lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0; |
2359 | lra_assignment_iter = lra_assignment_iter_after_spill = 0; | |
55a2c322 | 2360 | lra_inheritance_iter = lra_undo_inheritance_iter = 0; |
94446928 | 2361 | lra_rematerialization_iter = 0; |
55a2c322 VM |
2362 | |
2363 | setup_reg_spill_flag (); | |
2364 | ||
55a2c322 VM |
2365 | /* Function remove_scratches can creates new pseudos for clobbers -- |
2366 | so set up lra_constraint_new_regno_start before its call to | |
2367 | permit changing reg classes for pseudos created by this | |
2368 | simplification. */ | |
f681cf95 | 2369 | lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num (); |
8fd827b8 | 2370 | lra_bad_spill_regno_start = INT_MAX; |
55a2c322 | 2371 | remove_scratches (); |
55a2c322 VM |
2372 | |
2373 | /* A function that has a non-local label that can reach the exit | |
2374 | block via non-exceptional paths must save all call-saved | |
2375 | registers. */ | |
2376 | if (cfun->has_nonlocal_label && has_nonexceptional_receiver ()) | |
2377 | crtl->saves_all_registers = 1; | |
2378 | ||
2379 | if (crtl->saves_all_registers) | |
2380 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
a1e6ee38 RS |
2381 | if (!crtl->abi->clobbers_full_reg_p (i) |
2382 | && !fixed_regs[i] | |
2383 | && !LOCAL_REGNO (i)) | |
55a2c322 VM |
2384 | df_set_regs_ever_live (i, true); |
2385 | ||
2386 | /* We don't DF from now and avoid its using because it is to | |
2387 | expensive when a lot of RTL changes are made. */ | |
2388 | df_set_flags (DF_NO_INSN_RESCAN); | |
9771b263 | 2389 | lra_constraint_insn_stack.create (get_max_uid ()); |
55a2c322 | 2390 | lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ()); |
f61e445a | 2391 | bitmap_clear (lra_constraint_insn_stack_bitmap); |
55a2c322 VM |
2392 | lra_live_ranges_init (); |
2393 | lra_constraints_init (); | |
2394 | lra_curr_reload_num = 0; | |
cfa434f6 | 2395 | push_insns (get_last_insn (), NULL); |
55a2c322 | 2396 | /* It is needed for the 1st coalescing. */ |
55a2c322 VM |
2397 | bitmap_initialize (&lra_inheritance_pseudos, ®_obstack); |
2398 | bitmap_initialize (&lra_split_regs, ®_obstack); | |
2399 | bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack); | |
2b778c9d | 2400 | bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack); |
55a2c322 | 2401 | live_p = false; |
f075bd95 | 2402 | if (maybe_ne (get_frame_size (), 0) && crtl->stack_alignment_needed) |
2c62cbaa VM |
2403 | /* If we have a stack frame, we must align it now. The stack size |
2404 | may be a part of the offset computation for register | |
2405 | elimination. */ | |
2406 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
4c2b2d79 | 2407 | lra_init_equiv (); |
55a2c322 VM |
2408 | for (;;) |
2409 | { | |
2410 | for (;;) | |
2411 | { | |
0a045a1f | 2412 | bool reloads_p = lra_constraints (lra_constraint_iter == 0); |
55a2c322 VM |
2413 | /* Constraint transformations may result in that eliminable |
2414 | hard regs become uneliminable and pseudos which use them | |
2415 | should be spilled. It is better to do it before pseudo | |
2416 | assignments. | |
2417 | ||
2418 | For example, rs6000 can make | |
2419 | RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started | |
2420 | to use a constant pool. */ | |
8d49e7ef | 2421 | lra_eliminate (false, false); |
0a045a1f VM |
2422 | /* We should try to assign hard registers to scratches even |
2423 | if there were no RTL transformations in lra_constraints. | |
2424 | Also we should check IRA assignments on the first | |
2425 | iteration as they can be wrong because of early clobbers | |
2426 | operands which are ignored in IRA. */ | |
2427 | if (! reloads_p && lra_constraint_iter > 1) | |
2428 | { | |
2429 | /* Stack is not empty here only when there are changes | |
2430 | during the elimination sub-pass. */ | |
2431 | if (bitmap_empty_p (lra_constraint_insn_stack_bitmap)) | |
2432 | break; | |
2433 | else | |
2434 | /* If there are no reloads but changing due | |
2435 | elimination, restart the constraint sub-pass | |
2436 | first. */ | |
2437 | continue; | |
2438 | } | |
55a2c322 VM |
2439 | /* Do inheritance only for regular algorithms. */ |
2440 | if (! lra_simple_p) | |
a1e6ee38 | 2441 | lra_inheritance (); |
4ccf8f43 JJ |
2442 | if (live_p) |
2443 | lra_clear_live_ranges (); | |
6027ea4c VM |
2444 | bool fails_p; |
2445 | do | |
55a2c322 | 2446 | { |
6027ea4c VM |
2447 | /* We need live ranges for lra_assign -- so build them. |
2448 | But don't remove dead insns or change global live | |
2449 | info as we can undo inheritance transformations after | |
2450 | inheritance pseudo assigning. */ | |
12981e9b | 2451 | lra_create_live_ranges (true, !lra_simple_p); |
6027ea4c VM |
2452 | live_p = true; |
2453 | /* If we don't spill non-reload and non-inheritance | |
2454 | pseudos, there is no sense to run memory-memory move | |
2455 | coalescing. If inheritance pseudos were spilled, the | |
2456 | memory-memory moves involving them will be removed by | |
2457 | pass undoing inheritance. */ | |
2458 | if (lra_simple_p) | |
2459 | lra_assign (fails_p); | |
2460 | else | |
72ea0d47 | 2461 | { |
6027ea4c VM |
2462 | bool spill_p = !lra_assign (fails_p); |
2463 | ||
2464 | if (lra_undo_inheritance ()) | |
2465 | live_p = false; | |
2466 | if (spill_p && ! fails_p) | |
72ea0d47 | 2467 | { |
6027ea4c VM |
2468 | if (! live_p) |
2469 | { | |
2470 | lra_create_live_ranges (true, true); | |
2471 | live_p = true; | |
2472 | } | |
2473 | if (lra_coalesce ()) | |
2474 | live_p = false; | |
72ea0d47 | 2475 | } |
6027ea4c VM |
2476 | if (! live_p) |
2477 | lra_clear_live_ranges (); | |
2478 | } | |
2479 | if (fails_p) | |
2480 | { | |
2481 | /* It is a very rare case. It is the last hope to | |
2482 | split a hard regno live range for a reload | |
2483 | pseudo. */ | |
2484 | if (live_p) | |
2485 | lra_clear_live_ranges (); | |
2486 | live_p = false; | |
2487 | if (! lra_split_hard_reg_for ()) | |
2488 | break; | |
72ea0d47 | 2489 | } |
55a2c322 | 2490 | } |
6027ea4c | 2491 | while (fails_p); |
12981e9b VM |
2492 | if (! live_p) { |
2493 | /* We need the correct reg notes for work of constraint sub-pass. */ | |
2494 | lra_create_live_ranges (true, true); | |
2495 | live_p = true; | |
2496 | } | |
55a2c322 | 2497 | } |
080cbf9e VM |
2498 | /* Don't clear optional reloads bitmap until all constraints are |
2499 | satisfied as we need to differ them from regular reloads. */ | |
2500 | bitmap_clear (&lra_optional_reload_pseudos); | |
2b778c9d | 2501 | bitmap_clear (&lra_subreg_reload_pseudos); |
55a2c322 VM |
2502 | bitmap_clear (&lra_inheritance_pseudos); |
2503 | bitmap_clear (&lra_split_regs); | |
55a2c322 VM |
2504 | if (! live_p) |
2505 | { | |
2506 | /* We need full live info for spilling pseudos into | |
2507 | registers instead of memory. */ | |
4ab74a01 | 2508 | lra_create_live_ranges (lra_reg_spill_p, true); |
55a2c322 VM |
2509 | live_p = true; |
2510 | } | |
4ab74a01 VM |
2511 | /* We should check necessity for spilling here as the above live |
2512 | range pass can remove spilled pseudos. */ | |
2513 | if (! lra_need_for_spills_p ()) | |
2514 | break; | |
d9cf932c VM |
2515 | /* Now we know what pseudos should be spilled. Try to |
2516 | rematerialize them first. */ | |
f607c5c4 | 2517 | if (lra_remat ()) |
d9cf932c VM |
2518 | { |
2519 | /* We need full live info -- see the comment above. */ | |
4ab74a01 | 2520 | lra_create_live_ranges (lra_reg_spill_p, true); |
d9cf932c VM |
2521 | live_p = true; |
2522 | if (! lra_need_for_spills_p ()) | |
23e0f4c3 BE |
2523 | { |
2524 | if (lra_need_for_scratch_reg_p ()) | |
2525 | continue; | |
2526 | break; | |
2527 | } | |
d9cf932c | 2528 | } |
55a2c322 VM |
2529 | lra_spill (); |
2530 | /* Assignment of stack slots changes elimination offsets for | |
2531 | some eliminations. So update the offsets here. */ | |
8d49e7ef | 2532 | lra_eliminate (false, false); |
8fd827b8 VM |
2533 | lra_constraint_new_regno_start = max_reg_num (); |
2534 | if (lra_bad_spill_regno_start == INT_MAX | |
2535 | && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES | |
2536 | && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES) | |
2537 | /* After switching off inheritance and rematerialization | |
2538 | passes, avoid spilling reload pseudos will be created to | |
2539 | prevent LRA cycling in some complicated cases. */ | |
2540 | lra_bad_spill_regno_start = lra_constraint_new_regno_start; | |
f54437d5 | 2541 | lra_assignment_iter_after_spill = 0; |
55a2c322 VM |
2542 | } |
2543 | restore_scratches (); | |
8d49e7ef | 2544 | lra_eliminate (true, false); |
c5cd5a7e | 2545 | lra_final_code_change (); |
55a2c322 | 2546 | lra_in_progress = 0; |
4ccf8f43 JJ |
2547 | if (live_p) |
2548 | lra_clear_live_ranges (); | |
55a2c322 VM |
2549 | lra_live_ranges_finish (); |
2550 | lra_constraints_finish (); | |
2551 | finish_reg_info (); | |
2552 | sbitmap_free (lra_constraint_insn_stack_bitmap); | |
9771b263 | 2553 | lra_constraint_insn_stack.release (); |
55a2c322 VM |
2554 | finish_insn_recog_data (); |
2555 | regstat_free_n_sets_and_refs (); | |
2556 | regstat_free_ri (); | |
2557 | reload_completed = 1; | |
2558 | update_inc_notes (); | |
2559 | ||
2560 | inserted_p = fixup_abnormal_edges (); | |
2561 | ||
2562 | /* We've possibly turned single trapping insn into multiple ones. */ | |
2563 | if (cfun->can_throw_non_call_exceptions) | |
2564 | { | |
7ba9e72d | 2565 | auto_sbitmap blocks (last_basic_block_for_fn (cfun)); |
f61e445a | 2566 | bitmap_ones (blocks); |
55a2c322 | 2567 | find_many_sub_basic_blocks (blocks); |
55a2c322 VM |
2568 | } |
2569 | ||
2570 | if (inserted_p) | |
2571 | commit_edge_insertions (); | |
2572 | ||
2573 | /* Replacing pseudos with their memory equivalents might have | |
2574 | created shared rtx. Subsequent passes would get confused | |
2575 | by this, so unshare everything here. */ | |
2576 | unshare_all_rtl_again (get_insns ()); | |
2577 | ||
b2b29377 MM |
2578 | if (flag_checking) |
2579 | check_rtl (true); | |
55a2c322 VM |
2580 | |
2581 | timevar_pop (TV_LRA); | |
2582 | } | |
2583 | ||
2584 | /* Called once per compiler to initialize LRA data once. */ | |
2585 | void | |
2586 | lra_init_once (void) | |
2587 | { | |
2588 | init_insn_code_data_once (); | |
2589 | } | |
2590 | ||
55a2c322 VM |
2591 | /* Called once per compiler to finish LRA data which are initialize |
2592 | once. */ | |
2593 | void | |
2594 | lra_finish_once (void) | |
2595 | { | |
2596 | finish_insn_code_data_once (); | |
2597 | } |