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c6a6cdaa | 1 | /* LRA (local register allocator) driver and LRA utilities. |
fbd26352 | 2 | Copyright (C) 2010-2019 Free Software Foundation, Inc. |
c6a6cdaa | 3 | Contributed by Vladimir Makarov <vmakarov@redhat.com>. |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify it under | |
8 | the terms of the GNU General Public License as published by the Free | |
9 | Software Foundation; either version 3, or (at your option) any later | |
10 | version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | ||
22 | /* The Local Register Allocator (LRA) is a replacement of former | |
23 | reload pass. It is focused to simplify code solving the reload | |
24 | pass tasks, to make the code maintenance easier, and to implement new | |
25 | perspective optimizations. | |
26 | ||
27 | The major LRA design solutions are: | |
28 | o division small manageable, separated sub-tasks | |
29 | o reflection of all transformations and decisions in RTL as more | |
30 | as possible | |
31 | o insn constraints as a primary source of the info (minimizing | |
32 | number of target-depended macros/hooks) | |
33 | ||
34 | In brief LRA works by iterative insn process with the final goal is | |
35 | to satisfy all insn and address constraints: | |
36 | o New reload insns (in brief reloads) and reload pseudos might be | |
37 | generated; | |
38 | o Some pseudos might be spilled to assign hard registers to | |
39 | new reload pseudos; | |
497ba60f | 40 | o Recalculating spilled pseudo values (rematerialization); |
c6a6cdaa | 41 | o Changing spilled pseudos to stack memory or their equivalences; |
42 | o Allocation stack memory changes the address displacement and | |
43 | new iteration is needed. | |
44 | ||
45 | Here is block diagram of LRA passes: | |
46 | ||
1f3a048a | 47 | ------------------------ |
48 | --------------- | Undo inheritance for | --------------- | |
49 | | Memory-memory | | spilled pseudos, | | New (and old) | | |
50 | | move coalesce |<---| splits for pseudos got |<-- | pseudos | | |
51 | --------------- | the same hard regs, | | assignment | | |
52 | Start | | and optional reloads | --------------- | |
53 | | | ------------------------ ^ | |
b28ae2d4 | 54 | V | ---------------- | |
55 | ----------- V | Update virtual | | | |
56 | | Remove |----> ------------>| register | | | |
57 | | scratches | ^ | displacements | | | |
58 | ----------- | ---------------- | | |
59 | | | | | |
60 | | V New | | |
497ba60f | 61 | | ------------ pseudos ------------------- |
62 | | |Constraints:| or insns | Inheritance/split | | |
63 | | | RTL |--------->| transformations | | |
64 | | | transfor- | | in EBB scope | | |
65 | | substi- | mations | ------------------- | |
66 | | tutions ------------ | |
67 | | | No change | |
68 | ---------------- V | |
69 | | Spilled pseudo | ------------------- | |
70 | | to memory |<----| Rematerialization | | |
71 | | substitution | ------------------- | |
72 | ---------------- | |
73 | | No susbtitions | |
74 | V | |
75 | ------------------------- | |
76 | | Hard regs substitution, | | |
77 | | devirtalization, and |------> Finish | |
78 | | restoring scratches got | | |
79 | | memory | | |
80 | ------------------------- | |
c6a6cdaa | 81 | |
82 | To speed up the process: | |
83 | o We process only insns affected by changes on previous | |
84 | iterations; | |
85 | o We don't use DFA-infrastructure because it results in much slower | |
86 | compiler speed than a special IR described below does; | |
87 | o We use a special insn representation for quick access to insn | |
88 | info which is always *synchronized* with the current RTL; | |
89 | o Insn IR is minimized by memory. It is divided on three parts: | |
90 | o one specific for each insn in RTL (only operand locations); | |
91 | o one common for all insns in RTL with the same insn code | |
92 | (different operand attributes from machine descriptions); | |
93 | o one oriented for maintenance of live info (list of pseudos). | |
94 | o Pseudo data: | |
95 | o all insns where the pseudo is referenced; | |
96 | o live info (conflicting hard regs, live ranges, # of | |
97 | references etc); | |
98 | o data used for assigning (preferred hard regs, costs etc). | |
99 | ||
100 | This file contains LRA driver, LRA utility functions and data, and | |
101 | code for dealing with scratches. */ | |
102 | ||
103 | #include "config.h" | |
104 | #include "system.h" | |
105 | #include "coretypes.h" | |
9ef16211 | 106 | #include "backend.h" |
7c29e30e | 107 | #include "target.h" |
c6a6cdaa | 108 | #include "rtl.h" |
7c29e30e | 109 | #include "tree.h" |
110 | #include "predict.h" | |
9ef16211 | 111 | #include "df.h" |
ad7b10a2 | 112 | #include "memmodel.h" |
c6a6cdaa | 113 | #include "tm_p.h" |
7c29e30e | 114 | #include "optabs.h" |
c6a6cdaa | 115 | #include "regs.h" |
7c29e30e | 116 | #include "ira.h" |
c6a6cdaa | 117 | #include "recog.h" |
c6a6cdaa | 118 | #include "expr.h" |
94ea8568 | 119 | #include "cfgrtl.h" |
120 | #include "cfgbuild.h" | |
9ef16211 | 121 | #include "lra.h" |
c6a6cdaa | 122 | #include "lra-int.h" |
397881d3 | 123 | #include "print-rtl.h" |
c6a6cdaa | 124 | |
8c0d01a4 | 125 | /* Dump bitmap SET with TITLE and BB INDEX. */ |
126 | void | |
127 | lra_dump_bitmap_with_title (const char *title, bitmap set, int index) | |
128 | { | |
129 | unsigned int i; | |
130 | int count; | |
131 | bitmap_iterator bi; | |
132 | static const int max_nums_on_line = 10; | |
133 | ||
134 | if (bitmap_empty_p (set)) | |
135 | return; | |
136 | fprintf (lra_dump_file, " %s %d:", title, index); | |
137 | fprintf (lra_dump_file, "\n"); | |
138 | count = max_nums_on_line + 1; | |
139 | EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi) | |
140 | { | |
141 | if (count > max_nums_on_line) | |
142 | { | |
143 | fprintf (lra_dump_file, "\n "); | |
144 | count = 0; | |
145 | } | |
146 | fprintf (lra_dump_file, " %4u", i); | |
147 | count++; | |
148 | } | |
149 | fprintf (lra_dump_file, "\n"); | |
150 | } | |
151 | ||
c6a6cdaa | 152 | /* Hard registers currently not available for allocation. It can |
153 | changed after some hard registers become not eliminable. */ | |
154 | HARD_REG_SET lra_no_alloc_regs; | |
155 | ||
156 | static int get_new_reg_value (void); | |
157 | static void expand_reg_info (void); | |
158 | static void invalidate_insn_recog_data (int); | |
7f836b57 | 159 | static int get_insn_freq (rtx_insn *); |
160 | static void invalidate_insn_data_regno_info (lra_insn_recog_data_t, | |
161 | rtx_insn *, int); | |
409a6c36 | 162 | static void remove_scratches_1 (rtx_insn *); |
c6a6cdaa | 163 | |
164 | /* Expand all regno related info needed for LRA. */ | |
165 | static void | |
7619e612 | 166 | expand_reg_data (int old) |
c6a6cdaa | 167 | { |
168 | resize_reg_info (); | |
169 | expand_reg_info (); | |
170 | ira_expand_reg_equiv (); | |
7619e612 | 171 | for (int i = (int) max_reg_num () - 1; i >= old; i--) |
172 | lra_change_class (i, ALL_REGS, " Set", true); | |
c6a6cdaa | 173 | } |
174 | ||
175 | /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL | |
176 | or of VOIDmode, use MD_MODE for the new reg. Initialize its | |
177 | register class to RCLASS. Print message about assigning class | |
178 | RCLASS containing new register name TITLE unless it is NULL. Use | |
179 | attributes of ORIGINAL if it is a register. The created register | |
180 | will have unique held value. */ | |
181 | rtx | |
3754d046 | 182 | lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original, |
c6a6cdaa | 183 | enum reg_class rclass, const char *title) |
184 | { | |
3754d046 | 185 | machine_mode mode; |
c6a6cdaa | 186 | rtx new_reg; |
187 | ||
188 | if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode) | |
189 | mode = md_mode; | |
190 | lra_assert (mode != VOIDmode); | |
191 | new_reg = gen_reg_rtx (mode); | |
192 | if (original == NULL_RTX || ! REG_P (original)) | |
193 | { | |
194 | if (lra_dump_file != NULL) | |
195 | fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg)); | |
196 | } | |
197 | else | |
198 | { | |
199 | if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER) | |
200 | ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original); | |
201 | REG_USERVAR_P (new_reg) = REG_USERVAR_P (original); | |
202 | REG_POINTER (new_reg) = REG_POINTER (original); | |
203 | REG_ATTRS (new_reg) = REG_ATTRS (original); | |
204 | if (lra_dump_file != NULL) | |
205 | fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i", | |
206 | REGNO (new_reg), REGNO (original)); | |
207 | } | |
208 | if (lra_dump_file != NULL) | |
209 | { | |
210 | if (title != NULL) | |
211 | fprintf (lra_dump_file, ", assigning class %s to%s%s r%d", | |
212 | reg_class_names[rclass], *title == '\0' ? "" : " ", | |
213 | title, REGNO (new_reg)); | |
214 | fprintf (lra_dump_file, "\n"); | |
215 | } | |
7619e612 | 216 | expand_reg_data (max_reg_num ()); |
c6a6cdaa | 217 | setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass); |
218 | return new_reg; | |
219 | } | |
220 | ||
221 | /* Analogous to the previous function but also inherits value of | |
222 | ORIGINAL. */ | |
223 | rtx | |
3754d046 | 224 | lra_create_new_reg (machine_mode md_mode, rtx original, |
c6a6cdaa | 225 | enum reg_class rclass, const char *title) |
226 | { | |
227 | rtx new_reg; | |
228 | ||
229 | new_reg | |
230 | = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title); | |
231 | if (original != NULL_RTX && REG_P (original)) | |
a1064490 | 232 | lra_assign_reg_val (REGNO (original), REGNO (new_reg)); |
c6a6cdaa | 233 | return new_reg; |
234 | } | |
235 | ||
236 | /* Set up for REGNO unique hold value. */ | |
237 | void | |
238 | lra_set_regno_unique_value (int regno) | |
239 | { | |
240 | lra_reg_info[regno].val = get_new_reg_value (); | |
241 | } | |
242 | ||
3b3a5e5f | 243 | /* Invalidate INSN related info used by LRA. The info should never be |
244 | used after that. */ | |
c6a6cdaa | 245 | void |
7f836b57 | 246 | lra_invalidate_insn_data (rtx_insn *insn) |
c6a6cdaa | 247 | { |
248 | lra_invalidate_insn_regno_info (insn); | |
249 | invalidate_insn_recog_data (INSN_UID (insn)); | |
250 | } | |
251 | ||
252 | /* Mark INSN deleted and invalidate the insn related info used by | |
253 | LRA. */ | |
254 | void | |
7f836b57 | 255 | lra_set_insn_deleted (rtx_insn *insn) |
c6a6cdaa | 256 | { |
257 | lra_invalidate_insn_data (insn); | |
258 | SET_INSN_DELETED (insn); | |
259 | } | |
260 | ||
261 | /* Delete an unneeded INSN and any previous insns who sole purpose is | |
262 | loading data that is dead in INSN. */ | |
263 | void | |
7f836b57 | 264 | lra_delete_dead_insn (rtx_insn *insn) |
c6a6cdaa | 265 | { |
7f836b57 | 266 | rtx_insn *prev = prev_real_insn (insn); |
c6a6cdaa | 267 | rtx prev_dest; |
268 | ||
269 | /* If the previous insn sets a register that dies in our insn, | |
270 | delete it too. */ | |
271 | if (prev && GET_CODE (PATTERN (prev)) == SET | |
272 | && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) | |
273 | && reg_mentioned_p (prev_dest, PATTERN (insn)) | |
274 | && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) | |
275 | && ! side_effects_p (SET_SRC (PATTERN (prev)))) | |
276 | lra_delete_dead_insn (prev); | |
277 | ||
278 | lra_set_insn_deleted (insn); | |
279 | } | |
280 | ||
6c397456 | 281 | /* Emit insn x = y + z. Return NULL if we failed to do it. |
282 | Otherwise, return the insn. We don't use gen_add3_insn as it might | |
283 | clobber CC. */ | |
9ed997be | 284 | static rtx_insn * |
6c397456 | 285 | emit_add3_insn (rtx x, rtx y, rtx z) |
286 | { | |
57c26b3a | 287 | rtx_insn *last; |
6c397456 | 288 | |
289 | last = get_last_insn (); | |
79127ad5 | 290 | |
291 | if (have_addptr3_insn (x, y, z)) | |
292 | { | |
9ed997be | 293 | rtx_insn *insn = gen_addptr3_insn (x, y, z); |
79127ad5 | 294 | |
295 | /* If the target provides an "addptr" pattern it hopefully does | |
296 | for a reason. So falling back to the normal add would be | |
297 | a bug. */ | |
298 | lra_assert (insn != NULL_RTX); | |
299 | emit_insn (insn); | |
300 | return insn; | |
301 | } | |
302 | ||
d1f9b275 | 303 | rtx_insn *insn = emit_insn (gen_rtx_SET (x, gen_rtx_PLUS (GET_MODE (y), |
304 | y, z))); | |
6c397456 | 305 | if (recog_memoized (insn) < 0) |
306 | { | |
307 | delete_insns_since (last); | |
ed3e6e5d | 308 | insn = NULL; |
6c397456 | 309 | } |
310 | return insn; | |
311 | } | |
312 | ||
313 | /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the | |
314 | last resort. */ | |
9ed997be | 315 | static rtx_insn * |
6c397456 | 316 | emit_add2_insn (rtx x, rtx y) |
317 | { | |
9ed997be | 318 | rtx_insn *insn = emit_add3_insn (x, x, y); |
6c397456 | 319 | if (insn == NULL_RTX) |
320 | { | |
321 | insn = gen_add2_insn (x, y); | |
322 | if (insn != NULL_RTX) | |
323 | emit_insn (insn); | |
324 | } | |
325 | return insn; | |
326 | } | |
327 | ||
c6a6cdaa | 328 | /* Target checks operands through operand predicates to recognize an |
329 | insn. We should have a special precaution to generate add insns | |
330 | which are frequent results of elimination. | |
331 | ||
332 | Emit insns for x = y + z. X can be used to store intermediate | |
333 | values and should be not in Y and Z when we use X to store an | |
334 | intermediate value. Y + Z should form [base] [+ index[ * scale]] [ | |
335 | + disp] where base and index are registers, disp and scale are | |
336 | constants. Y should contain base if it is present, Z should | |
337 | contain disp if any. index[*scale] can be part of Y or Z. */ | |
338 | void | |
339 | lra_emit_add (rtx x, rtx y, rtx z) | |
340 | { | |
341 | int old; | |
57c26b3a | 342 | rtx_insn *last; |
c6a6cdaa | 343 | rtx a1, a2, base, index, disp, scale, index_scale; |
344 | bool ok_p; | |
345 | ||
9ed997be | 346 | rtx_insn *add3_insn = emit_add3_insn (x, y, z); |
c6a6cdaa | 347 | old = max_reg_num (); |
ed3e6e5d | 348 | if (add3_insn != NULL) |
6c397456 | 349 | ; |
c6a6cdaa | 350 | else |
351 | { | |
352 | disp = a2 = NULL_RTX; | |
353 | if (GET_CODE (y) == PLUS) | |
354 | { | |
355 | a1 = XEXP (y, 0); | |
356 | a2 = XEXP (y, 1); | |
357 | disp = z; | |
358 | } | |
359 | else | |
360 | { | |
361 | a1 = y; | |
362 | if (CONSTANT_P (z)) | |
363 | disp = z; | |
364 | else | |
365 | a2 = z; | |
366 | } | |
367 | index_scale = scale = NULL_RTX; | |
368 | if (GET_CODE (a1) == MULT) | |
369 | { | |
370 | index_scale = a1; | |
371 | index = XEXP (a1, 0); | |
372 | scale = XEXP (a1, 1); | |
373 | base = a2; | |
374 | } | |
375 | else if (a2 != NULL_RTX && GET_CODE (a2) == MULT) | |
376 | { | |
377 | index_scale = a2; | |
378 | index = XEXP (a2, 0); | |
379 | scale = XEXP (a2, 1); | |
380 | base = a1; | |
381 | } | |
382 | else | |
383 | { | |
384 | base = a1; | |
385 | index = a2; | |
386 | } | |
af121a86 | 387 | if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG)) |
1c1417f1 | 388 | || (index != NULL_RTX |
389 | && ! (REG_P (index) || GET_CODE (index) == SUBREG)) | |
c6a6cdaa | 390 | || (disp != NULL_RTX && ! CONSTANT_P (disp)) |
391 | || (scale != NULL_RTX && ! CONSTANT_P (scale))) | |
392 | { | |
6c397456 | 393 | /* Probably we have no 3 op add. Last chance is to use 2-op |
394 | add insn. To succeed, don't move Z to X as an address | |
395 | segment always comes in Y. Otherwise, we might fail when | |
396 | adding the address segment to register. */ | |
c6a6cdaa | 397 | lra_assert (x != y && x != z); |
0178c26e | 398 | emit_move_insn (x, y); |
9ed997be | 399 | rtx_insn *insn = emit_add2_insn (x, z); |
6c397456 | 400 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 401 | } |
402 | else | |
403 | { | |
404 | if (index_scale == NULL_RTX) | |
405 | index_scale = index; | |
406 | if (disp == NULL_RTX) | |
407 | { | |
408 | /* Generate x = index_scale; x = x + base. */ | |
409 | lra_assert (index_scale != NULL_RTX && base != NULL_RTX); | |
410 | emit_move_insn (x, index_scale); | |
9ed997be | 411 | rtx_insn *insn = emit_add2_insn (x, base); |
6c397456 | 412 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 413 | } |
414 | else if (scale == NULL_RTX) | |
415 | { | |
416 | /* Try x = base + disp. */ | |
417 | lra_assert (base != NULL_RTX); | |
418 | last = get_last_insn (); | |
ed3e6e5d | 419 | rtx_insn *move_insn = |
420 | emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp)); | |
421 | if (recog_memoized (move_insn) < 0) | |
c6a6cdaa | 422 | { |
423 | delete_insns_since (last); | |
424 | /* Generate x = disp; x = x + base. */ | |
425 | emit_move_insn (x, disp); | |
9ed997be | 426 | rtx_insn *add2_insn = emit_add2_insn (x, base); |
ed3e6e5d | 427 | lra_assert (add2_insn != NULL_RTX); |
c6a6cdaa | 428 | } |
429 | /* Generate x = x + index. */ | |
430 | if (index != NULL_RTX) | |
431 | { | |
9ed997be | 432 | rtx_insn *insn = emit_add2_insn (x, index); |
6c397456 | 433 | lra_assert (insn != NULL_RTX); |
c6a6cdaa | 434 | } |
435 | } | |
436 | else | |
437 | { | |
438 | /* Try x = index_scale; x = x + disp; x = x + base. */ | |
439 | last = get_last_insn (); | |
ed3e6e5d | 440 | rtx_insn *move_insn = emit_move_insn (x, index_scale); |
c6a6cdaa | 441 | ok_p = false; |
ed3e6e5d | 442 | if (recog_memoized (move_insn) >= 0) |
c6a6cdaa | 443 | { |
9ed997be | 444 | rtx_insn *insn = emit_add2_insn (x, disp); |
c6a6cdaa | 445 | if (insn != NULL_RTX) |
446 | { | |
af121a86 | 447 | if (base == NULL_RTX) |
6c397456 | 448 | ok_p = true; |
af121a86 | 449 | else |
450 | { | |
451 | insn = emit_add2_insn (x, base); | |
452 | if (insn != NULL_RTX) | |
453 | ok_p = true; | |
454 | } | |
c6a6cdaa | 455 | } |
456 | } | |
457 | if (! ok_p) | |
458 | { | |
af121a86 | 459 | rtx_insn *insn; |
460 | ||
c6a6cdaa | 461 | delete_insns_since (last); |
462 | /* Generate x = disp; x = x + base; x = x + index_scale. */ | |
463 | emit_move_insn (x, disp); | |
af121a86 | 464 | if (base != NULL_RTX) |
465 | { | |
466 | insn = emit_add2_insn (x, base); | |
467 | lra_assert (insn != NULL_RTX); | |
468 | } | |
6c397456 | 469 | insn = emit_add2_insn (x, index_scale); |
470 | lra_assert (insn != NULL_RTX); | |
c6a6cdaa | 471 | } |
472 | } | |
473 | } | |
474 | } | |
475 | /* Functions emit_... can create pseudos -- so expand the pseudo | |
476 | data. */ | |
477 | if (old != max_reg_num ()) | |
7619e612 | 478 | expand_reg_data (old); |
c6a6cdaa | 479 | } |
480 | ||
481 | /* The number of emitted reload insns so far. */ | |
482 | int lra_curr_reload_num; | |
483 | ||
484 | /* Emit x := y, processing special case when y = u + v or y = u + v * | |
485 | scale + w through emit_add (Y can be an address which is base + | |
486 | index reg * scale + displacement in general case). X may be used | |
487 | as intermediate result therefore it should be not in Y. */ | |
488 | void | |
489 | lra_emit_move (rtx x, rtx y) | |
490 | { | |
491 | int old; | |
492 | ||
493 | if (GET_CODE (y) != PLUS) | |
494 | { | |
495 | if (rtx_equal_p (x, y)) | |
496 | return; | |
497 | old = max_reg_num (); | |
409a6c36 | 498 | rtx_insn *insn = emit_move_insn (x, y); |
499 | /* The move pattern may require scratch registers, so convert them | |
500 | into real registers now. */ | |
501 | if (insn != NULL_RTX) | |
502 | remove_scratches_1 (insn); | |
c6a6cdaa | 503 | if (REG_P (x)) |
504 | lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num; | |
505 | /* Function emit_move can create pseudos -- so expand the pseudo | |
506 | data. */ | |
507 | if (old != max_reg_num ()) | |
7619e612 | 508 | expand_reg_data (old); |
c6a6cdaa | 509 | return; |
510 | } | |
511 | lra_emit_add (x, XEXP (y, 0), XEXP (y, 1)); | |
512 | } | |
513 | ||
514 | /* Update insn operands which are duplication of operands whose | |
515 | numbers are in array of NOPS (with end marker -1). The insn is | |
516 | represented by its LRA internal representation ID. */ | |
517 | void | |
518 | lra_update_dups (lra_insn_recog_data_t id, signed char *nops) | |
519 | { | |
520 | int i, j, nop; | |
521 | struct lra_static_insn_data *static_id = id->insn_static_data; | |
522 | ||
523 | for (i = 0; i < static_id->n_dups; i++) | |
524 | for (j = 0; (nop = nops[j]) >= 0; j++) | |
525 | if (static_id->dup_num[i] == nop) | |
526 | *id->dup_loc[i] = *id->operand_loc[nop]; | |
527 | } | |
528 | ||
529 | \f | |
530 | ||
531 | /* This page contains code dealing with info about registers in the | |
532 | insns. */ | |
533 | ||
534 | /* Pools for insn reg info. */ | |
1dc6c44d | 535 | object_allocator<lra_insn_reg> lra_insn_reg_pool ("insn regs"); |
c6a6cdaa | 536 | |
3da302c5 | 537 | /* Create LRA insn related info about a reference to REGNO in INSN |
538 | with TYPE (in/out/inout), biggest reference mode MODE, flag that it | |
539 | is reference through subreg (SUBREG_P), flag that is early | |
540 | clobbered in the insn (EARLY_CLOBBER), and reference to the next | |
541 | insn reg info (NEXT). If REGNO can be early clobbered, | |
542 | alternatives in which it can be early clobbered are given by | |
0823eb36 | 543 | EARLY_CLOBBER_ALTS. CLOBBER_HIGH marks if reference is a clobber |
544 | high. */ | |
c6a6cdaa | 545 | static struct lra_insn_reg * |
7f836b57 | 546 | new_insn_reg (rtx_insn *insn, int regno, enum op_type type, |
3754d046 | 547 | machine_mode mode, |
3da302c5 | 548 | bool subreg_p, bool early_clobber, |
549 | alternative_mask early_clobber_alts, | |
0823eb36 | 550 | struct lra_insn_reg *next, bool clobber_high) |
c6a6cdaa | 551 | { |
e16712b1 | 552 | lra_insn_reg *ir = lra_insn_reg_pool.allocate (); |
c6a6cdaa | 553 | ir->type = type; |
554 | ir->biggest_mode = mode; | |
974534ab | 555 | if (NONDEBUG_INSN_P (insn) |
556 | && partial_subreg_p (lra_reg_info[regno].biggest_mode, mode)) | |
fc8a0f60 | 557 | lra_reg_info[regno].biggest_mode = mode; |
c6a6cdaa | 558 | ir->subreg_p = subreg_p; |
559 | ir->early_clobber = early_clobber; | |
3da302c5 | 560 | ir->early_clobber_alts = early_clobber_alts; |
0823eb36 | 561 | ir->clobber_high = clobber_high; |
c6a6cdaa | 562 | ir->regno = regno; |
563 | ir->next = next; | |
564 | return ir; | |
565 | } | |
566 | ||
c6a6cdaa | 567 | /* Free insn reg info list IR. */ |
568 | static void | |
569 | free_insn_regs (struct lra_insn_reg *ir) | |
570 | { | |
571 | struct lra_insn_reg *next_ir; | |
572 | ||
573 | for (; ir != NULL; ir = next_ir) | |
574 | { | |
575 | next_ir = ir->next; | |
e16712b1 | 576 | lra_insn_reg_pool.remove (ir); |
c6a6cdaa | 577 | } |
578 | } | |
579 | ||
580 | /* Finish pool for insn reg info. */ | |
581 | static void | |
582 | finish_insn_regs (void) | |
583 | { | |
e16712b1 | 584 | lra_insn_reg_pool.release (); |
c6a6cdaa | 585 | } |
586 | ||
587 | \f | |
588 | ||
589 | /* This page contains code dealing LRA insn info (or in other words | |
590 | LRA internal insn representation). */ | |
591 | ||
c6a6cdaa | 592 | /* Map INSN_CODE -> the static insn data. This info is valid during |
593 | all translation unit. */ | |
9fdbc432 | 594 | struct lra_static_insn_data *insn_code_data[NUM_INSN_CODES]; |
c6a6cdaa | 595 | |
596 | /* Debug insns are represented as a special insn with one input | |
597 | operand which is RTL expression in var_location. */ | |
598 | ||
599 | /* The following data are used as static insn operand data for all | |
600 | debug insns. If structure lra_operand_data is changed, the | |
601 | initializer should be changed too. */ | |
602 | static struct lra_operand_data debug_operand_data = | |
603 | { | |
604 | NULL, /* alternative */ | |
3da302c5 | 605 | 0, /* early_clobber_alts */ |
1e0295b9 | 606 | E_VOIDmode, /* We are not interesting in the operand mode. */ |
c6a6cdaa | 607 | OP_IN, |
608 | 0, 0, 0, 0 | |
609 | }; | |
610 | ||
611 | /* The following data are used as static insn data for all debug | |
90567983 | 612 | bind insns. If structure lra_static_insn_data is changed, the |
c6a6cdaa | 613 | initializer should be changed too. */ |
90567983 | 614 | static struct lra_static_insn_data debug_bind_static_data = |
c6a6cdaa | 615 | { |
616 | &debug_operand_data, | |
617 | 0, /* Duplication operands #. */ | |
618 | -1, /* Commutative operand #. */ | |
619 | 1, /* Operands #. There is only one operand which is debug RTL | |
620 | expression. */ | |
621 | 0, /* Duplications #. */ | |
622 | 0, /* Alternatives #. We are not interesting in alternatives | |
623 | because we does not proceed debug_insns for reloads. */ | |
624 | NULL, /* Hard registers referenced in machine description. */ | |
625 | NULL /* Descriptions of operands in alternatives. */ | |
626 | }; | |
627 | ||
90567983 | 628 | /* The following data are used as static insn data for all debug |
629 | marker insns. If structure lra_static_insn_data is changed, the | |
630 | initializer should be changed too. */ | |
631 | static struct lra_static_insn_data debug_marker_static_data = | |
632 | { | |
633 | &debug_operand_data, | |
634 | 0, /* Duplication operands #. */ | |
635 | -1, /* Commutative operand #. */ | |
636 | 0, /* Operands #. There isn't any operand. */ | |
637 | 0, /* Duplications #. */ | |
638 | 0, /* Alternatives #. We are not interesting in alternatives | |
639 | because we does not proceed debug_insns for reloads. */ | |
640 | NULL, /* Hard registers referenced in machine description. */ | |
641 | NULL /* Descriptions of operands in alternatives. */ | |
642 | }; | |
643 | ||
c6a6cdaa | 644 | /* Called once per compiler work to initialize some LRA data related |
645 | to insns. */ | |
646 | static void | |
647 | init_insn_code_data_once (void) | |
648 | { | |
649 | memset (insn_code_data, 0, sizeof (insn_code_data)); | |
c6a6cdaa | 650 | } |
651 | ||
652 | /* Called once per compiler work to finalize some LRA data related to | |
653 | insns. */ | |
654 | static void | |
655 | finish_insn_code_data_once (void) | |
656 | { | |
9fdbc432 | 657 | for (unsigned int i = 0; i < NUM_INSN_CODES; i++) |
c6a6cdaa | 658 | { |
659 | if (insn_code_data[i] != NULL) | |
660 | free (insn_code_data[i]); | |
c6a6cdaa | 661 | } |
662 | } | |
663 | ||
c6a6cdaa | 664 | /* Return static insn data, allocate and setup if necessary. Although |
665 | dup_num is static data (it depends only on icode), to set it up we | |
666 | need to extract insn first. So recog_data should be valid for | |
667 | normal insn (ICODE >= 0) before the call. */ | |
668 | static struct lra_static_insn_data * | |
669 | get_static_insn_data (int icode, int nop, int ndup, int nalt) | |
670 | { | |
671 | struct lra_static_insn_data *data; | |
672 | size_t n_bytes; | |
673 | ||
9fdbc432 | 674 | lra_assert (icode < (int) NUM_INSN_CODES); |
c6a6cdaa | 675 | if (icode >= 0 && (data = insn_code_data[icode]) != NULL) |
676 | return data; | |
677 | lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0); | |
678 | n_bytes = sizeof (struct lra_static_insn_data) | |
679 | + sizeof (struct lra_operand_data) * nop | |
680 | + sizeof (int) * ndup; | |
681 | data = XNEWVAR (struct lra_static_insn_data, n_bytes); | |
92b4b904 | 682 | data->operand_alternative = NULL; |
c6a6cdaa | 683 | data->n_operands = nop; |
684 | data->n_dups = ndup; | |
685 | data->n_alternatives = nalt; | |
686 | data->operand = ((struct lra_operand_data *) | |
687 | ((char *) data + sizeof (struct lra_static_insn_data))); | |
688 | data->dup_num = ((int *) ((char *) data->operand | |
689 | + sizeof (struct lra_operand_data) * nop)); | |
690 | if (icode >= 0) | |
691 | { | |
692 | int i; | |
693 | ||
694 | insn_code_data[icode] = data; | |
695 | for (i = 0; i < nop; i++) | |
696 | { | |
697 | data->operand[i].constraint | |
698 | = insn_data[icode].operand[i].constraint; | |
699 | data->operand[i].mode = insn_data[icode].operand[i].mode; | |
700 | data->operand[i].strict_low = insn_data[icode].operand[i].strict_low; | |
701 | data->operand[i].is_operator | |
702 | = insn_data[icode].operand[i].is_operator; | |
703 | data->operand[i].type | |
704 | = (data->operand[i].constraint[0] == '=' ? OP_OUT | |
705 | : data->operand[i].constraint[0] == '+' ? OP_INOUT | |
706 | : OP_IN); | |
707 | data->operand[i].is_address = false; | |
708 | } | |
709 | for (i = 0; i < ndup; i++) | |
710 | data->dup_num[i] = recog_data.dup_num[i]; | |
711 | } | |
712 | return data; | |
713 | } | |
714 | ||
715 | /* The current length of the following array. */ | |
716 | int lra_insn_recog_data_len; | |
717 | ||
718 | /* Map INSN_UID -> the insn recog data (NULL if unknown). */ | |
719 | lra_insn_recog_data_t *lra_insn_recog_data; | |
720 | ||
721 | /* Initialize LRA data about insns. */ | |
722 | static void | |
723 | init_insn_recog_data (void) | |
724 | { | |
725 | lra_insn_recog_data_len = 0; | |
726 | lra_insn_recog_data = NULL; | |
c6a6cdaa | 727 | } |
728 | ||
729 | /* Expand, if necessary, LRA data about insns. */ | |
730 | static void | |
731 | check_and_expand_insn_recog_data (int index) | |
732 | { | |
733 | int i, old; | |
734 | ||
735 | if (lra_insn_recog_data_len > index) | |
736 | return; | |
737 | old = lra_insn_recog_data_len; | |
738 | lra_insn_recog_data_len = index * 3 / 2 + 1; | |
739 | lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t, | |
740 | lra_insn_recog_data, | |
741 | lra_insn_recog_data_len); | |
742 | for (i = old; i < lra_insn_recog_data_len; i++) | |
743 | lra_insn_recog_data[i] = NULL; | |
744 | } | |
745 | ||
746 | /* Finish LRA DATA about insn. */ | |
747 | static void | |
748 | free_insn_recog_data (lra_insn_recog_data_t data) | |
749 | { | |
750 | if (data->operand_loc != NULL) | |
751 | free (data->operand_loc); | |
752 | if (data->dup_loc != NULL) | |
753 | free (data->dup_loc); | |
754 | if (data->arg_hard_regs != NULL) | |
755 | free (data->arg_hard_regs); | |
c6a6cdaa | 756 | if (data->icode < 0 && NONDEBUG_INSN_P (data->insn)) |
757 | { | |
758 | if (data->insn_static_data->operand_alternative != NULL) | |
92b4b904 | 759 | free (const_cast <operand_alternative *> |
760 | (data->insn_static_data->operand_alternative)); | |
c6a6cdaa | 761 | free_insn_regs (data->insn_static_data->hard_regs); |
762 | free (data->insn_static_data); | |
763 | } | |
764 | free_insn_regs (data->regs); | |
765 | data->regs = NULL; | |
766 | free (data); | |
767 | } | |
768 | ||
e16712b1 | 769 | /* Pools for copies. */ |
1dc6c44d | 770 | static object_allocator<lra_copy> lra_copy_pool ("lra copies"); |
e16712b1 | 771 | |
c6a6cdaa | 772 | /* Finish LRA data about all insns. */ |
773 | static void | |
774 | finish_insn_recog_data (void) | |
775 | { | |
776 | int i; | |
777 | lra_insn_recog_data_t data; | |
778 | ||
779 | for (i = 0; i < lra_insn_recog_data_len; i++) | |
780 | if ((data = lra_insn_recog_data[i]) != NULL) | |
781 | free_insn_recog_data (data); | |
782 | finish_insn_regs (); | |
e16712b1 | 783 | lra_copy_pool.release (); |
784 | lra_insn_reg_pool.release (); | |
c6a6cdaa | 785 | free (lra_insn_recog_data); |
786 | } | |
787 | ||
788 | /* Setup info about operands in alternatives of LRA DATA of insn. */ | |
789 | static void | |
92b4b904 | 790 | setup_operand_alternative (lra_insn_recog_data_t data, |
791 | const operand_alternative *op_alt) | |
c6a6cdaa | 792 | { |
92b4b904 | 793 | int i, j, nop, nalt; |
c6a6cdaa | 794 | int icode = data->icode; |
795 | struct lra_static_insn_data *static_data = data->insn_static_data; | |
796 | ||
c6a6cdaa | 797 | static_data->commutative = -1; |
798 | nop = static_data->n_operands; | |
c6a6cdaa | 799 | nalt = static_data->n_alternatives; |
92b4b904 | 800 | static_data->operand_alternative = op_alt; |
c6a6cdaa | 801 | for (i = 0; i < nop; i++) |
802 | { | |
3da302c5 | 803 | static_data->operand[i].early_clobber_alts = 0; |
92b4b904 | 804 | static_data->operand[i].early_clobber = false; |
805 | static_data->operand[i].is_address = false; | |
806 | if (static_data->operand[i].constraint[0] == '%') | |
c6a6cdaa | 807 | { |
92b4b904 | 808 | /* We currently only support one commutative pair of operands. */ |
809 | if (static_data->commutative < 0) | |
810 | static_data->commutative = i; | |
811 | else | |
812 | lra_assert (icode < 0); /* Asm */ | |
813 | /* The last operand should not be marked commutative. */ | |
814 | lra_assert (i != nop - 1); | |
c6a6cdaa | 815 | } |
816 | } | |
92b4b904 | 817 | for (j = 0; j < nalt; j++) |
818 | for (i = 0; i < nop; i++, op_alt++) | |
819 | { | |
820 | static_data->operand[i].early_clobber |= op_alt->earlyclobber; | |
3da302c5 | 821 | if (op_alt->earlyclobber) |
822 | static_data->operand[i].early_clobber_alts |= (alternative_mask) 1 << j; | |
92b4b904 | 823 | static_data->operand[i].is_address |= op_alt->is_address; |
824 | } | |
c6a6cdaa | 825 | } |
826 | ||
827 | /* Recursively process X and collect info about registers, which are | |
828 | not the insn operands, in X with TYPE (in/out/inout) and flag that | |
829 | it is early clobbered in the insn (EARLY_CLOBBER) and add the info | |
830 | to LIST. X is a part of insn given by DATA. Return the result | |
0823eb36 | 831 | list. CLOBBER_HIGH marks if X is a clobber high. */ |
c6a6cdaa | 832 | static struct lra_insn_reg * |
4f1bac7c | 833 | collect_non_operand_hard_regs (rtx_insn *insn, rtx *x, |
834 | lra_insn_recog_data_t data, | |
c6a6cdaa | 835 | struct lra_insn_reg *list, |
0823eb36 | 836 | enum op_type type, bool early_clobber, |
837 | bool clobber_high) | |
c6a6cdaa | 838 | { |
839 | int i, j, regno, last; | |
840 | bool subreg_p; | |
3754d046 | 841 | machine_mode mode; |
c6a6cdaa | 842 | struct lra_insn_reg *curr; |
843 | rtx op = *x; | |
844 | enum rtx_code code = GET_CODE (op); | |
845 | const char *fmt = GET_RTX_FORMAT (code); | |
846 | ||
847 | for (i = 0; i < data->insn_static_data->n_operands; i++) | |
d106f8f5 | 848 | if (! data->insn_static_data->operand[i].is_operator |
849 | && x == data->operand_loc[i]) | |
c6a6cdaa | 850 | /* It is an operand loc. Stop here. */ |
851 | return list; | |
852 | for (i = 0; i < data->insn_static_data->n_dups; i++) | |
853 | if (x == data->dup_loc[i]) | |
854 | /* It is a dup loc. Stop here. */ | |
855 | return list; | |
856 | mode = GET_MODE (op); | |
857 | subreg_p = false; | |
858 | if (code == SUBREG) | |
859 | { | |
081c1d32 | 860 | mode = wider_subreg_mode (op); |
9f2c0e68 | 861 | if (read_modify_subreg_p (op)) |
862 | subreg_p = true; | |
c6a6cdaa | 863 | op = SUBREG_REG (op); |
864 | code = GET_CODE (op); | |
c6a6cdaa | 865 | } |
866 | if (REG_P (op)) | |
867 | { | |
868 | if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER) | |
869 | return list; | |
497ba60f | 870 | /* Process all regs even unallocatable ones as we need info |
871 | about all regs for rematerialization pass. */ | |
16b9e38b | 872 | for (last = end_hard_regno (mode, regno); regno < last; regno++) |
497ba60f | 873 | { |
874 | for (curr = list; curr != NULL; curr = curr->next) | |
875 | if (curr->regno == regno && curr->subreg_p == subreg_p | |
876 | && curr->biggest_mode == mode) | |
c6a6cdaa | 877 | { |
497ba60f | 878 | if (curr->type != type) |
879 | curr->type = OP_INOUT; | |
3da302c5 | 880 | if (early_clobber) |
881 | { | |
882 | curr->early_clobber = true; | |
883 | curr->early_clobber_alts = ALL_ALTERNATIVES; | |
884 | } | |
497ba60f | 885 | break; |
886 | } | |
887 | if (curr == NULL) | |
888 | { | |
f4d3c071 | 889 | /* This is a new hard regno or the info cannot be |
497ba60f | 890 | integrated into the found structure. */ |
c6a6cdaa | 891 | #ifdef STACK_REGS |
497ba60f | 892 | early_clobber |
893 | = (early_clobber | |
894 | /* This clobber is to inform popping floating | |
895 | point stack only. */ | |
896 | && ! (FIRST_STACK_REG <= regno | |
897 | && regno <= LAST_STACK_REG)); | |
c6a6cdaa | 898 | #endif |
497ba60f | 899 | list = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
3da302c5 | 900 | early_clobber, |
0823eb36 | 901 | early_clobber ? ALL_ALTERNATIVES : 0, list, |
902 | clobber_high); | |
497ba60f | 903 | } |
904 | } | |
c6a6cdaa | 905 | return list; |
906 | } | |
907 | switch (code) | |
908 | { | |
909 | case SET: | |
4f1bac7c | 910 | list = collect_non_operand_hard_regs (insn, &SET_DEST (op), data, |
0823eb36 | 911 | list, OP_OUT, false, false); |
4f1bac7c | 912 | list = collect_non_operand_hard_regs (insn, &SET_SRC (op), data, |
0823eb36 | 913 | list, OP_IN, false, false); |
c6a6cdaa | 914 | break; |
915 | case CLOBBER: | |
49f6a314 | 916 | /* We treat clobber of non-operand hard registers as early clobber. */ |
917 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, | |
0823eb36 | 918 | list, OP_OUT, true, false); |
919 | break; | |
920 | case CLOBBER_HIGH: | |
921 | /* Clobber high should always span exactly one register. */ | |
922 | gcc_assert (REG_NREGS (XEXP (op, 0)) == 1); | |
923 | /* We treat clobber of non-operand hard registers as early clobber. */ | |
924 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, | |
925 | list, OP_OUT, true, true); | |
49f6a314 | 926 | break; |
c6a6cdaa | 927 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: |
4f1bac7c | 928 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, |
0823eb36 | 929 | list, OP_INOUT, false, false); |
c6a6cdaa | 930 | break; |
931 | case PRE_MODIFY: case POST_MODIFY: | |
4f1bac7c | 932 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 0), data, |
0823eb36 | 933 | list, OP_INOUT, false, false); |
4f1bac7c | 934 | list = collect_non_operand_hard_regs (insn, &XEXP (op, 1), data, |
0823eb36 | 935 | list, OP_IN, false, false); |
c6a6cdaa | 936 | break; |
937 | default: | |
938 | fmt = GET_RTX_FORMAT (code); | |
939 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
940 | { | |
941 | if (fmt[i] == 'e') | |
4f1bac7c | 942 | list = collect_non_operand_hard_regs (insn, &XEXP (op, i), data, |
0823eb36 | 943 | list, OP_IN, false, false); |
c6a6cdaa | 944 | else if (fmt[i] == 'E') |
945 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
4f1bac7c | 946 | list = collect_non_operand_hard_regs (insn, &XVECEXP (op, i, j), |
0823eb36 | 947 | data, list, OP_IN, false, |
948 | false); | |
c6a6cdaa | 949 | } |
950 | } | |
951 | return list; | |
952 | } | |
953 | ||
954 | /* Set up and return info about INSN. Set up the info if it is not set up | |
955 | yet. */ | |
956 | lra_insn_recog_data_t | |
7f836b57 | 957 | lra_set_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 958 | { |
959 | lra_insn_recog_data_t data; | |
960 | int i, n, icode; | |
961 | rtx **locs; | |
962 | unsigned int uid = INSN_UID (insn); | |
963 | struct lra_static_insn_data *insn_static_data; | |
964 | ||
965 | check_and_expand_insn_recog_data (uid); | |
966 | if (DEBUG_INSN_P (insn)) | |
967 | icode = -1; | |
968 | else | |
969 | { | |
970 | icode = INSN_CODE (insn); | |
971 | if (icode < 0) | |
972 | /* It might be a new simple insn which is not recognized yet. */ | |
973 | INSN_CODE (insn) = icode = recog_memoized (insn); | |
974 | } | |
975 | data = XNEW (struct lra_insn_recog_data); | |
976 | lra_insn_recog_data[uid] = data; | |
977 | data->insn = insn; | |
71d47a14 | 978 | data->used_insn_alternative = LRA_UNKNOWN_ALT; |
c6a6cdaa | 979 | data->icode = icode; |
980 | data->regs = NULL; | |
981 | if (DEBUG_INSN_P (insn)) | |
982 | { | |
c6a6cdaa | 983 | data->dup_loc = NULL; |
984 | data->arg_hard_regs = NULL; | |
e1a797ad | 985 | data->preferred_alternatives = ALL_ALTERNATIVES; |
90567983 | 986 | if (DEBUG_BIND_INSN_P (insn)) |
987 | { | |
988 | data->insn_static_data = &debug_bind_static_data; | |
989 | data->operand_loc = XNEWVEC (rtx *, 1); | |
990 | data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn); | |
991 | } | |
992 | else if (DEBUG_MARKER_INSN_P (insn)) | |
993 | { | |
994 | data->insn_static_data = &debug_marker_static_data; | |
995 | data->operand_loc = NULL; | |
996 | } | |
c6a6cdaa | 997 | return data; |
998 | } | |
999 | if (icode < 0) | |
1000 | { | |
92b4b904 | 1001 | int nop, nalt; |
3754d046 | 1002 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 1003 | const char *constraints[MAX_RECOG_OPERANDS]; |
1004 | ||
1005 | nop = asm_noperands (PATTERN (insn)); | |
1006 | data->operand_loc = data->dup_loc = NULL; | |
92b4b904 | 1007 | nalt = 1; |
c6a6cdaa | 1008 | if (nop < 0) |
73a18f44 | 1009 | { |
150967ab | 1010 | /* It is a special insn like USE or CLOBBER. We should |
73a18f44 | 1011 | recognize any regular insn otherwise LRA can do nothing |
1012 | with this insn. */ | |
1013 | gcc_assert (GET_CODE (PATTERN (insn)) == USE | |
1014 | || GET_CODE (PATTERN (insn)) == CLOBBER | |
1015 | || GET_CODE (PATTERN (insn)) == ASM_INPUT); | |
1016 | data->insn_static_data = insn_static_data | |
92b4b904 | 1017 | = get_static_insn_data (-1, 0, 0, nalt); |
73a18f44 | 1018 | } |
c6a6cdaa | 1019 | else |
1020 | { | |
1021 | /* expand_asm_operands makes sure there aren't too many | |
1022 | operands. */ | |
1023 | lra_assert (nop <= MAX_RECOG_OPERANDS); | |
1024 | if (nop != 0) | |
1025 | data->operand_loc = XNEWVEC (rtx *, nop); | |
1026 | /* Now get the operand values and constraints out of the | |
1027 | insn. */ | |
1028 | decode_asm_operands (PATTERN (insn), NULL, | |
1029 | data->operand_loc, | |
1030 | constraints, operand_mode, NULL); | |
c6a6cdaa | 1031 | if (nop > 0) |
1032 | { | |
1033 | const char *p = recog_data.constraints[0]; | |
1a8f8886 | 1034 | |
c6a6cdaa | 1035 | for (p = constraints[0]; *p; p++) |
92b4b904 | 1036 | nalt += *p == ','; |
c6a6cdaa | 1037 | } |
1038 | data->insn_static_data = insn_static_data | |
92b4b904 | 1039 | = get_static_insn_data (-1, nop, 0, nalt); |
c6a6cdaa | 1040 | for (i = 0; i < nop; i++) |
1041 | { | |
1042 | insn_static_data->operand[i].mode = operand_mode[i]; | |
1043 | insn_static_data->operand[i].constraint = constraints[i]; | |
1044 | insn_static_data->operand[i].strict_low = false; | |
1045 | insn_static_data->operand[i].is_operator = false; | |
1046 | insn_static_data->operand[i].is_address = false; | |
1047 | } | |
1048 | } | |
1049 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1050 | insn_static_data->operand[i].type | |
1051 | = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1052 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1053 | : OP_IN); | |
e1a797ad | 1054 | data->preferred_alternatives = ALL_ALTERNATIVES; |
92b4b904 | 1055 | if (nop > 0) |
1056 | { | |
1057 | operand_alternative *op_alt = XCNEWVEC (operand_alternative, | |
1058 | nalt * nop); | |
afca8a73 | 1059 | preprocess_constraints (nop, nalt, constraints, op_alt, |
1060 | data->operand_loc); | |
92b4b904 | 1061 | setup_operand_alternative (data, op_alt); |
1062 | } | |
c6a6cdaa | 1063 | } |
1064 | else | |
1065 | { | |
1066 | insn_extract (insn); | |
1067 | data->insn_static_data = insn_static_data | |
1068 | = get_static_insn_data (icode, insn_data[icode].n_operands, | |
1069 | insn_data[icode].n_dups, | |
1070 | insn_data[icode].n_alternatives); | |
1071 | n = insn_static_data->n_operands; | |
1072 | if (n == 0) | |
1073 | locs = NULL; | |
1074 | else | |
1075 | { | |
1076 | locs = XNEWVEC (rtx *, n); | |
1077 | memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *)); | |
1078 | } | |
1079 | data->operand_loc = locs; | |
1080 | n = insn_static_data->n_dups; | |
1081 | if (n == 0) | |
1082 | locs = NULL; | |
1083 | else | |
1084 | { | |
1085 | locs = XNEWVEC (rtx *, n); | |
1086 | memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *)); | |
1087 | } | |
1088 | data->dup_loc = locs; | |
e1a797ad | 1089 | data->preferred_alternatives = get_preferred_alternatives (insn); |
92b4b904 | 1090 | const operand_alternative *op_alt = preprocess_insn_constraints (icode); |
1091 | if (!insn_static_data->operand_alternative) | |
1092 | setup_operand_alternative (data, op_alt); | |
1093 | else if (op_alt != insn_static_data->operand_alternative) | |
1094 | insn_static_data->operand_alternative = op_alt; | |
c6a6cdaa | 1095 | } |
1096 | if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE) | |
1097 | insn_static_data->hard_regs = NULL; | |
1098 | else | |
1099 | insn_static_data->hard_regs | |
4f1bac7c | 1100 | = collect_non_operand_hard_regs (insn, &PATTERN (insn), data, |
0823eb36 | 1101 | NULL, OP_IN, false, false); |
c6a6cdaa | 1102 | data->arg_hard_regs = NULL; |
1103 | if (CALL_P (insn)) | |
1104 | { | |
853a01d6 | 1105 | bool use_p; |
c6a6cdaa | 1106 | rtx link; |
1107 | int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER]; | |
1108 | ||
1109 | n_hard_regs = 0; | |
1110 | /* Finding implicit hard register usage. We believe it will be | |
1111 | not changed whatever transformations are used. Call insns | |
1112 | are such example. */ | |
1113 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1114 | link != NULL_RTX; | |
1115 | link = XEXP (link, 1)) | |
853a01d6 | 1116 | if (((use_p = GET_CODE (XEXP (link, 0)) == USE) |
1117 | || GET_CODE (XEXP (link, 0)) == CLOBBER) | |
c6a6cdaa | 1118 | && REG_P (XEXP (XEXP (link, 0), 0))) |
1119 | { | |
1120 | regno = REGNO (XEXP (XEXP (link, 0), 0)); | |
1121 | lra_assert (regno < FIRST_PSEUDO_REGISTER); | |
1122 | /* It is an argument register. */ | |
0933f1d9 | 1123 | for (i = REG_NREGS (XEXP (XEXP (link, 0), 0)) - 1; i >= 0; i--) |
853a01d6 | 1124 | arg_hard_regs[n_hard_regs++] |
1125 | = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER); | |
c6a6cdaa | 1126 | } |
0823eb36 | 1127 | else if (GET_CODE (XEXP (link, 0)) == CLOBBER_HIGH) |
1128 | /* We could support CLOBBER_HIGH and treat it in the same way as | |
1129 | HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */ | |
1130 | gcc_unreachable (); | |
1131 | ||
c6a6cdaa | 1132 | if (n_hard_regs != 0) |
1133 | { | |
1134 | arg_hard_regs[n_hard_regs++] = -1; | |
1135 | data->arg_hard_regs = XNEWVEC (int, n_hard_regs); | |
1136 | memcpy (data->arg_hard_regs, arg_hard_regs, | |
1137 | sizeof (int) * n_hard_regs); | |
1138 | } | |
1139 | } | |
1140 | /* Some output operand can be recognized only from the context not | |
1141 | from the constraints which are empty in this case. Call insn may | |
1142 | contain a hard register in set destination with empty constraint | |
1143 | and extract_insn treats them as an input. */ | |
1144 | for (i = 0; i < insn_static_data->n_operands; i++) | |
1145 | { | |
1146 | int j; | |
1147 | rtx pat, set; | |
1148 | struct lra_operand_data *operand = &insn_static_data->operand[i]; | |
1149 | ||
1150 | /* ??? Should we treat 'X' the same way. It looks to me that | |
1151 | 'X' means anything and empty constraint means we do not | |
1152 | care. */ | |
1153 | if (operand->type != OP_IN || *operand->constraint != '\0' | |
1154 | || operand->is_operator) | |
1155 | continue; | |
1156 | pat = PATTERN (insn); | |
1157 | if (GET_CODE (pat) == SET) | |
1158 | { | |
1159 | if (data->operand_loc[i] != &SET_DEST (pat)) | |
1160 | continue; | |
1161 | } | |
1162 | else if (GET_CODE (pat) == PARALLEL) | |
1163 | { | |
1164 | for (j = XVECLEN (pat, 0) - 1; j >= 0; j--) | |
1165 | { | |
1166 | set = XVECEXP (PATTERN (insn), 0, j); | |
1167 | if (GET_CODE (set) == SET | |
1168 | && &SET_DEST (set) == data->operand_loc[i]) | |
1169 | break; | |
1170 | } | |
1171 | if (j < 0) | |
1172 | continue; | |
1173 | } | |
1174 | else | |
1175 | continue; | |
1176 | operand->type = OP_OUT; | |
1177 | } | |
1178 | return data; | |
1179 | } | |
1180 | ||
1181 | /* Return info about insn give by UID. The info should be already set | |
1182 | up. */ | |
1183 | static lra_insn_recog_data_t | |
1184 | get_insn_recog_data_by_uid (int uid) | |
1185 | { | |
1186 | lra_insn_recog_data_t data; | |
1187 | ||
1188 | data = lra_insn_recog_data[uid]; | |
1189 | lra_assert (data != NULL); | |
1190 | return data; | |
1191 | } | |
1192 | ||
1193 | /* Invalidate all info about insn given by its UID. */ | |
1194 | static void | |
1195 | invalidate_insn_recog_data (int uid) | |
1196 | { | |
1197 | lra_insn_recog_data_t data; | |
1198 | ||
1199 | data = lra_insn_recog_data[uid]; | |
1200 | lra_assert (data != NULL); | |
1201 | free_insn_recog_data (data); | |
1202 | lra_insn_recog_data[uid] = NULL; | |
1203 | } | |
1204 | ||
1205 | /* Update all the insn info about INSN. It is usually called when | |
1206 | something in the insn was changed. Return the updated info. */ | |
1207 | lra_insn_recog_data_t | |
7f836b57 | 1208 | lra_update_insn_recog_data (rtx_insn *insn) |
c6a6cdaa | 1209 | { |
1210 | lra_insn_recog_data_t data; | |
1211 | int n; | |
1212 | unsigned int uid = INSN_UID (insn); | |
1213 | struct lra_static_insn_data *insn_static_data; | |
a4686d0a | 1214 | poly_int64 sp_offset = 0; |
1a8f8886 | 1215 | |
c6a6cdaa | 1216 | check_and_expand_insn_recog_data (uid); |
1217 | if ((data = lra_insn_recog_data[uid]) != NULL | |
1218 | && data->icode != INSN_CODE (insn)) | |
1219 | { | |
3b3a5e5f | 1220 | sp_offset = data->sp_offset; |
c6a6cdaa | 1221 | invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn)); |
1222 | invalidate_insn_recog_data (uid); | |
1223 | data = NULL; | |
1224 | } | |
1225 | if (data == NULL) | |
3b3a5e5f | 1226 | { |
1227 | data = lra_get_insn_recog_data (insn); | |
1228 | /* Initiate or restore SP offset. */ | |
1229 | data->sp_offset = sp_offset; | |
1230 | return data; | |
1231 | } | |
c6a6cdaa | 1232 | insn_static_data = data->insn_static_data; |
71d47a14 | 1233 | data->used_insn_alternative = LRA_UNKNOWN_ALT; |
c6a6cdaa | 1234 | if (DEBUG_INSN_P (insn)) |
1235 | return data; | |
1236 | if (data->icode < 0) | |
1237 | { | |
1238 | int nop; | |
3754d046 | 1239 | machine_mode operand_mode[MAX_RECOG_OPERANDS]; |
c6a6cdaa | 1240 | const char *constraints[MAX_RECOG_OPERANDS]; |
1241 | ||
1242 | nop = asm_noperands (PATTERN (insn)); | |
1243 | if (nop >= 0) | |
1244 | { | |
1245 | lra_assert (nop == data->insn_static_data->n_operands); | |
1246 | /* Now get the operand values and constraints out of the | |
1247 | insn. */ | |
1248 | decode_asm_operands (PATTERN (insn), NULL, | |
1249 | data->operand_loc, | |
1250 | constraints, operand_mode, NULL); | |
c6a6cdaa | 1251 | |
382ecba7 | 1252 | if (flag_checking) |
1253 | for (int i = 0; i < nop; i++) | |
c6a6cdaa | 1254 | lra_assert |
1255 | (insn_static_data->operand[i].mode == operand_mode[i] | |
1256 | && insn_static_data->operand[i].constraint == constraints[i] | |
1257 | && ! insn_static_data->operand[i].is_operator); | |
c6a6cdaa | 1258 | } |
c6a6cdaa | 1259 | |
382ecba7 | 1260 | if (flag_checking) |
1261 | for (int i = 0; i < insn_static_data->n_operands; i++) | |
c6a6cdaa | 1262 | lra_assert |
1263 | (insn_static_data->operand[i].type | |
1264 | == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT | |
1265 | : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT | |
1266 | : OP_IN)); | |
c6a6cdaa | 1267 | } |
1268 | else | |
1269 | { | |
1270 | insn_extract (insn); | |
1271 | n = insn_static_data->n_operands; | |
1272 | if (n != 0) | |
1273 | memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *)); | |
1274 | n = insn_static_data->n_dups; | |
1275 | if (n != 0) | |
1276 | memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *)); | |
e1a797ad | 1277 | lra_assert (check_bool_attrs (insn)); |
c6a6cdaa | 1278 | } |
1279 | return data; | |
1280 | } | |
1281 | ||
1282 | /* Set up that INSN is using alternative ALT now. */ | |
1283 | void | |
7f836b57 | 1284 | lra_set_used_insn_alternative (rtx_insn *insn, int alt) |
c6a6cdaa | 1285 | { |
1286 | lra_insn_recog_data_t data; | |
1287 | ||
1288 | data = lra_get_insn_recog_data (insn); | |
1289 | data->used_insn_alternative = alt; | |
1290 | } | |
1291 | ||
1292 | /* Set up that insn with UID is using alternative ALT now. The insn | |
1293 | info should be already set up. */ | |
1294 | void | |
1295 | lra_set_used_insn_alternative_by_uid (int uid, int alt) | |
1296 | { | |
1297 | lra_insn_recog_data_t data; | |
1298 | ||
1299 | check_and_expand_insn_recog_data (uid); | |
1300 | data = lra_insn_recog_data[uid]; | |
1301 | lra_assert (data != NULL); | |
1302 | data->used_insn_alternative = alt; | |
1303 | } | |
1304 | ||
1305 | \f | |
1306 | ||
1307 | /* This page contains code dealing with common register info and | |
1308 | pseudo copies. */ | |
1309 | ||
1310 | /* The size of the following array. */ | |
1311 | static int reg_info_size; | |
1312 | /* Common info about each register. */ | |
1313 | struct lra_reg *lra_reg_info; | |
1314 | ||
95f18d43 | 1315 | HARD_REG_SET hard_regs_spilled_into; |
1316 | ||
c6a6cdaa | 1317 | /* Last register value. */ |
1318 | static int last_reg_value; | |
1319 | ||
1320 | /* Return new register value. */ | |
1321 | static int | |
1322 | get_new_reg_value (void) | |
1323 | { | |
1324 | return ++last_reg_value; | |
1325 | } | |
1326 | ||
c6a6cdaa | 1327 | /* Vec referring to pseudo copies. */ |
f1f41a6c | 1328 | static vec<lra_copy_t> copy_vec; |
c6a6cdaa | 1329 | |
1330 | /* Initialize I-th element of lra_reg_info. */ | |
1331 | static inline void | |
1332 | initialize_lra_reg_info_element (int i) | |
1333 | { | |
1334 | bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack); | |
1335 | #ifdef STACK_REGS | |
1336 | lra_reg_info[i].no_stack_p = false; | |
1337 | #endif | |
1338 | CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs); | |
f2cc6708 | 1339 | CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set); |
c6a6cdaa | 1340 | lra_reg_info[i].preferred_hard_regno1 = -1; |
1341 | lra_reg_info[i].preferred_hard_regno2 = -1; | |
1342 | lra_reg_info[i].preferred_hard_regno_profit1 = 0; | |
1343 | lra_reg_info[i].preferred_hard_regno_profit2 = 0; | |
fc8a0f60 | 1344 | lra_reg_info[i].biggest_mode = VOIDmode; |
c6a6cdaa | 1345 | lra_reg_info[i].live_ranges = NULL; |
1346 | lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0; | |
1347 | lra_reg_info[i].last_reload = 0; | |
ab4ea053 | 1348 | lra_reg_info[i].restore_rtx = NULL_RTX; |
c6a6cdaa | 1349 | lra_reg_info[i].val = get_new_reg_value (); |
a1064490 | 1350 | lra_reg_info[i].offset = 0; |
c6a6cdaa | 1351 | lra_reg_info[i].copies = NULL; |
5c62f29a | 1352 | lra_reg_info[i].call_insn = NULL; |
c6a6cdaa | 1353 | } |
1354 | ||
1355 | /* Initialize common reg info and copies. */ | |
1356 | static void | |
1357 | init_reg_info (void) | |
1358 | { | |
1359 | int i; | |
1360 | ||
1361 | last_reg_value = 0; | |
1362 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1363 | lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size); | |
1364 | for (i = 0; i < reg_info_size; i++) | |
1365 | initialize_lra_reg_info_element (i); | |
c45ca67d | 1366 | copy_vec.truncate (0); |
95f18d43 | 1367 | CLEAR_HARD_REG_SET (hard_regs_spilled_into); |
c6a6cdaa | 1368 | } |
1369 | ||
1370 | ||
1371 | /* Finish common reg info and copies. */ | |
1372 | static void | |
1373 | finish_reg_info (void) | |
1374 | { | |
1375 | int i; | |
1376 | ||
1377 | for (i = 0; i < reg_info_size; i++) | |
1378 | bitmap_clear (&lra_reg_info[i].insn_bitmap); | |
1379 | free (lra_reg_info); | |
1380 | reg_info_size = 0; | |
c6a6cdaa | 1381 | } |
1382 | ||
1383 | /* Expand common reg info if it is necessary. */ | |
1384 | static void | |
1385 | expand_reg_info (void) | |
1386 | { | |
1387 | int i, old = reg_info_size; | |
1388 | ||
1389 | if (reg_info_size > max_reg_num ()) | |
1390 | return; | |
1391 | reg_info_size = max_reg_num () * 3 / 2 + 1; | |
1392 | lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size); | |
1393 | for (i = old; i < reg_info_size; i++) | |
1394 | initialize_lra_reg_info_element (i); | |
1395 | } | |
1396 | ||
1397 | /* Free all copies. */ | |
1398 | void | |
1399 | lra_free_copies (void) | |
1400 | { | |
1401 | lra_copy_t cp; | |
1402 | ||
f1f41a6c | 1403 | while (copy_vec.length () != 0) |
c6a6cdaa | 1404 | { |
f1f41a6c | 1405 | cp = copy_vec.pop (); |
c6a6cdaa | 1406 | lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL; |
e16712b1 | 1407 | lra_copy_pool.remove (cp); |
c6a6cdaa | 1408 | } |
1409 | } | |
1410 | ||
1411 | /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution | |
1412 | frequency is FREQ. */ | |
1413 | void | |
1414 | lra_create_copy (int regno1, int regno2, int freq) | |
1415 | { | |
1416 | bool regno1_dest_p; | |
1417 | lra_copy_t cp; | |
1418 | ||
1419 | lra_assert (regno1 != regno2); | |
1420 | regno1_dest_p = true; | |
1421 | if (regno1 > regno2) | |
1422 | { | |
a4f59596 | 1423 | std::swap (regno1, regno2); |
c6a6cdaa | 1424 | regno1_dest_p = false; |
c6a6cdaa | 1425 | } |
e16712b1 | 1426 | cp = lra_copy_pool.allocate (); |
f1f41a6c | 1427 | copy_vec.safe_push (cp); |
c6a6cdaa | 1428 | cp->regno1_dest_p = regno1_dest_p; |
1429 | cp->freq = freq; | |
1430 | cp->regno1 = regno1; | |
1431 | cp->regno2 = regno2; | |
1432 | cp->regno1_next = lra_reg_info[regno1].copies; | |
1433 | lra_reg_info[regno1].copies = cp; | |
1434 | cp->regno2_next = lra_reg_info[regno2].copies; | |
1435 | lra_reg_info[regno2].copies = cp; | |
1436 | if (lra_dump_file != NULL) | |
1437 | fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n", | |
1438 | regno1, regno1_dest_p ? "<-" : "->", regno2, freq); | |
1439 | } | |
1440 | ||
1441 | /* Return N-th (0, 1, ...) copy. If there is no copy, return | |
1442 | NULL. */ | |
1443 | lra_copy_t | |
1444 | lra_get_copy (int n) | |
1445 | { | |
f1f41a6c | 1446 | if (n >= (int) copy_vec.length ()) |
c6a6cdaa | 1447 | return NULL; |
f1f41a6c | 1448 | return copy_vec[n]; |
c6a6cdaa | 1449 | } |
1450 | ||
1451 | \f | |
1452 | ||
1453 | /* This page contains code dealing with info about registers in | |
1454 | insns. */ | |
1455 | ||
4f1bac7c | 1456 | /* Process X of INSN recursively and add info (operand type is |
c6a6cdaa | 1457 | given by TYPE, flag of that it is early clobber is EARLY_CLOBBER) |
3da302c5 | 1458 | about registers in X to the insn DATA. If X can be early clobbered, |
1459 | alternatives in which it can be early clobbered are given by | |
1460 | EARLY_CLOBBER_ALTS. */ | |
c6a6cdaa | 1461 | static void |
4f1bac7c | 1462 | add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, |
1463 | rtx_insn *insn, | |
3da302c5 | 1464 | enum op_type type, bool early_clobber, |
1465 | alternative_mask early_clobber_alts) | |
c6a6cdaa | 1466 | { |
1467 | int i, j, regno; | |
1468 | bool subreg_p; | |
3754d046 | 1469 | machine_mode mode; |
c6a6cdaa | 1470 | const char *fmt; |
1471 | enum rtx_code code; | |
1472 | struct lra_insn_reg *curr; | |
1473 | ||
1474 | code = GET_CODE (x); | |
1475 | mode = GET_MODE (x); | |
1476 | subreg_p = false; | |
1477 | if (GET_CODE (x) == SUBREG) | |
1478 | { | |
081c1d32 | 1479 | mode = wider_subreg_mode (x); |
9f2c0e68 | 1480 | if (read_modify_subreg_p (x)) |
1481 | subreg_p = true; | |
c6a6cdaa | 1482 | x = SUBREG_REG (x); |
1483 | code = GET_CODE (x); | |
c6a6cdaa | 1484 | } |
1485 | if (REG_P (x)) | |
1486 | { | |
1487 | regno = REGNO (x); | |
497ba60f | 1488 | /* Process all regs even unallocatable ones as we need info about |
1489 | all regs for rematerialization pass. */ | |
c6a6cdaa | 1490 | expand_reg_info (); |
4f1bac7c | 1491 | if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, INSN_UID (insn))) |
c6a6cdaa | 1492 | { |
40cec44a | 1493 | data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, |
3da302c5 | 1494 | early_clobber, early_clobber_alts, |
0823eb36 | 1495 | data->regs, false); |
c6a6cdaa | 1496 | return; |
1497 | } | |
1498 | else | |
1499 | { | |
1500 | for (curr = data->regs; curr != NULL; curr = curr->next) | |
1501 | if (curr->regno == regno) | |
1502 | { | |
1503 | if (curr->subreg_p != subreg_p || curr->biggest_mode != mode) | |
f4d3c071 | 1504 | /* The info cannot be integrated into the found |
c6a6cdaa | 1505 | structure. */ |
40cec44a | 1506 | data->regs = new_insn_reg (data->insn, regno, type, mode, |
1507 | subreg_p, early_clobber, | |
0823eb36 | 1508 | early_clobber_alts, data->regs, |
1509 | false); | |
c6a6cdaa | 1510 | else |
1511 | { | |
1512 | if (curr->type != type) | |
1513 | curr->type = OP_INOUT; | |
1514 | if (curr->early_clobber != early_clobber) | |
1515 | curr->early_clobber = true; | |
3da302c5 | 1516 | curr->early_clobber_alts |= early_clobber_alts; |
c6a6cdaa | 1517 | } |
1518 | return; | |
1519 | } | |
1520 | gcc_unreachable (); | |
1521 | } | |
1522 | } | |
1523 | ||
1524 | switch (code) | |
1525 | { | |
1526 | case SET: | |
4f1bac7c | 1527 | add_regs_to_insn_regno_info (data, SET_DEST (x), insn, OP_OUT, false, 0); |
1528 | add_regs_to_insn_regno_info (data, SET_SRC (x), insn, OP_IN, false, 0); | |
c6a6cdaa | 1529 | break; |
1530 | case CLOBBER: | |
1bdd07cb | 1531 | /* We treat clobber of non-operand hard registers as early |
1532 | clobber. */ | |
1533 | add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_OUT, | |
1534 | true, ALL_ALTERNATIVES); | |
1535 | break; | |
0823eb36 | 1536 | case CLOBBER_HIGH: |
1537 | gcc_unreachable (); | |
c6a6cdaa | 1538 | case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: |
4f1bac7c | 1539 | add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0); |
c6a6cdaa | 1540 | break; |
1541 | case PRE_MODIFY: case POST_MODIFY: | |
4f1bac7c | 1542 | add_regs_to_insn_regno_info (data, XEXP (x, 0), insn, OP_INOUT, false, 0); |
1543 | add_regs_to_insn_regno_info (data, XEXP (x, 1), insn, OP_IN, false, 0); | |
c6a6cdaa | 1544 | break; |
1545 | default: | |
1546 | if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT) | |
1547 | /* Some targets place small structures in registers for return | |
1548 | values of functions, and those registers are wrapped in | |
1549 | PARALLEL that we may see as the destination of a SET. Here | |
1550 | is an example: | |
1551 | ||
1552 | (call_insn 13 12 14 2 (set (parallel:BLK [ | |
1553 | (expr_list:REG_DEP_TRUE (reg:DI 0 ax) | |
1554 | (const_int 0 [0])) | |
1555 | (expr_list:REG_DEP_TRUE (reg:DI 1 dx) | |
1556 | (const_int 8 [0x8])) | |
1557 | ]) | |
1558 | (call (mem:QI (symbol_ref:DI (... */ | |
1559 | type = OP_IN; | |
1560 | fmt = GET_RTX_FORMAT (code); | |
1561 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1562 | { | |
1563 | if (fmt[i] == 'e') | |
4f1bac7c | 1564 | add_regs_to_insn_regno_info (data, XEXP (x, i), insn, type, false, 0); |
c6a6cdaa | 1565 | else if (fmt[i] == 'E') |
1566 | { | |
1567 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
4f1bac7c | 1568 | add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), insn, |
3da302c5 | 1569 | type, false, 0); |
c6a6cdaa | 1570 | } |
1571 | } | |
1572 | } | |
1573 | } | |
1574 | ||
1575 | /* Return execution frequency of INSN. */ | |
1576 | static int | |
7f836b57 | 1577 | get_insn_freq (rtx_insn *insn) |
c6a6cdaa | 1578 | { |
91f71fa3 | 1579 | basic_block bb = BLOCK_FOR_INSN (insn); |
c6a6cdaa | 1580 | |
91f71fa3 | 1581 | gcc_checking_assert (bb != NULL); |
1582 | return REG_FREQ_FROM_BB (bb); | |
c6a6cdaa | 1583 | } |
1584 | ||
1585 | /* Invalidate all reg info of INSN with DATA and execution frequency | |
1586 | FREQ. Update common info about the invalidated registers. */ | |
1587 | static void | |
7f836b57 | 1588 | invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn, |
c6a6cdaa | 1589 | int freq) |
1590 | { | |
1591 | int uid; | |
1592 | bool debug_p; | |
1593 | unsigned int i; | |
1594 | struct lra_insn_reg *ir, *next_ir; | |
1595 | ||
1596 | uid = INSN_UID (insn); | |
1597 | debug_p = DEBUG_INSN_P (insn); | |
1598 | for (ir = data->regs; ir != NULL; ir = next_ir) | |
1599 | { | |
1600 | i = ir->regno; | |
1601 | next_ir = ir->next; | |
e16712b1 | 1602 | lra_insn_reg_pool.remove (ir); |
c6a6cdaa | 1603 | bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid); |
1604 | if (i >= FIRST_PSEUDO_REGISTER && ! debug_p) | |
1605 | { | |
1606 | lra_reg_info[i].nrefs--; | |
1607 | lra_reg_info[i].freq -= freq; | |
1608 | lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0); | |
1609 | } | |
1610 | } | |
1611 | data->regs = NULL; | |
1612 | } | |
1613 | ||
1614 | /* Invalidate all reg info of INSN. Update common info about the | |
1615 | invalidated registers. */ | |
1616 | void | |
7f836b57 | 1617 | lra_invalidate_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1618 | { |
1619 | invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn, | |
1620 | get_insn_freq (insn)); | |
1621 | } | |
1622 | ||
1623 | /* Update common reg info from reg info of insn given by its DATA and | |
1624 | execution frequency FREQ. */ | |
1625 | static void | |
1626 | setup_insn_reg_info (lra_insn_recog_data_t data, int freq) | |
1627 | { | |
1628 | unsigned int i; | |
1629 | struct lra_insn_reg *ir; | |
1630 | ||
1631 | for (ir = data->regs; ir != NULL; ir = ir->next) | |
1632 | if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER) | |
1633 | { | |
1634 | lra_reg_info[i].nrefs++; | |
1635 | lra_reg_info[i].freq += freq; | |
1636 | } | |
1637 | } | |
1638 | ||
1639 | /* Set up insn reg info of INSN. Update common reg info from reg info | |
1640 | of INSN. */ | |
1641 | void | |
7f836b57 | 1642 | lra_update_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1643 | { |
4f1bac7c | 1644 | int i, freq; |
c6a6cdaa | 1645 | lra_insn_recog_data_t data; |
1646 | struct lra_static_insn_data *static_data; | |
1647 | enum rtx_code code; | |
70ae5dc6 | 1648 | rtx link; |
1649 | ||
c6a6cdaa | 1650 | if (! INSN_P (insn)) |
1651 | return; | |
1652 | data = lra_get_insn_recog_data (insn); | |
1653 | static_data = data->insn_static_data; | |
90567983 | 1654 | freq = NONDEBUG_INSN_P (insn) ? get_insn_freq (insn) : 0; |
c6a6cdaa | 1655 | invalidate_insn_data_regno_info (data, insn, freq); |
c6a6cdaa | 1656 | for (i = static_data->n_operands - 1; i >= 0; i--) |
4f1bac7c | 1657 | add_regs_to_insn_regno_info (data, *data->operand_loc[i], insn, |
c6a6cdaa | 1658 | static_data->operand[i].type, |
3da302c5 | 1659 | static_data->operand[i].early_clobber, |
1660 | static_data->operand[i].early_clobber_alts); | |
c6a6cdaa | 1661 | if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE) |
4f1bac7c | 1662 | add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), insn, |
3da302c5 | 1663 | code == USE ? OP_IN : OP_OUT, false, 0); |
70ae5dc6 | 1664 | if (CALL_P (insn)) |
1665 | /* On some targets call insns can refer to pseudos in memory in | |
1666 | CALL_INSN_FUNCTION_USAGE list. Process them in order to | |
1667 | consider their occurrences in calls for different | |
1668 | transformations (e.g. inheritance) with given pseudos. */ | |
1669 | for (link = CALL_INSN_FUNCTION_USAGE (insn); | |
1670 | link != NULL_RTX; | |
1671 | link = XEXP (link, 1)) | |
0823eb36 | 1672 | { |
1673 | code = GET_CODE (XEXP (link, 0)); | |
1674 | /* We could support CLOBBER_HIGH and treat it in the same way as | |
1675 | HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */ | |
1676 | gcc_assert (code != CLOBBER_HIGH); | |
1677 | if ((code == USE || code == CLOBBER) | |
1678 | && MEM_P (XEXP (XEXP (link, 0), 0))) | |
1679 | add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), insn, | |
1680 | code == USE ? OP_IN : OP_OUT, false, 0); | |
1681 | } | |
c6a6cdaa | 1682 | if (NONDEBUG_INSN_P (insn)) |
1683 | setup_insn_reg_info (data, freq); | |
1684 | } | |
1685 | ||
1686 | /* Return reg info of insn given by it UID. */ | |
1687 | struct lra_insn_reg * | |
1688 | lra_get_insn_regs (int uid) | |
1689 | { | |
1690 | lra_insn_recog_data_t data; | |
1691 | ||
1692 | data = get_insn_recog_data_by_uid (uid); | |
1693 | return data->regs; | |
1694 | } | |
1695 | ||
1696 | \f | |
1697 | ||
ab4ea053 | 1698 | /* Recursive hash function for RTL X. */ |
1699 | hashval_t | |
1700 | lra_rtx_hash (rtx x) | |
1701 | { | |
1702 | int i, j; | |
1703 | enum rtx_code code; | |
1704 | const char *fmt; | |
1705 | hashval_t val = 0; | |
1706 | ||
1707 | if (x == 0) | |
1708 | return val; | |
1709 | ||
1710 | code = GET_CODE (x); | |
1711 | val += (int) code + 4095; | |
1712 | ||
1713 | /* Some RTL can be compared nonrecursively. */ | |
1714 | switch (code) | |
1715 | { | |
1716 | case REG: | |
1717 | return val + REGNO (x); | |
1718 | ||
1719 | case LABEL_REF: | |
1720 | return iterative_hash_object (XEXP (x, 0), val); | |
1721 | ||
1722 | case SYMBOL_REF: | |
1723 | return iterative_hash_object (XSTR (x, 0), val); | |
1724 | ||
1725 | case SCRATCH: | |
1726 | case CONST_DOUBLE: | |
ab4ea053 | 1727 | case CONST_VECTOR: |
1728 | return val; | |
1729 | ||
b555c94f | 1730 | case CONST_INT: |
1731 | return val + UINTVAL (x); | |
1732 | ||
ab4ea053 | 1733 | default: |
1734 | break; | |
1735 | } | |
1736 | ||
1737 | /* Hash the elements. */ | |
1738 | fmt = GET_RTX_FORMAT (code); | |
1739 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1740 | { | |
1741 | switch (fmt[i]) | |
1742 | { | |
1743 | case 'w': | |
1744 | val += XWINT (x, i); | |
1745 | break; | |
1746 | ||
1747 | case 'n': | |
1748 | case 'i': | |
1749 | val += XINT (x, i); | |
1750 | break; | |
1751 | ||
1752 | case 'V': | |
1753 | case 'E': | |
1754 | val += XVECLEN (x, i); | |
1755 | ||
1756 | for (j = 0; j < XVECLEN (x, i); j++) | |
1757 | val += lra_rtx_hash (XVECEXP (x, i, j)); | |
1758 | break; | |
1759 | ||
1760 | case 'e': | |
1761 | val += lra_rtx_hash (XEXP (x, i)); | |
1762 | break; | |
1763 | ||
1764 | case 'S': | |
1765 | case 's': | |
1766 | val += htab_hash_string (XSTR (x, i)); | |
1767 | break; | |
1768 | ||
1769 | case 'u': | |
1770 | case '0': | |
1771 | case 't': | |
1772 | break; | |
1773 | ||
1774 | /* It is believed that rtx's at this level will never | |
1775 | contain anything but integers and other rtx's, except for | |
1776 | within LABEL_REFs and SYMBOL_REFs. */ | |
1777 | default: | |
1778 | abort (); | |
1779 | } | |
1780 | } | |
1781 | return val; | |
1782 | } | |
1783 | ||
1784 | \f | |
1785 | ||
c6a6cdaa | 1786 | /* This page contains code dealing with stack of the insns which |
1787 | should be processed by the next constraint pass. */ | |
1788 | ||
1789 | /* Bitmap used to put an insn on the stack only in one exemplar. */ | |
1790 | static sbitmap lra_constraint_insn_stack_bitmap; | |
1791 | ||
1792 | /* The stack itself. */ | |
7f836b57 | 1793 | vec<rtx_insn *> lra_constraint_insn_stack; |
c6a6cdaa | 1794 | |
1795 | /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg | |
1796 | info for INSN, otherwise only update it if INSN is not already on the | |
1797 | stack. */ | |
1798 | static inline void | |
7f836b57 | 1799 | lra_push_insn_1 (rtx_insn *insn, bool always_update) |
c6a6cdaa | 1800 | { |
1801 | unsigned int uid = INSN_UID (insn); | |
1802 | if (always_update) | |
1803 | lra_update_insn_regno_info (insn); | |
1804 | if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap)) | |
1805 | lra_constraint_insn_stack_bitmap = | |
1806 | sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0); | |
08b7917c | 1807 | if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid)) |
c6a6cdaa | 1808 | return; |
08b7917c | 1809 | bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid); |
c6a6cdaa | 1810 | if (! always_update) |
1811 | lra_update_insn_regno_info (insn); | |
f1f41a6c | 1812 | lra_constraint_insn_stack.safe_push (insn); |
c6a6cdaa | 1813 | } |
1814 | ||
1815 | /* Put INSN on the stack. */ | |
1816 | void | |
7f836b57 | 1817 | lra_push_insn (rtx_insn *insn) |
c6a6cdaa | 1818 | { |
1819 | lra_push_insn_1 (insn, false); | |
1820 | } | |
1821 | ||
1822 | /* Put INSN on the stack and update its reg info. */ | |
1823 | void | |
7f836b57 | 1824 | lra_push_insn_and_update_insn_regno_info (rtx_insn *insn) |
c6a6cdaa | 1825 | { |
1826 | lra_push_insn_1 (insn, true); | |
1827 | } | |
1828 | ||
1829 | /* Put insn with UID on the stack. */ | |
1830 | void | |
1831 | lra_push_insn_by_uid (unsigned int uid) | |
1832 | { | |
1833 | lra_push_insn (lra_insn_recog_data[uid]->insn); | |
1834 | } | |
1835 | ||
1836 | /* Take the last-inserted insns off the stack and return it. */ | |
7f836b57 | 1837 | rtx_insn * |
c6a6cdaa | 1838 | lra_pop_insn (void) |
1839 | { | |
7f836b57 | 1840 | rtx_insn *insn = lra_constraint_insn_stack.pop (); |
08b7917c | 1841 | bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn)); |
c6a6cdaa | 1842 | return insn; |
1843 | } | |
1844 | ||
1845 | /* Return the current size of the insn stack. */ | |
1846 | unsigned int | |
1847 | lra_insn_stack_length (void) | |
1848 | { | |
f1f41a6c | 1849 | return lra_constraint_insn_stack.length (); |
c6a6cdaa | 1850 | } |
1851 | ||
1852 | /* Push insns FROM to TO (excluding it) going in reverse order. */ | |
1853 | static void | |
7f836b57 | 1854 | push_insns (rtx_insn *from, rtx_insn *to) |
c6a6cdaa | 1855 | { |
7f836b57 | 1856 | rtx_insn *insn; |
c6a6cdaa | 1857 | |
1858 | if (from == NULL_RTX) | |
1859 | return; | |
1860 | for (insn = from; insn != to; insn = PREV_INSN (insn)) | |
1861 | if (INSN_P (insn)) | |
1862 | lra_push_insn (insn); | |
1863 | } | |
1864 | ||
3b3a5e5f | 1865 | /* Set up sp offset for insn in range [FROM, LAST]. The offset is |
1866 | taken from the next BB insn after LAST or zero if there in such | |
1867 | insn. */ | |
1868 | static void | |
7f836b57 | 1869 | setup_sp_offset (rtx_insn *from, rtx_insn *last) |
3b3a5e5f | 1870 | { |
18fc6357 | 1871 | rtx_insn *before = next_nonnote_nondebug_insn_bb (last); |
a4686d0a | 1872 | poly_int64 offset = (before == NULL_RTX || ! INSN_P (before) |
1873 | ? 0 : lra_get_insn_recog_data (before)->sp_offset); | |
3b3a5e5f | 1874 | |
7f836b57 | 1875 | for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn)) |
3b3a5e5f | 1876 | lra_get_insn_recog_data (insn)->sp_offset = offset; |
1877 | } | |
1878 | ||
c6a6cdaa | 1879 | /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the |
1880 | insns onto the stack. Print about emitting the insns with | |
1881 | TITLE. */ | |
1882 | void | |
7f836b57 | 1883 | lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after, |
1884 | const char *title) | |
c6a6cdaa | 1885 | { |
7f836b57 | 1886 | rtx_insn *last; |
c6a6cdaa | 1887 | |
3b3a5e5f | 1888 | if (before == NULL_RTX && after == NULL_RTX) |
1889 | return; | |
1890 | if (lra_dump_file != NULL) | |
c6a6cdaa | 1891 | { |
6dde9719 | 1892 | dump_insn_slim (lra_dump_file, insn); |
c6a6cdaa | 1893 | if (before != NULL_RTX) |
1894 | { | |
1895 | fprintf (lra_dump_file," %s before:\n", title); | |
4cd001d5 | 1896 | dump_rtl_slim (lra_dump_file, before, NULL, -1, 0); |
c6a6cdaa | 1897 | } |
1898 | if (after != NULL_RTX) | |
1899 | { | |
1900 | fprintf (lra_dump_file, " %s after:\n", title); | |
4cd001d5 | 1901 | dump_rtl_slim (lra_dump_file, after, NULL, -1, 0); |
c6a6cdaa | 1902 | } |
1903 | fprintf (lra_dump_file, "\n"); | |
1904 | } | |
1905 | if (before != NULL_RTX) | |
1906 | { | |
743d9602 | 1907 | if (cfun->can_throw_non_call_exceptions) |
1908 | copy_reg_eh_region_note_forward (insn, before, NULL); | |
c6a6cdaa | 1909 | emit_insn_before (before, insn); |
1910 | push_insns (PREV_INSN (insn), PREV_INSN (before)); | |
3b3a5e5f | 1911 | setup_sp_offset (before, PREV_INSN (insn)); |
c6a6cdaa | 1912 | } |
1913 | if (after != NULL_RTX) | |
1914 | { | |
743d9602 | 1915 | if (cfun->can_throw_non_call_exceptions) |
1916 | copy_reg_eh_region_note_forward (insn, after, NULL); | |
c6a6cdaa | 1917 | for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last)) |
1918 | ; | |
1919 | emit_insn_after (after, insn); | |
1920 | push_insns (last, insn); | |
3b3a5e5f | 1921 | setup_sp_offset (after, last); |
c6a6cdaa | 1922 | } |
743d9602 | 1923 | if (cfun->can_throw_non_call_exceptions) |
1924 | { | |
1925 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
1926 | if (note && !insn_could_throw_p (insn)) | |
1927 | remove_note (insn, note); | |
1928 | } | |
c6a6cdaa | 1929 | } |
c6a6cdaa | 1930 | \f |
1931 | ||
8c0d01a4 | 1932 | /* Replace all references to register OLD_REGNO in *LOC with pseudo |
06072e79 | 1933 | register NEW_REG. Try to simplify subreg of constant if SUBREG_P. |
d686eece | 1934 | DEBUG_P is if LOC is within a DEBUG_INSN. Return true if any |
1935 | change was made. */ | |
8c0d01a4 | 1936 | bool |
d686eece | 1937 | lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p, |
1938 | bool debug_p) | |
8c0d01a4 | 1939 | { |
1940 | rtx x = *loc; | |
1941 | bool result = false; | |
1942 | enum rtx_code code; | |
1943 | const char *fmt; | |
1944 | int i, j; | |
1945 | ||
1946 | if (x == NULL_RTX) | |
1947 | return false; | |
1948 | ||
1949 | code = GET_CODE (x); | |
06072e79 | 1950 | if (code == SUBREG && subreg_p) |
8c0d01a4 | 1951 | { |
06072e79 | 1952 | rtx subst, inner = SUBREG_REG (x); |
1953 | /* Transform subreg of constant while we still have inner mode | |
1954 | of the subreg. The subreg internal should not be an insn | |
1955 | operand. */ | |
1956 | if (REG_P (inner) && (int) REGNO (inner) == old_regno | |
1957 | && CONSTANT_P (new_reg) | |
1958 | && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner), | |
1959 | SUBREG_BYTE (x))) != NULL_RTX) | |
1960 | { | |
1961 | *loc = subst; | |
1962 | return true; | |
1963 | } | |
1964 | ||
1965 | } | |
1966 | else if (code == REG && (int) REGNO (x) == old_regno) | |
1967 | { | |
1968 | machine_mode mode = GET_MODE (x); | |
8c0d01a4 | 1969 | machine_mode inner_mode = GET_MODE (new_reg); |
1970 | ||
c77a06af | 1971 | if (mode != inner_mode |
198a0ce9 | 1972 | && ! (CONST_SCALAR_INT_P (new_reg) && SCALAR_INT_MODE_P (mode))) |
8c0d01a4 | 1973 | { |
d686eece | 1974 | poly_uint64 offset = 0; |
1975 | if (partial_subreg_p (mode, inner_mode) | |
1976 | && SCALAR_INT_MODE_P (inner_mode)) | |
1977 | offset = subreg_lowpart_offset (mode, inner_mode); | |
1978 | if (debug_p) | |
1979 | new_reg = gen_rtx_raw_SUBREG (mode, new_reg, offset); | |
8c0d01a4 | 1980 | else |
d686eece | 1981 | new_reg = gen_rtx_SUBREG (mode, new_reg, offset); |
8c0d01a4 | 1982 | } |
1983 | *loc = new_reg; | |
1984 | return true; | |
1985 | } | |
1986 | ||
1987 | /* Scan all the operand sub-expressions. */ | |
1988 | fmt = GET_RTX_FORMAT (code); | |
1989 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1990 | { | |
1991 | if (fmt[i] == 'e') | |
1992 | { | |
06072e79 | 1993 | if (lra_substitute_pseudo (&XEXP (x, i), old_regno, |
d686eece | 1994 | new_reg, subreg_p, debug_p)) |
8c0d01a4 | 1995 | result = true; |
1996 | } | |
1997 | else if (fmt[i] == 'E') | |
1998 | { | |
1999 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
06072e79 | 2000 | if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno, |
d686eece | 2001 | new_reg, subreg_p, debug_p)) |
8c0d01a4 | 2002 | result = true; |
2003 | } | |
2004 | } | |
2005 | return result; | |
2006 | } | |
2007 | ||
06072e79 | 2008 | /* Call lra_substitute_pseudo within an insn. Try to simplify subreg |
2009 | of constant if SUBREG_P. This won't update the insn ptr, just the | |
2010 | contents of the insn. */ | |
8c0d01a4 | 2011 | bool |
06072e79 | 2012 | lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno, |
2013 | rtx new_reg, bool subreg_p) | |
8c0d01a4 | 2014 | { |
2015 | rtx loc = insn; | |
d686eece | 2016 | return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p, |
2017 | DEBUG_INSN_P (insn)); | |
8c0d01a4 | 2018 | } |
2019 | ||
2020 | \f | |
2021 | ||
c6a6cdaa | 2022 | /* This page contains code dealing with scratches (changing them onto |
2023 | pseudos and restoring them from the pseudos). | |
2024 | ||
2025 | We change scratches into pseudos at the beginning of LRA to | |
2026 | simplify dealing with them (conflicts, hard register assignments). | |
2027 | ||
2028 | If the pseudo denoting scratch was spilled it means that we do need | |
2029 | a hard register for it. Such pseudos are transformed back to | |
2030 | scratches at the end of LRA. */ | |
2031 | ||
2032 | /* Description of location of a former scratch operand. */ | |
453f1a8c | 2033 | struct sloc |
c6a6cdaa | 2034 | { |
7f836b57 | 2035 | rtx_insn *insn; /* Insn where the scratch was. */ |
c6a6cdaa | 2036 | int nop; /* Number of the operand which was a scratch. */ |
95f61091 | 2037 | int icode; /* Original icode from which scratch was removed. */ |
c6a6cdaa | 2038 | }; |
2039 | ||
453f1a8c | 2040 | typedef struct sloc *sloc_t; |
c6a6cdaa | 2041 | |
c6a6cdaa | 2042 | /* Locations of the former scratches. */ |
f1f41a6c | 2043 | static vec<sloc_t> scratches; |
c6a6cdaa | 2044 | |
2045 | /* Bitmap of scratch regnos. */ | |
2046 | static bitmap_head scratch_bitmap; | |
2047 | ||
2048 | /* Bitmap of scratch operands. */ | |
2049 | static bitmap_head scratch_operand_bitmap; | |
2050 | ||
2051 | /* Return true if pseudo REGNO is made of SCRATCH. */ | |
2052 | bool | |
2053 | lra_former_scratch_p (int regno) | |
2054 | { | |
2055 | return bitmap_bit_p (&scratch_bitmap, regno); | |
2056 | } | |
2057 | ||
2058 | /* Return true if the operand NOP of INSN is a former scratch. */ | |
2059 | bool | |
7f836b57 | 2060 | lra_former_scratch_operand_p (rtx_insn *insn, int nop) |
c6a6cdaa | 2061 | { |
2062 | return bitmap_bit_p (&scratch_operand_bitmap, | |
2063 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0; | |
2064 | } | |
2065 | ||
fb87313e | 2066 | /* Register operand NOP in INSN as a former scratch. It will be |
2067 | changed to scratch back, if it is necessary, at the LRA end. */ | |
2068 | void | |
95f61091 | 2069 | lra_register_new_scratch_op (rtx_insn *insn, int nop, int icode) |
fb87313e | 2070 | { |
2071 | lra_insn_recog_data_t id = lra_get_insn_recog_data (insn); | |
2072 | rtx op = *id->operand_loc[nop]; | |
2073 | sloc_t loc = XNEW (struct sloc); | |
2074 | lra_assert (REG_P (op)); | |
2075 | loc->insn = insn; | |
2076 | loc->nop = nop; | |
95f61091 | 2077 | loc->icode = icode; |
fb87313e | 2078 | scratches.safe_push (loc); |
2079 | bitmap_set_bit (&scratch_bitmap, REGNO (op)); | |
2080 | bitmap_set_bit (&scratch_operand_bitmap, | |
2081 | INSN_UID (insn) * MAX_RECOG_OPERANDS + nop); | |
2082 | add_reg_note (insn, REG_UNUSED, op); | |
2083 | } | |
2084 | ||
409a6c36 | 2085 | /* Change INSN's scratches into pseudos and save their location. */ |
c6a6cdaa | 2086 | static void |
409a6c36 | 2087 | remove_scratches_1 (rtx_insn *insn) |
c6a6cdaa | 2088 | { |
2089 | int i; | |
2090 | bool insn_changed_p; | |
7f836b57 | 2091 | rtx reg; |
c6a6cdaa | 2092 | lra_insn_recog_data_t id; |
2093 | struct lra_static_insn_data *static_id; | |
2094 | ||
409a6c36 | 2095 | id = lra_get_insn_recog_data (insn); |
2096 | static_id = id->insn_static_data; | |
2097 | insn_changed_p = false; | |
2098 | for (i = 0; i < static_id->n_operands; i++) | |
2099 | if (GET_CODE (*id->operand_loc[i]) == SCRATCH | |
2100 | && GET_MODE (*id->operand_loc[i]) != VOIDmode) | |
2101 | { | |
2102 | insn_changed_p = true; | |
2103 | *id->operand_loc[i] = reg | |
2104 | = lra_create_new_reg (static_id->operand[i].mode, | |
2105 | *id->operand_loc[i], ALL_REGS, NULL); | |
2106 | lra_register_new_scratch_op (insn, i, id->icode); | |
2107 | if (lra_dump_file != NULL) | |
2108 | fprintf (lra_dump_file, | |
2109 | "Removing SCRATCH in insn #%u (nop %d)\n", | |
2110 | INSN_UID (insn), i); | |
2111 | } | |
2112 | if (insn_changed_p) | |
2113 | /* Because we might use DF right after caller-saves sub-pass | |
2114 | we need to keep DF info up to date. */ | |
2115 | df_insn_rescan (insn); | |
2116 | } | |
2117 | ||
2118 | /* Change scratches into pseudos and save their location. */ | |
2119 | static void | |
2120 | remove_scratches (void) | |
2121 | { | |
2122 | basic_block bb; | |
2123 | rtx_insn *insn; | |
2124 | ||
f1f41a6c | 2125 | scratches.create (get_max_uid ()); |
c6a6cdaa | 2126 | bitmap_initialize (&scratch_bitmap, ®_obstack); |
2127 | bitmap_initialize (&scratch_operand_bitmap, ®_obstack); | |
fc00614f | 2128 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2129 | FOR_BB_INSNS (bb, insn) |
2130 | if (INSN_P (insn)) | |
409a6c36 | 2131 | remove_scratches_1 (insn); |
c6a6cdaa | 2132 | } |
2133 | ||
2134 | /* Changes pseudos created by function remove_scratches onto scratches. */ | |
2135 | static void | |
2136 | restore_scratches (void) | |
2137 | { | |
f1f41a6c | 2138 | int regno; |
2139 | unsigned i; | |
453f1a8c | 2140 | sloc_t loc; |
7f836b57 | 2141 | rtx_insn *last = NULL; |
c6a6cdaa | 2142 | lra_insn_recog_data_t id = NULL; |
2143 | ||
f1f41a6c | 2144 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 2145 | { |
2715f63a | 2146 | /* Ignore already deleted insns. */ |
2147 | if (NOTE_P (loc->insn) | |
2148 | && NOTE_KIND (loc->insn) == NOTE_INSN_DELETED) | |
2149 | continue; | |
c6a6cdaa | 2150 | if (last != loc->insn) |
2151 | { | |
2152 | last = loc->insn; | |
2153 | id = lra_get_insn_recog_data (last); | |
2154 | } | |
95f61091 | 2155 | if (loc->icode != id->icode) |
2156 | { | |
2157 | /* The icode doesn't match, which means the insn has been modified | |
2158 | (e.g. register elimination). The scratch cannot be restored. */ | |
2159 | continue; | |
2160 | } | |
c6a6cdaa | 2161 | if (REG_P (*id->operand_loc[loc->nop]) |
2162 | && ((regno = REGNO (*id->operand_loc[loc->nop])) | |
2163 | >= FIRST_PSEUDO_REGISTER) | |
2164 | && lra_get_regno_hard_regno (regno) < 0) | |
2165 | { | |
2166 | /* It should be only case when scratch register with chosen | |
2167 | constraint 'X' did not get memory or hard register. */ | |
2168 | lra_assert (lra_former_scratch_p (regno)); | |
2169 | *id->operand_loc[loc->nop] | |
2170 | = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop])); | |
2171 | lra_update_dup (id, loc->nop); | |
2172 | if (lra_dump_file != NULL) | |
2173 | fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n", | |
2174 | INSN_UID (loc->insn), loc->nop); | |
2175 | } | |
2176 | } | |
f1f41a6c | 2177 | for (i = 0; scratches.iterate (i, &loc); i++) |
c6a6cdaa | 2178 | free (loc); |
f1f41a6c | 2179 | scratches.release (); |
c6a6cdaa | 2180 | bitmap_clear (&scratch_bitmap); |
2181 | bitmap_clear (&scratch_operand_bitmap); | |
2182 | } | |
2183 | ||
2184 | \f | |
2185 | ||
c6a6cdaa | 2186 | /* Function checks RTL for correctness. If FINAL_P is true, it is |
2187 | done at the end of LRA and the check is more rigorous. */ | |
2188 | static void | |
2189 | check_rtl (bool final_p) | |
2190 | { | |
c6a6cdaa | 2191 | basic_block bb; |
7f836b57 | 2192 | rtx_insn *insn; |
c6a6cdaa | 2193 | |
2194 | lra_assert (! final_p || reload_completed); | |
fc00614f | 2195 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2196 | FOR_BB_INSNS (bb, insn) |
2197 | if (NONDEBUG_INSN_P (insn) | |
2198 | && GET_CODE (PATTERN (insn)) != USE | |
2199 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
c6a6cdaa | 2200 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) |
2201 | { | |
2202 | if (final_p) | |
2203 | { | |
835b8178 | 2204 | extract_constrain_insn (insn); |
c6a6cdaa | 2205 | continue; |
2206 | } | |
cba8c2e6 | 2207 | /* LRA code is based on assumption that all addresses can be |
2208 | correctly decomposed. LRA can generate reloads for | |
2209 | decomposable addresses. The decomposition code checks the | |
2210 | correctness of the addresses. So we don't need to check | |
76f778fd | 2211 | the addresses here. Don't call insn_invalid_p here, it can |
2212 | change the code at this stage. */ | |
2213 | if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0) | |
c6a6cdaa | 2214 | fatal_insn_not_found (insn); |
c6a6cdaa | 2215 | } |
2216 | } | |
c6a6cdaa | 2217 | |
2218 | /* Determine if the current function has an exception receiver block | |
2219 | that reaches the exit block via non-exceptional edges */ | |
2220 | static bool | |
2221 | has_nonexceptional_receiver (void) | |
2222 | { | |
2223 | edge e; | |
2224 | edge_iterator ei; | |
2225 | basic_block *tos, *worklist, bb; | |
2226 | ||
2227 | /* If we're not optimizing, then just err on the safe side. */ | |
2228 | if (!optimize) | |
2229 | return true; | |
1a8f8886 | 2230 | |
c6a6cdaa | 2231 | /* First determine which blocks can reach exit via normal paths. */ |
a28770e1 | 2232 | tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); |
c6a6cdaa | 2233 | |
fc00614f | 2234 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2235 | bb->flags &= ~BB_REACHABLE; |
2236 | ||
2237 | /* Place the exit block on our worklist. */ | |
34154e27 | 2238 | EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; |
2239 | *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); | |
1a8f8886 | 2240 | |
c6a6cdaa | 2241 | /* Iterate: find everything reachable from what we've already seen. */ |
2242 | while (tos != worklist) | |
2243 | { | |
2244 | bb = *--tos; | |
2245 | ||
2246 | FOR_EACH_EDGE (e, ei, bb->preds) | |
2247 | if (e->flags & EDGE_ABNORMAL) | |
2248 | { | |
2249 | free (worklist); | |
2250 | return true; | |
2251 | } | |
2252 | else | |
2253 | { | |
2254 | basic_block src = e->src; | |
2255 | ||
2256 | if (!(src->flags & BB_REACHABLE)) | |
2257 | { | |
2258 | src->flags |= BB_REACHABLE; | |
2259 | *tos++ = src; | |
2260 | } | |
2261 | } | |
2262 | } | |
2263 | free (worklist); | |
2264 | /* No exceptional block reached exit unexceptionally. */ | |
2265 | return false; | |
2266 | } | |
2267 | ||
c6a6cdaa | 2268 | |
2269 | /* Process recursively X of INSN and add REG_INC notes if necessary. */ | |
2270 | static void | |
7f836b57 | 2271 | add_auto_inc_notes (rtx_insn *insn, rtx x) |
c6a6cdaa | 2272 | { |
2273 | enum rtx_code code = GET_CODE (x); | |
2274 | const char *fmt; | |
2275 | int i, j; | |
2276 | ||
2277 | if (code == MEM && auto_inc_p (XEXP (x, 0))) | |
2278 | { | |
2279 | add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); | |
2280 | return; | |
2281 | } | |
2282 | ||
2283 | /* Scan all X sub-expressions. */ | |
2284 | fmt = GET_RTX_FORMAT (code); | |
2285 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2286 | { | |
2287 | if (fmt[i] == 'e') | |
2288 | add_auto_inc_notes (insn, XEXP (x, i)); | |
2289 | else if (fmt[i] == 'E') | |
2290 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
2291 | add_auto_inc_notes (insn, XVECEXP (x, i, j)); | |
2292 | } | |
2293 | } | |
2294 | ||
c6a6cdaa | 2295 | |
2296 | /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC. | |
2297 | We change pseudos by hard registers without notification of DF and | |
2298 | that can make the notes obsolete. DF-infrastructure does not deal | |
2299 | with REG_INC notes -- so we should regenerate them here. */ | |
2300 | static void | |
2301 | update_inc_notes (void) | |
2302 | { | |
2303 | rtx *pnote; | |
2304 | basic_block bb; | |
7f836b57 | 2305 | rtx_insn *insn; |
c6a6cdaa | 2306 | |
fc00614f | 2307 | FOR_EACH_BB_FN (bb, cfun) |
c6a6cdaa | 2308 | FOR_BB_INSNS (bb, insn) |
2309 | if (NONDEBUG_INSN_P (insn)) | |
2310 | { | |
2311 | pnote = ®_NOTES (insn); | |
2312 | while (*pnote != 0) | |
2313 | { | |
e2ca76ac | 2314 | if (REG_NOTE_KIND (*pnote) == REG_DEAD |
2315 | || REG_NOTE_KIND (*pnote) == REG_UNUSED | |
2316 | || REG_NOTE_KIND (*pnote) == REG_INC) | |
c6a6cdaa | 2317 | *pnote = XEXP (*pnote, 1); |
2318 | else | |
2319 | pnote = &XEXP (*pnote, 1); | |
2320 | } | |
32aa77d9 | 2321 | |
2322 | if (AUTO_INC_DEC) | |
2323 | add_auto_inc_notes (insn, PATTERN (insn)); | |
c6a6cdaa | 2324 | } |
2325 | } | |
2326 | ||
2327 | /* Set to 1 while in lra. */ | |
2328 | int lra_in_progress; | |
2329 | ||
edfb1d8f | 2330 | /* Start of pseudo regnos before the LRA. */ |
2331 | int lra_new_regno_start; | |
2332 | ||
1a8f8886 | 2333 | /* Start of reload pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2334 | int lra_constraint_new_regno_start; |
2335 | ||
0f7b6a0d | 2336 | /* Avoid spilling pseudos with regno more than the following value if |
2337 | it is possible. */ | |
2338 | int lra_bad_spill_regno_start; | |
2339 | ||
1a8f8886 | 2340 | /* Inheritance pseudo regnos before the new spill pass. */ |
c6a6cdaa | 2341 | bitmap_head lra_inheritance_pseudos; |
2342 | ||
1a8f8886 | 2343 | /* Split regnos before the new spill pass. */ |
c6a6cdaa | 2344 | bitmap_head lra_split_regs; |
2345 | ||
2fbe7a32 | 2346 | /* Reload pseudo regnos before the new assignment pass which still can |
2347 | be spilled after the assignment pass as memory is also accepted in | |
1f3a048a | 2348 | insns for the reload pseudos. */ |
c6a6cdaa | 2349 | bitmap_head lra_optional_reload_pseudos; |
2350 | ||
1f3a048a | 2351 | /* Pseudo regnos used for subreg reloads before the new assignment |
2fbe7a32 | 2352 | pass. Such pseudos still can be spilled after the assignment |
1f3a048a | 2353 | pass. */ |
2354 | bitmap_head lra_subreg_reload_pseudos; | |
2355 | ||
c6a6cdaa | 2356 | /* File used for output of LRA debug information. */ |
2357 | FILE *lra_dump_file; | |
2358 | ||
3923c63e | 2359 | /* True if we found an asm error. */ |
2360 | bool lra_asm_error_p; | |
2361 | ||
c6a6cdaa | 2362 | /* True if we should try spill into registers of different classes |
2363 | instead of memory. */ | |
2364 | bool lra_reg_spill_p; | |
2365 | ||
2366 | /* Set up value LRA_REG_SPILL_P. */ | |
2367 | static void | |
2368 | setup_reg_spill_flag (void) | |
2369 | { | |
2370 | int cl, mode; | |
2371 | ||
2372 | if (targetm.spill_class != NULL) | |
2373 | for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++) | |
2374 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
2375 | if (targetm.spill_class ((enum reg_class) cl, | |
3754d046 | 2376 | (machine_mode) mode) != NO_REGS) |
c6a6cdaa | 2377 | { |
2378 | lra_reg_spill_p = true; | |
2379 | return; | |
2380 | } | |
2381 | lra_reg_spill_p = false; | |
2382 | } | |
2383 | ||
2384 | /* True if the current function is too big to use regular algorithms | |
2385 | in LRA. In other words, we should use simpler and faster algorithms | |
2386 | in LRA. It also means we should not worry about generation code | |
2387 | for caller saves. The value is set up in IRA. */ | |
2388 | bool lra_simple_p; | |
2389 | ||
2390 | /* Major LRA entry function. F is a file should be used to dump LRA | |
2391 | debug info. */ | |
2392 | void | |
2393 | lra (FILE *f) | |
2394 | { | |
2395 | int i; | |
9628978f | 2396 | bool live_p, inserted_p; |
c6a6cdaa | 2397 | |
2398 | lra_dump_file = f; | |
3923c63e | 2399 | lra_asm_error_p = false; |
2400 | ||
c6a6cdaa | 2401 | timevar_push (TV_LRA); |
2402 | ||
ea99c7a1 | 2403 | /* Make sure that the last insn is a note. Some subsequent passes |
2404 | need it. */ | |
2405 | emit_note (NOTE_INSN_DELETED); | |
2406 | ||
fc8a0f60 | 2407 | COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs); |
2408 | ||
b85cafd3 | 2409 | init_reg_info (); |
2410 | expand_reg_info (); | |
2411 | ||
c6a6cdaa | 2412 | init_insn_recog_data (); |
2413 | ||
76f778fd | 2414 | /* Some quick check on RTL generated by previous passes. */ |
382ecba7 | 2415 | if (flag_checking) |
2416 | check_rtl (false); | |
c6a6cdaa | 2417 | |
76f778fd | 2418 | lra_in_progress = 1; |
2419 | ||
f95727ee | 2420 | lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0; |
2421 | lra_assignment_iter = lra_assignment_iter_after_spill = 0; | |
c6a6cdaa | 2422 | lra_inheritance_iter = lra_undo_inheritance_iter = 0; |
fa4f0b4e | 2423 | lra_rematerialization_iter = 0; |
c6a6cdaa | 2424 | |
2425 | setup_reg_spill_flag (); | |
2426 | ||
c6a6cdaa | 2427 | /* Function remove_scratches can creates new pseudos for clobbers -- |
2428 | so set up lra_constraint_new_regno_start before its call to | |
2429 | permit changing reg classes for pseudos created by this | |
2430 | simplification. */ | |
edfb1d8f | 2431 | lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num (); |
0f7b6a0d | 2432 | lra_bad_spill_regno_start = INT_MAX; |
c6a6cdaa | 2433 | remove_scratches (); |
c6a6cdaa | 2434 | |
2435 | /* A function that has a non-local label that can reach the exit | |
2436 | block via non-exceptional paths must save all call-saved | |
2437 | registers. */ | |
2438 | if (cfun->has_nonlocal_label && has_nonexceptional_receiver ()) | |
2439 | crtl->saves_all_registers = 1; | |
2440 | ||
2441 | if (crtl->saves_all_registers) | |
2442 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
2443 | if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) | |
2444 | df_set_regs_ever_live (i, true); | |
2445 | ||
2446 | /* We don't DF from now and avoid its using because it is to | |
2447 | expensive when a lot of RTL changes are made. */ | |
2448 | df_set_flags (DF_NO_INSN_RESCAN); | |
f1f41a6c | 2449 | lra_constraint_insn_stack.create (get_max_uid ()); |
c6a6cdaa | 2450 | lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ()); |
53c5d9d4 | 2451 | bitmap_clear (lra_constraint_insn_stack_bitmap); |
c6a6cdaa | 2452 | lra_live_ranges_init (); |
2453 | lra_constraints_init (); | |
2454 | lra_curr_reload_num = 0; | |
7f836b57 | 2455 | push_insns (get_last_insn (), NULL); |
c6a6cdaa | 2456 | /* It is needed for the 1st coalescing. */ |
c6a6cdaa | 2457 | bitmap_initialize (&lra_inheritance_pseudos, ®_obstack); |
2458 | bitmap_initialize (&lra_split_regs, ®_obstack); | |
2459 | bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack); | |
1f3a048a | 2460 | bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack); |
c6a6cdaa | 2461 | live_p = false; |
85aa2f28 | 2462 | if (maybe_ne (get_frame_size (), 0) && crtl->stack_alignment_needed) |
ea99c7a1 | 2463 | /* If we have a stack frame, we must align it now. The stack size |
2464 | may be a part of the offset computation for register | |
2465 | elimination. */ | |
2466 | assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); | |
61cd3e57 | 2467 | lra_init_equiv (); |
c6a6cdaa | 2468 | for (;;) |
2469 | { | |
2470 | for (;;) | |
2471 | { | |
f15d85a5 | 2472 | bool reloads_p = lra_constraints (lra_constraint_iter == 0); |
c6a6cdaa | 2473 | /* Constraint transformations may result in that eliminable |
2474 | hard regs become uneliminable and pseudos which use them | |
2475 | should be spilled. It is better to do it before pseudo | |
2476 | assignments. | |
2477 | ||
2478 | For example, rs6000 can make | |
2479 | RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started | |
2480 | to use a constant pool. */ | |
3b3a5e5f | 2481 | lra_eliminate (false, false); |
f15d85a5 | 2482 | /* We should try to assign hard registers to scratches even |
2483 | if there were no RTL transformations in lra_constraints. | |
2484 | Also we should check IRA assignments on the first | |
2485 | iteration as they can be wrong because of early clobbers | |
2486 | operands which are ignored in IRA. */ | |
2487 | if (! reloads_p && lra_constraint_iter > 1) | |
2488 | { | |
2489 | /* Stack is not empty here only when there are changes | |
2490 | during the elimination sub-pass. */ | |
2491 | if (bitmap_empty_p (lra_constraint_insn_stack_bitmap)) | |
2492 | break; | |
2493 | else | |
2494 | /* If there are no reloads but changing due | |
2495 | elimination, restart the constraint sub-pass | |
2496 | first. */ | |
2497 | continue; | |
2498 | } | |
c6a6cdaa | 2499 | /* Do inheritance only for regular algorithms. */ |
2500 | if (! lra_simple_p) | |
f2cc6708 | 2501 | { |
fcf56aaf | 2502 | if (flag_ipa_ra) |
f2cc6708 | 2503 | { |
2504 | if (live_p) | |
2505 | lra_clear_live_ranges (); | |
2506 | /* As a side-effect of lra_create_live_ranges, we calculate | |
2507 | actual_call_used_reg_set, which is needed during | |
2508 | lra_inheritance. */ | |
04472658 | 2509 | lra_create_live_ranges (true, true); |
2045f87a | 2510 | live_p = true; |
f2cc6708 | 2511 | } |
2512 | lra_inheritance (); | |
2513 | } | |
d3d0b390 | 2514 | if (live_p) |
2515 | lra_clear_live_ranges (); | |
6a4bc24e | 2516 | bool fails_p; |
2517 | do | |
c6a6cdaa | 2518 | { |
6a4bc24e | 2519 | /* We need live ranges for lra_assign -- so build them. |
2520 | But don't remove dead insns or change global live | |
2521 | info as we can undo inheritance transformations after | |
2522 | inheritance pseudo assigning. */ | |
2523 | lra_create_live_ranges (true, false); | |
2524 | live_p = true; | |
2525 | /* If we don't spill non-reload and non-inheritance | |
2526 | pseudos, there is no sense to run memory-memory move | |
2527 | coalescing. If inheritance pseudos were spilled, the | |
2528 | memory-memory moves involving them will be removed by | |
2529 | pass undoing inheritance. */ | |
2530 | if (lra_simple_p) | |
2531 | lra_assign (fails_p); | |
2532 | else | |
638e746e | 2533 | { |
6a4bc24e | 2534 | bool spill_p = !lra_assign (fails_p); |
2535 | ||
2536 | if (lra_undo_inheritance ()) | |
2537 | live_p = false; | |
2538 | if (spill_p && ! fails_p) | |
638e746e | 2539 | { |
6a4bc24e | 2540 | if (! live_p) |
2541 | { | |
2542 | lra_create_live_ranges (true, true); | |
2543 | live_p = true; | |
2544 | } | |
2545 | if (lra_coalesce ()) | |
2546 | live_p = false; | |
638e746e | 2547 | } |
6a4bc24e | 2548 | if (! live_p) |
2549 | lra_clear_live_ranges (); | |
2550 | } | |
2551 | if (fails_p) | |
2552 | { | |
2553 | /* It is a very rare case. It is the last hope to | |
2554 | split a hard regno live range for a reload | |
2555 | pseudo. */ | |
2556 | if (live_p) | |
2557 | lra_clear_live_ranges (); | |
2558 | live_p = false; | |
2559 | if (! lra_split_hard_reg_for ()) | |
2560 | break; | |
638e746e | 2561 | } |
c6a6cdaa | 2562 | } |
6a4bc24e | 2563 | while (fails_p); |
c6a6cdaa | 2564 | } |
95563487 | 2565 | /* Don't clear optional reloads bitmap until all constraints are |
2566 | satisfied as we need to differ them from regular reloads. */ | |
2567 | bitmap_clear (&lra_optional_reload_pseudos); | |
1f3a048a | 2568 | bitmap_clear (&lra_subreg_reload_pseudos); |
c6a6cdaa | 2569 | bitmap_clear (&lra_inheritance_pseudos); |
2570 | bitmap_clear (&lra_split_regs); | |
c6a6cdaa | 2571 | if (! live_p) |
2572 | { | |
2573 | /* We need full live info for spilling pseudos into | |
2574 | registers instead of memory. */ | |
04472658 | 2575 | lra_create_live_ranges (lra_reg_spill_p, true); |
c6a6cdaa | 2576 | live_p = true; |
2577 | } | |
04472658 | 2578 | /* We should check necessity for spilling here as the above live |
2579 | range pass can remove spilled pseudos. */ | |
2580 | if (! lra_need_for_spills_p ()) | |
2581 | break; | |
497ba60f | 2582 | /* Now we know what pseudos should be spilled. Try to |
2583 | rematerialize them first. */ | |
68474cd7 | 2584 | if (lra_remat ()) |
497ba60f | 2585 | { |
2586 | /* We need full live info -- see the comment above. */ | |
04472658 | 2587 | lra_create_live_ranges (lra_reg_spill_p, true); |
497ba60f | 2588 | live_p = true; |
2589 | if (! lra_need_for_spills_p ()) | |
2590 | break; | |
2591 | } | |
c6a6cdaa | 2592 | lra_spill (); |
2593 | /* Assignment of stack slots changes elimination offsets for | |
2594 | some eliminations. So update the offsets here. */ | |
3b3a5e5f | 2595 | lra_eliminate (false, false); |
0f7b6a0d | 2596 | lra_constraint_new_regno_start = max_reg_num (); |
2597 | if (lra_bad_spill_regno_start == INT_MAX | |
2598 | && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES | |
2599 | && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES) | |
2600 | /* After switching off inheritance and rematerialization | |
2601 | passes, avoid spilling reload pseudos will be created to | |
2602 | prevent LRA cycling in some complicated cases. */ | |
2603 | lra_bad_spill_regno_start = lra_constraint_new_regno_start; | |
f95727ee | 2604 | lra_assignment_iter_after_spill = 0; |
c6a6cdaa | 2605 | } |
2606 | restore_scratches (); | |
3b3a5e5f | 2607 | lra_eliminate (true, false); |
ae72d5b2 | 2608 | lra_final_code_change (); |
c6a6cdaa | 2609 | lra_in_progress = 0; |
d3d0b390 | 2610 | if (live_p) |
2611 | lra_clear_live_ranges (); | |
c6a6cdaa | 2612 | lra_live_ranges_finish (); |
2613 | lra_constraints_finish (); | |
2614 | finish_reg_info (); | |
2615 | sbitmap_free (lra_constraint_insn_stack_bitmap); | |
f1f41a6c | 2616 | lra_constraint_insn_stack.release (); |
c6a6cdaa | 2617 | finish_insn_recog_data (); |
2618 | regstat_free_n_sets_and_refs (); | |
2619 | regstat_free_ri (); | |
2620 | reload_completed = 1; | |
2621 | update_inc_notes (); | |
2622 | ||
2623 | inserted_p = fixup_abnormal_edges (); | |
2624 | ||
2625 | /* We've possibly turned single trapping insn into multiple ones. */ | |
2626 | if (cfun->can_throw_non_call_exceptions) | |
2627 | { | |
3c6549f8 | 2628 | auto_sbitmap blocks (last_basic_block_for_fn (cfun)); |
53c5d9d4 | 2629 | bitmap_ones (blocks); |
c6a6cdaa | 2630 | find_many_sub_basic_blocks (blocks); |
c6a6cdaa | 2631 | } |
2632 | ||
2633 | if (inserted_p) | |
2634 | commit_edge_insertions (); | |
2635 | ||
2636 | /* Replacing pseudos with their memory equivalents might have | |
2637 | created shared rtx. Subsequent passes would get confused | |
2638 | by this, so unshare everything here. */ | |
2639 | unshare_all_rtl_again (get_insns ()); | |
2640 | ||
382ecba7 | 2641 | if (flag_checking) |
2642 | check_rtl (true); | |
c6a6cdaa | 2643 | |
2644 | timevar_pop (TV_LRA); | |
2645 | } | |
2646 | ||
2647 | /* Called once per compiler to initialize LRA data once. */ | |
2648 | void | |
2649 | lra_init_once (void) | |
2650 | { | |
2651 | init_insn_code_data_once (); | |
2652 | } | |
2653 | ||
c6a6cdaa | 2654 | /* Called once per compiler to finish LRA data which are initialize |
2655 | once. */ | |
2656 | void | |
2657 | lra_finish_once (void) | |
2658 | { | |
2659 | finish_insn_code_data_once (); | |
2660 | } |