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4bccb39e 1/* Target instruction definitions.
7adcbafe 2 Copyright (C) 2015-2022 Free Software Foundation, Inc.
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3
4 This program is free software; you can redistribute it and/or modify it
5 under the terms of the GNU General Public License as published by the
6 Free Software Foundation; either version 3, or (at your option) any
7 later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; see the file COPYING3. If not see
16 <http://www.gnu.org/licenses/>. */
17
18/* This file has one entry for each public pattern name that the target
19 can provide. It is only used if no distinction between operand modes
20 is necessary. If separate patterns are needed for different modes
21 (so as to distinguish addition of QImode values from addition of
22 HImode values, for example) then an optab should be used instead.
23
24 Each entry has the form:
25
26 DEF_TARGET_INSN (name, prototype)
27
28 where NAME is the name of the pattern and PROTOTYPE is its C prototype.
29 The prototype should use parameter names of the form "x0", "x1", etc.
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30 for the operands that the .md pattern is required to have, followed by
31 parameter names of the form "optN" for operands that the .md pattern
32 may choose to ignore. Patterns that never take operands should have
33 a prototype "(void)".
4bccb39e 34
58d745ec 35 Pattern names should be documented in md.texi rather than here. */
10169a8b 36DEF_TARGET_INSN (allocate_stack, (rtx x0, rtx x1))
3d000450 37DEF_TARGET_INSN (atomic_test_and_set, (rtx x0, rtx x1, rtx x2))
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38DEF_TARGET_INSN (builtin_longjmp, (rtx x0))
39DEF_TARGET_INSN (builtin_setjmp_receiver, (rtx x0))
40DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0))
e86a9946 41DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1))
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42DEF_TARGET_INSN (call, (rtx x0, rtx opt1, rtx opt2, rtx opt3))
43DEF_TARGET_INSN (call_pop, (rtx x0, rtx opt1, rtx opt2, rtx opt3))
44DEF_TARGET_INSN (call_value, (rtx x0, rtx x1, rtx opt2, rtx opt3, rtx opt4))
45DEF_TARGET_INSN (call_value_pop, (rtx x0, rtx x1, rtx opt2, rtx opt3,
46 rtx opt4))
8684d89d 47DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4))
10169a8b 48DEF_TARGET_INSN (check_stack, (rtx x0))
f2cf13bd 49DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1))
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50DEF_TARGET_INSN (doloop_begin, (rtx x0, rtx x1))
51DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1))
3b0b0013 52DEF_TARGET_INSN (eh_return, (rtx x0))
e86a9946 53DEF_TARGET_INSN (epilogue, (void))
95a3fb9d 54DEF_TARGET_INSN (exception_receiver, (void))
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55DEF_TARGET_INSN (extv, (rtx x0, rtx x1, rtx x2, rtx x3))
56DEF_TARGET_INSN (extzv, (rtx x0, rtx x1, rtx x2, rtx x3))
90262804 57DEF_TARGET_INSN (indirect_jump, (rtx x0))
234d14ac 58DEF_TARGET_INSN (insv, (rtx x0, rtx x1, rtx x2, rtx x3))
ec4a505f 59DEF_TARGET_INSN (jump, (rtx x0))
20fceb31 60DEF_TARGET_INSN (load_multiple, (rtx x0, rtx x1, rtx x2))
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61DEF_TARGET_INSN (mem_thread_fence, (rtx x0))
62DEF_TARGET_INSN (memory_barrier, (void))
51ced7e4 63DEF_TARGET_INSN (memory_blockage, (void))
7cff0471 64DEF_TARGET_INSN (movstr, (rtx x0, rtx x1, rtx x2))
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65DEF_TARGET_INSN (nonlocal_goto, (rtx x0, rtx x1, rtx x2, rtx x3))
66DEF_TARGET_INSN (nonlocal_goto_receiver, (void))
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67DEF_TARGET_INSN (oacc_dim_pos, (rtx x0, rtx x1))
68DEF_TARGET_INSN (oacc_dim_size, (rtx x0, rtx x1))
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69DEF_TARGET_INSN (oacc_fork, (rtx x0, rtx x1, rtx x2))
70DEF_TARGET_INSN (oacc_join, (rtx x0, rtx x1, rtx x2))
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71DEF_TARGET_INSN (omp_simt_enter, (rtx x0, rtx x1, rtx x2))
72DEF_TARGET_INSN (omp_simt_exit, (rtx x0))
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73DEF_TARGET_INSN (omp_simt_lane, (rtx x0))
74DEF_TARGET_INSN (omp_simt_last_lane, (rtx x0, rtx x1))
75DEF_TARGET_INSN (omp_simt_ordered, (rtx x0, rtx x1))
76DEF_TARGET_INSN (omp_simt_vote_any, (rtx x0, rtx x1))
77DEF_TARGET_INSN (omp_simt_xchg_bfly, (rtx x0, rtx x1, rtx x2))
78DEF_TARGET_INSN (omp_simt_xchg_idx, (rtx x0, rtx x1, rtx x2))
134b044d 79DEF_TARGET_INSN (prefetch, (rtx x0, rtx x1, rtx x2))
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80DEF_TARGET_INSN (probe_stack, (rtx x0))
81DEF_TARGET_INSN (probe_stack_address, (rtx x0))
e86a9946 82DEF_TARGET_INSN (prologue, (void))
2a870875 83DEF_TARGET_INSN (ptr_extend, (rtx x0, rtx x1))
726858e3 84DEF_TARGET_INSN (reload_load_address, (rtx x0, rtx x1))
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85DEF_TARGET_INSN (restore_stack_block, (rtx x0, rtx x1))
86DEF_TARGET_INSN (restore_stack_function, (rtx x0, rtx x1))
87DEF_TARGET_INSN (restore_stack_nonlocal, (rtx x0, rtx x1))
4bccb39e 88DEF_TARGET_INSN (return, (void))
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89DEF_TARGET_INSN (save_stack_block, (rtx x0, rtx x1))
90DEF_TARGET_INSN (save_stack_function, (rtx x0, rtx x1))
91DEF_TARGET_INSN (save_stack_nonlocal, (rtx x0, rtx x1))
58d745ec 92DEF_TARGET_INSN (sibcall, (rtx x0, rtx opt1, rtx opt2, rtx opt3))
e86a9946 93DEF_TARGET_INSN (sibcall_epilogue, (void))
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94DEF_TARGET_INSN (sibcall_value, (rtx x0, rtx x1, rtx opt2, rtx opt3,
95 rtx opt4))
4bccb39e 96DEF_TARGET_INSN (simple_return, (void))
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97DEF_TARGET_INSN (split_stack_prologue, (void))
98DEF_TARGET_INSN (split_stack_space_check, (rtx x0, rtx x1))
89d75572 99DEF_TARGET_INSN (stack_protect_combined_set, (rtx x0, rtx x1))
c65aa042 100DEF_TARGET_INSN (stack_protect_set, (rtx x0, rtx x1))
89d75572 101DEF_TARGET_INSN (stack_protect_combined_test, (rtx x0, rtx x1, rtx x2))
c65aa042 102DEF_TARGET_INSN (stack_protect_test, (rtx x0, rtx x1, rtx x2))
20fceb31 103DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2))
8684d89d 104DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1))
eb6f47fb 105DEF_TARGET_INSN (trap, (void))
8ab78162 106DEF_TARGET_INSN (unique, (void))
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107DEF_TARGET_INSN (untyped_call, (rtx x0, rtx x1, rtx x2))
108DEF_TARGET_INSN (untyped_return, (rtx x0, rtx x1))