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feeeff5c 1/* Signed 32 bit division optimized for Epiphany.
a945c346 2 Copyright (C) 2009-2024 Free Software Foundation, Inc.
feeeff5c
JR
3 Contributed by Embecosm on behalf of Adapteva, Inc.
4
5This file is part of GCC.
6
7This file is free software; you can redistribute it and/or modify it
8under the terms of the GNU General Public License as published by the
9Free Software Foundation; either version 3, or (at your option) any
10later version.
11
12This file is distributed in the hope that it will be useful, but
13WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15General Public License for more details.
16
17Under Section 7 of GPL version 3, you are granted additional
18permissions described in the GCC Runtime Library Exception, version
193.1, as published by the Free Software Foundation.
20
21You should have received a copy of the GNU General Public License and
22a copy of the GCC Runtime Library Exception along with this program;
23see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24<http://www.gnu.org/licenses/>. */
25
26#include "epiphany-asm.h"
27
28 FSTAB (__divsi3,T_UINT)
29 .global SYM(__divsi3)
30 .balign 4
31 HIDDEN_FUNC(__divsi3)
32SYM(__divsi3):
33 float TMP2,r0
34 mov TMP4,0
35 float TMP1,r1
36 sub TMP0,TMP4,r0
37 beq .Lret_r0
38 movgt r0,TMP0
39 sub TMP0,TMP4,r1
40 movgt r1,TMP0
41 mov TMP0,1
42 sub TMP2,TMP2,TMP1
43 asr TMP3,TMP2,31 ; save sign
44 lsl TMP2,TMP2,1
45 blt .Lret0
46 sub TMP1,TMP2,1 ; rounding compensation, avoid overflow
47 movgte TMP2,TMP1
48 lsr TMP2,TMP2,24
49 lsl r1,r1,TMP2
50 lsl TMP0,TMP0,TMP2
51 sub TMP1,r0,r1
52 movgteu r0,TMP1
53 movgteu TMP4,TMP0
54 lsl TMP5,TMP0,1
55 sub TMP1,r0,r1
56 movgteu r0,TMP1
57 movgteu TMP4,TMP5
58 sub TMP1,r1,1
59 mov r1,%low(.L0step)
60 movt r1,%high(.L0step)
61 lsl TMP2,TMP2,3
62 sub r1,r1,TMP2
63 jr r1
64 .rep 30
65 lsl r0,r0,1
66 sub.l r1,r0,TMP1
67 movgteu r0,r1
68 .endr
69.L0step:sub r1,TMP0,1 ; mask result bits from steps ...
70 and r0,r0,r1
71 orr r0,r0,TMP4 ; ... and combine with first bit.
72 eor r0,r0,TMP3 ; restore sign
73 sub r0,r0,TMP3
74.Lret_r0:rts
75.Lret0: mov r0,0
76 rts
77 ENDFUNC(__divsi3)