+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (check_reduction_path): Compute reduction
+ operation here.
+ (vect_is_simple_reduction): Remove special-case of single-stmt
+ reduction path detection.
+
+2019-10-17 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.
+
+2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
+
+ * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
+ (aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
+ (aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
+ (aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
+ New combine patterns.
+ * config/aarch64/iterators.md (BSL_DUP): New int iterator for the
+ above.
+ (bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
+
+2019-10-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (value_range_base::dump): Display +INF for both
+ pointers and integers when appropriate.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_analyze_loop_2): Use same condition to decide
+ when to use versioning threshold.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (determine_peel_for_niter): New function contained
+ outlined code from ...
+ (vect_analyze_loop_2): ... here.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_transform_loop): Move code from here...
+ * tree-vect-loop-manip.c (vect_loop_versioning): ... to here.
+ * tree-vectorizer.h (vect_loop_versioning): Remove unused parameters.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (needs_fold_left_reduction_p): Export.
+ (vect_is_simple_reduction): Move all validity checks ...
+ (vectorizable_reduction): ... here. Compute whether we
+ need a fold-left reduction here.
+ * tree-vect-patterns.c (vect_reassociating_reduction_p): Merge
+ both overloads, check needs_fold_left_reduction_p directly.
+ * tree-vectorizer.h (needs_fold_left_reduction_p): Declare.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix
+ TARGET_MEM_REF creation.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92129
+ * tree-vect-loop.c (vectorizable_reduction): Also fail
+ on GIMPLE_SINGLE_RHS.
+
+2019-10-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/92056
+ * tree-object-size.c (cond_expr_object_size): Return early if then_
+ processing resulted in unknown size.
+
+ PR tree-optimization/92115
+ * tree-ssa-ifcombine.c (ifcombine_ifandif): Force condition into
+ temporary if it could trap.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ PR debug/91887
+ * dwarf2out.c (gen_formal_parameter_die): Also try to match
+ context_die against a DW_TAG_GNU_formal_parameter_pack parent.
+
+2019-10-16 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-ssa-strlen.c (maybe_invalidate): Use
+ HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".
+
+2019-10-16 Andrew Burgess <andrew.burgess@embecosm.com>
+ Jim Wilson <jimw@sifive.com>
+
+ * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
+ regs to SIBCALL_REGS.
+ * config/riscv/riscv.c (riscv_regno_to_class): Change argument
+ passing regs to SIBCALL_REGS.
+
+2019-10-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/83821
+ * tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider
+ the length of a string when available.
+ (handle_builtin_memset) Add argument.
+ (handle_store, strlen_check_and_optimize_call): Same.
+ (check_and_optimize_stmt): Same. Pass it to callees.
+
+2019-10-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/91996
+ * tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
+ information.
+ (compare_nonzero_chars): Add an overload.
+ (count_nonzero_bytes): Add an argument. Call overload above.
+ Handle non-constant lengths in some range.
+ (handle_store): Add an argument.
+ (check_and_optimize_stmt): Pass an argument to handle_store.
+
+2019-10-16 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (neon_valid_immediate): Clear bytes before use.
+
+2019-10-16 Mihailo Stojanovic <mistojanovic@wavecomp.com>
+
+ * config/mips/mips.c (mips_expand_builtin_insn): Force the
+ operands which correspond to the same input-output register to
+ have the same pseudo assigned to them.
+
+2019-10-16 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.
+
+2019-10-16 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_classify_symbol):
+ Apply reasonable limit to symbol offsets.
+
+2019-10-16 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
+ (vect_is_simple_reduction): Delay checking to
+ vectorizable_reduction and relax the checking.
+ (vectorizable_reduction): Check we have a simple use. Check
+ for bogus condition reductions.
+ * tree-vect-stmts.c (vect_transform_stmt): Make sure we
+ are looking at the last stmt in a pattern sequence when
+ filling in backedge PHI values.
+
+2019-10-16 Peter Bergner <bergner@linux.ibm.com>
+ Jiufu Guo <guojiufu@linux.ibm.com>
+
+ PR target/70010
+ * config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
+ the callee explicitly disables some isa_flags the caller is using.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * function-abi.cc (expr_callee_abi): Assert for POINTER_TYPE_P.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genmodes.c (mode_data::order): New field.
+ (blank_mode): Update accordingly.
+ (VECTOR_MODES_WITH_PREFIX): Add an order parameter.
+ (make_vector_modes): Likewise.
+ (VECTOR_MODES): Update use accordingly.
+ (cmp_modes): Sort by the new order field ahead of sorting by size.
+ * config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI)
+ (VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
+ * config/aarch64/aarch64.c (VEC_PARTIAL): New flag value.
+ (aarch64_classify_vector_mode): Handle the new partial modes.
+ (aarch64_vl_bytes): New function.
+ (aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR
+ when counting the number of registers in an SVE mode.
+ (aarch64_class_max_nregs): Likewise.
+ (aarch64_hard_regno_mode_ok): Don't allow partial vectors
+ in registers yet.
+ (aarch64_classify_address): Treat partial vectors analogously
+ to full vectors.
+ (aarch64_print_address_internal): Consolidate the printing of
+ MUL VL addresses, using aarch64_vl_bytes as the number of
+ bytes represented by "VL".
+ (aarch64_vector_mode_supported_p): Reject partial vector modes.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant
+ rather than known_lt when choosing frame layouts.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_layout_frame): Assert
+ that all the adjustments add up to the full frame size.
+ Use crtl->outgoing_args_size directly as the final adjustment
+ where appropriate.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_layout_frame): Use a local
+ "frame" reference instead of always referring directly to
+ "cfun->machine->frame".
+
+2019-10-16 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92119
+ * tree-vect-patterns.c (vect_recog_rotate_pattern): Guard
+ against missing bswap lhs.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR middle-end/92033
+ * poly-int.h (constant_lower_bound_with_limit): New function.
+ (constant_upper_bound_with_limit): Likewise.
+ * doc/poly-int.texi: Document them.
+ * tree-vrp.c (value_range_base::set): Convert POLY_INT_CST bounds
+ into the worst-case INTEGER_CST bounds.
+
+2019-10-16 Feng Xue <fxue@os.amperecomputing.com>
+
+ PR ipa/91088
+ * doc/invoke.texi (ipa-max-param-expr-ops): Document new option.
+ * params.def (PARAM_IPA_MAX_PARAM_EXPR_OPS): New.
+ * ipa-predicat.h (struct expr_eval_op): New struct.
+ (expr_eval_ops): New typedef.
+ (struct condition): Add type and param_ops fields, remove size field.
+ (add_condition): Replace size parameter with type parameter, add
+ param_ops parameter.
+ * ipa-predicat.c (expr_eval_ops_equal_p): New function.
+ (predicate::add_clause): Add comparisons on type and param_ops.
+ (dump_condition): Add debug dump for param_ops.
+ (remap_after_inlining): Adjust call arguments to add_condition.
+ (add_condition): Replace size parameter with type parameter, add
+ param_ops parameter. Unshare constant value used in conditions.
+ * ipa-fnsummary.c (evaluate_conditions_for_known_args): Fold
+ parameter expressions using param_ops.
+ (decompose_param_expr): New function.
+ (set_cond_stmt_execution_predicate): Use call to decompose_param_expr
+ to replace call to unmodified_parm_or_parm_agg_item.
+ (set_switch_stmt_execution_predicate): Likewise.
+ (will_be_nonconstant_expr_predicate): Likewise. Replace usage of size
+ with type.
+ (inline_read_section): Read param_ops from summary stream.
+ (ipa_fn_summary_write): Write param_ops to summary stream.
+
+2019-10-15 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR rtl-optimization/92107
+ * genattrtab.c (write_attr_value) <do_operator>: Parenthesize the
+ expression written.
+
+2019-10-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.c: Update description of fix and continue.
+
+2019-10-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ * config/darwin.c (darwin_binds_local_p): Update to call
+ default_binds_local_p_3 () directly. amend comments.
+
+2019-10-15 Richard Biener <rguenther@suse.de>
+
+ * lto-streamer-out.c (lto_variably_modified_type_p): New.
+ (tree_is_indexable): Use it.
+ * tree-streamer-out.c (pack_ts_type_common_value_fields):
+ Stream variably_modified_type_p as TYPE_LANG_FLAG_0.
+ * tree-streamer-in.c (unpack_ts_type_common_value_fields): Likewise.
+
+2019-10-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/msp430/msp430.md (zero_extendqipsi2): New.
+ (zero_extendqisi2): Optimize case where src register and base dst
+ register are the same.
+ (zero_extendhipsi2): Don't use 430X insn for rYs->r case.
+ (zero_extendpsisi2): Optimize r->m case.
+ Add unnamed insn patterns to catch insns combine searches for when
+ optimizing pointer manipulation.
+
+2019-10-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/msp430/msp430.md: Group zero_extend* insns together.
+
+2019-10-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
+
+ * config/msp430/constraints.md: Allow post_inc operand for "Ya"
+ constraint.
+ * config/msp430/msp430.c (msp430_legitimate_address_p): Handle
+ POST_INC.
+ (msp430_subreg): Likewise.
+ (msp430_split_addsi): Likewise.
+ (msp430_print_operand_addr): Likewise.
+ * config/msp430/msp430.h (HAVE_POST_INCREMENT): Define.
+ (USE_STORE_POST_INCREMENT): Define.
+ * config/msp430/msp430.md: Use the msp430_general_dst_operand or
+ msp430_general_dst_nonv_operand predicates for the lvalues of insns.
+ * config/msp430/predicates.md (msp430_nonpostinc_operand): New.
+ (msp430_general_dst_operand): New.
+ (msp430_general_dst_nonv_operand): New.
+ (msp430_nonsubreg_operand): Remove.
+ (msp430_nonsubreg_dst_operand): New.
+ (msp430_nonsubreg_or_imm_operand): Allow reg or mem operands in place
+ of defunct msp430_nonsubreg_operand.
+ (msp430_nonsubregnonpostinc_or_imm_operand): New.
+
+2019-10-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/91929
+ * tree-ssa-pre.c (pre_expr_d::loc): New member.
+ (get_or_alloc_expr_for_name): Initialize it.
+ (get_or_alloc_expr_for_constant): Likewise.
+ (phi_translate_1): Copy it.
+ (create_expression_by_pieces): Use the original location
+ of the expression for the inserted stmt.
+ (compute_avail): Record the location of the stmt for the
+ expressions created.
+
+2019-10-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-ssa-strlen.c (count_nonzero_bytes): Check tree_fits_uhwi_p
+ before using tree_to_uhwi.
+
+2019-10-15 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * config/s390/s390.md: Run %a0:DI splitters only after reload.
+
+2019-10-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92094
+ * tree-vect-loop.c (vectorizable_reduction): For nested cycles
+ do not adjust the reduction definition def type.
+ * tree-vect-stmts.c (vect_transform_stmt): Verify the scalar stmt
+ defines the latch argument of the PHI.
+
+2019-10-15 Hongyu Wang <hongtao.wang@intel.com>
+
+ PR target/92035
+ * config/i386/avx512fintrin.h (_mm_mask_roundscale_ss,
+ _mm_maskz_roundscale_ss, _mm_maskz_roundscale_round_ss,
+ _mm_maskz_roundscale_round_ss, _mm_mask_roundscale_sd,
+ _mm_maskz_roundscale_sd, _mm_mask_roundscale_round_sd,
+ _mm_maskz_roundscale_round_sd): New intrinsics.
+ (_mm_roundscale_ss, _mm_roundscale_round_ss): Use
+ __builtin_ia32_rndscales?_mask_round builtins instead of
+ __builtin_ia32_rndscales?_round.
+ * config/i386/i386-builtin.def (__builtin_ia32_rndscaless_round,
+ __builtin_ia32_rndscalesd_round): Remove.
+ (__builtin_ia32_rndscaless_mask_round,
+ __builtin_ia32_rndscalesd_mask_round): New intrinsics.
+ * config/i386/sse.md
+ (avx512f_rndscale<mode><round_saeonly_name>): Renamed to ...
+ (avx512f_rndscale<mode><mask_scalar_name><round_saeonly_scalar_name>):
+ ... this, adjust and add subst atrributes to make it maskable.
+
+2019-10-15 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/92046
+ * common.opt (fallow-store-data-races): New.
+ * params.def (PARAM_ALLOW_STORE_DATA_RACES): Remove.
+ * params.h (ALLOW_STORE_DATA_RACES): Likewise.
+ * doc/invoke.texi (fallow-store-data-races): Document.
+ (--param allow-store-data-races): Remove docs.
+ * opts.c (default_options_table): Enable -fallow-store-data-races
+ at -Ofast.
+ (default_options_optimization): Do not enable --param
+ allow-store-data-races at -Ofast.
+ * tree-if-conv.c (ifcvt_memrefs_wont_trap): Use flag_store_data_races
+ instead of PARAM_ALLOW_STORE_DATA_RACES.
+ * tree-ssa-loop-im.c (execute_sm): Likewise.
+
2019-10-15 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
PR tree-optimization/92085