+2019-10-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/92153
+ * ggc-page.c (release_pages): Read g->alloc_size before free rather
+ than after it.
+
+2019-10-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/t-multilib: Add rule to regenerate mutlilib header file
+ with any change to t-multilib, t-aprofile and t-rmprofile. Also add
+ new multilib variants and new mappings.
+
+2019-10-18 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/86040
+ * config/avr/avr.c (avr_out_lpm): Do not shortcut-return.
+
+2019-10-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+ Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/86753
+ * tree-vectorizer.h (scalar_cond_masked_key): New struct,
+ and define hashmap traits for it.
+ (loop_vec_info::scalar_cond_masked_set): New member.
+ (vect_record_loop_mask): Adjust prototype.
+ * tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree):
+ Implement method.
+ * tree-vect-loop.c (vectorizable_reduction): Pass NULL as last arg to
+ vect_record_loop_mask.
+ (vectorizable_live_operation): Likewise.
+ (vect_record_loop_mask): New param scalar_mask. Add entry
+ cond, loop_mask to scalar_cond_masked_set if scalar_mask is non NULL.
+ * tree-vect-stmts.c (check_load_store_masking): New param scalar_mask.
+ Pass it as last arg to vect_record_loop_mask.
+ (vectorizable_call): Pass scalar_mask as last arg to
+ vect_record_loop_mask.
+ (vectorizable_store): Likewise.
+ (vectorizable_load): Likewise.
+ (vectorizable_condition): Check if another part of vectorized code
+ applies loop_mask to condition or to it's inverse, and if yes,
+ apply loop_mask to result of vector comparison.
+
+2019-10-17 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.c (pa_output_indirect_call): Fix typos in last change.
+
+2019-10-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/92056
+ * tree-ssa-strlen.c (determine_min_objsize): Call init_object_sizes
+ before calling compute_builtin_object_size.
+
+2019-10-17 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/65342
+ * config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete.
+ (movdi_low_st): Delete.
+ * config/rs6000/rs6000.c
+ (darwin_rs6000_legitimate_lo_sum_const_p): New.
+ (mem_operand_gpr): Validate Mach-O LO_SUM cases separately.
+ * config/rs6000/rs6000.md (movsi_low): Delete.
+
+2019-10-17 Jason Merrill <jason@redhat.com>
+
+ * gimplify.h (get_initialized_tmp_var): Add default argument to
+ post_p.
+ * gimplify.c (gimplify_self_mod_expr, gimplify_omp_atomic): Remove
+ NULL post_p argument.
+ * targhooks (std_gimplify_va_arg_expr): Likewise.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
+ (STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
+ * tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
+ initialize STMT_VINFO_VEC_COND_REDUC_CODE.
+ * tree-vect-loop.c (vect_is_simple_reduction): Set
+ STMT_VINFO_REDUC_CODE.
+ (vectorizable_reduction): Remove dead and redundant code, use
+ STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.
+
+2019-10-17 Georg-Johann Lay <avr@gjlay.de>
+
+ Fix breakage introduced by r276985.
+
+ * config/avr/avr.c (avr_option_override): Remove set of
+ PARAM_ALLOW_STORE_DATA_RACES.
+ * common/config/avr/avr-common.c (avr_option_optimization_table)
+ [OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.
+
+2019-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.h (processor_costs): Add clear_ratio.
+ (CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
+ * config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
+ of 6 and move_ratio in all cost models.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (check_reduction_path): Compute reduction
+ operation here.
+ (vect_is_simple_reduction): Remove special-case of single-stmt
+ reduction path detection.
+
+2019-10-17 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.
+
+2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
+
+ * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
+ (aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
+ (aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
+ (aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
+ New combine patterns.
+ * config/aarch64/iterators.md (BSL_DUP): New int iterator for the
+ above.
+ (bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
+
+2019-10-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (value_range_base::dump): Display +INF for both
+ pointers and integers when appropriate.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_analyze_loop_2): Use same condition to decide
+ when to use versioning threshold.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (determine_peel_for_niter): New function contained
+ outlined code from ...
+ (vect_analyze_loop_2): ... here.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_transform_loop): Move code from here...
+ * tree-vect-loop-manip.c (vect_loop_versioning): ... to here.
+ * tree-vectorizer.h (vect_loop_versioning): Remove unused parameters.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (needs_fold_left_reduction_p): Export.
+ (vect_is_simple_reduction): Move all validity checks ...
+ (vectorizable_reduction): ... here. Compute whether we
+ need a fold-left reduction here.
+ * tree-vect-patterns.c (vect_reassociating_reduction_p): Merge
+ both overloads, check needs_fold_left_reduction_p directly.
+ * tree-vectorizer.h (needs_fold_left_reduction_p): Declare.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix
+ TARGET_MEM_REF creation.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92129
+ * tree-vect-loop.c (vectorizable_reduction): Also fail
+ on GIMPLE_SINGLE_RHS.
+
+2019-10-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/92056
+ * tree-object-size.c (cond_expr_object_size): Return early if then_
+ processing resulted in unknown size.
+
+ PR tree-optimization/92115
+ * tree-ssa-ifcombine.c (ifcombine_ifandif): Force condition into
+ temporary if it could trap.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ PR debug/91887
+ * dwarf2out.c (gen_formal_parameter_die): Also try to match
+ context_die against a DW_TAG_GNU_formal_parameter_pack parent.
+
+2019-10-16 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-ssa-strlen.c (maybe_invalidate): Use
+ HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".
+
+2019-10-16 Andrew Burgess <andrew.burgess@embecosm.com>
+ Jim Wilson <jimw@sifive.com>
+
+ * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
+ regs to SIBCALL_REGS.
+ * config/riscv/riscv.c (riscv_regno_to_class): Change argument
+ passing regs to SIBCALL_REGS.
+
+2019-10-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/83821
+ * tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider
+ the length of a string when available.
+ (handle_builtin_memset) Add argument.
+ (handle_store, strlen_check_and_optimize_call): Same.
+ (check_and_optimize_stmt): Same. Pass it to callees.
+
+2019-10-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/91996
+ * tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
+ information.
+ (compare_nonzero_chars): Add an overload.
+ (count_nonzero_bytes): Add an argument. Call overload above.
+ Handle non-constant lengths in some range.
+ (handle_store): Add an argument.
+ (check_and_optimize_stmt): Pass an argument to handle_store.
+
+2019-10-16 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (neon_valid_immediate): Clear bytes before use.
+
+2019-10-16 Mihailo Stojanovic <mistojanovic@wavecomp.com>
+
+ * config/mips/mips.c (mips_expand_builtin_insn): Force the
+ operands which correspond to the same input-output register to
+ have the same pseudo assigned to them.
+
+2019-10-16 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.
+
+2019-10-16 Wilco Dijkstra <wdijkstr@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_classify_symbol):
+ Apply reasonable limit to symbol offsets.
+
+2019-10-16 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (vect_valid_reduction_input_p): Remove.
+ (vect_is_simple_reduction): Delay checking to
+ vectorizable_reduction and relax the checking.
+ (vectorizable_reduction): Check we have a simple use. Check
+ for bogus condition reductions.
+ * tree-vect-stmts.c (vect_transform_stmt): Make sure we
+ are looking at the last stmt in a pattern sequence when
+ filling in backedge PHI values.
+
+2019-10-16 Peter Bergner <bergner@linux.ibm.com>
+ Jiufu Guo <guojiufu@linux.ibm.com>
+
+ PR target/70010
+ * config/rs6000/rs6000.c (rs6000_can_inline_p): Prohibit inlining if
+ the callee explicitly disables some isa_flags the caller is using.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * function-abi.cc (expr_callee_abi): Assert for POINTER_TYPE_P.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * genmodes.c (mode_data::order): New field.
+ (blank_mode): Update accordingly.
+ (VECTOR_MODES_WITH_PREFIX): Add an order parameter.
+ (make_vector_modes): Likewise.
+ (VECTOR_MODES): Update use accordingly.
+ (cmp_modes): Sort by the new order field ahead of sorting by size.
+ * config/aarch64/aarch64-modes.def (VNx2QI, VN2xHI, VNx2SI)
+ (VNx4QI, VNx4HI, VNx8QI): New partial vector modes.
+ * config/aarch64/aarch64.c (VEC_PARTIAL): New flag value.
+ (aarch64_classify_vector_mode): Handle the new partial modes.
+ (aarch64_vl_bytes): New function.
+ (aarch64_hard_regno_nregs): Use it instead of BYTES_PER_SVE_VECTOR
+ when counting the number of registers in an SVE mode.
+ (aarch64_class_max_nregs): Likewise.
+ (aarch64_hard_regno_mode_ok): Don't allow partial vectors
+ in registers yet.
+ (aarch64_classify_address): Treat partial vectors analogously
+ to full vectors.
+ (aarch64_print_address_internal): Consolidate the printing of
+ MUL VL addresses, using aarch64_vl_bytes as the number of
+ bytes represented by "VL".
+ (aarch64_vector_mode_supported_p): Reject partial vector modes.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_layout_frame): Use is_constant
+ rather than known_lt when choosing frame layouts.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_layout_frame): Assert
+ that all the adjustments add up to the full frame size.
+ Use crtl->outgoing_args_size directly as the final adjustment
+ where appropriate.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.c (aarch64_layout_frame): Use a local
+ "frame" reference instead of always referring directly to
+ "cfun->machine->frame".
+
+2019-10-16 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92119
+ * tree-vect-patterns.c (vect_recog_rotate_pattern): Guard
+ against missing bswap lhs.
+
+2019-10-16 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR middle-end/92033
+ * poly-int.h (constant_lower_bound_with_limit): New function.
+ (constant_upper_bound_with_limit): Likewise.
+ * doc/poly-int.texi: Document them.
+ * tree-vrp.c (value_range_base::set): Convert POLY_INT_CST bounds
+ into the worst-case INTEGER_CST bounds.
+
2019-10-16 Feng Xue <fxue@os.amperecomputing.com>
PR ipa/91088
projects / thirdparty / gcc.git / blobdiff