+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (arm_select_cc_mode): Allow either the first
+ or second operand of the PLUS inside a DImode equality test to be
+ sign-extend when selecting CC_Vmode.
+ * config/arm/arm.md (addvdi4): Early-split the operation into SImode
+ instructions.
+ (addsi3_cin_vout_reg, addsi3_cin_vout_imm, addsi3_cin_vout_0): New
+ expand patterns.
+ (addsi3_cin_vout_reg_insn, addsi3_cin_vout_imm_insn): New patterns.
+ (addsi3_cin_vout_0): Likewise.
+ (adddi3_compareV): Delete.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (addsi3_compareV_reg_nosum): New insn.
+ (addsi3_compareV_imm_nosum): New insn. Also add peephole2 patterns
+ to transform this back into the summation version when that leads
+ to smaller code.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (addv<mode>4): Delete.
+ (addvsi4): New pattern. Handle immediate values that the architecture
+ supports.
+ (addvdi4): New pattern.
+ (addsi3_compareV): Rename to ...
+ (addsi3_compareV_reg): ... this. Add constraints for thumb2 variants
+ and use COMPARE rather than NE.
+ (addsi3_compareV_imm): New pattern.
+ * config/arm/arm.c (arm_select_cc_mode): Return CC_Vmode for
+ a signed-overflow check.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-modes.def (CC_ADC): New CC mode.
+ * config/arm/arm.c (arm_select_cc_mode): Detect selection of
+ CC_ADCmode.
+ (maybe_get_arm_condition_code): Handle CC_ADCmode.
+ * config/arm/arm.md (uaddvdi4): Early expansion of unsigned addition
+ with overflow.
+ (addsi3_cin_cout_reg, addsi3_cin_cout_imm, addsi3_cin_cout_0): New
+ expand patterns.
+ (addsi3_cin_cout_reg_insn, addsi3_cin_cout_0_insn): New insn patterns
+ (addsi3_cin_cout_imm_insn): Likewise.
+ (adddi3_compareC): Delete insn.
+ * config/arm/predicates.md (arm_carry_operation): Handle CC_ADCmode.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (adddi3): Call gen_addsi3_compare_op1.
+ * (uaddv<mode>4): Delete expansion pattern.
+ (uaddvsi4): New pattern.
+ (uaddvdi4): Likewise.
+ (addsi3_compareC): Delete pattern, change callers to use
+ addsi3_compare_op1.
+ (addsi3_compare_op1): No-longer anonymous. Clean up constraints to
+ reduce the number of alternatives and re-work type attribute handling.
+ (addsi3_compare_op2): Clean up constraints to reduce the number of
+ alternatives and re-work type attribute handling.
+ (compare_addsi2_op0): Likewise.
+ (compare_addsi2_op1): Likewise.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-modes.def (CC_NCV, CC_CZ): Delete CC modes.
+ * config/arm/arm.c (arm_select_cc_mode): Remove old selection code
+ for DImode operands.
+ (arm_gen_dicompare_reg): Remove unreachable expansion code.
+ (maybe_get_arm_condition_code): Remove support for CC_CZmode and
+ CC_NCVmode.
+ * config/arm/arm.md (arm_cmpdi_insn): Delete.
+ (arm_cmpdi_unsigned): Delete.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (arm_const_double_prefer_rsbs_rsc): New function.
+ (arm_canonicalize_comparison): For GT/LE/GTU/GEU, use the constant
+ unchanged only if that will be cheaper.
+ (arm_select_cc_mode): Recognize a swapped comparison that will
+ be regenerated using RSBS or RSCS. Relax restriction on selecting
+ CC_RSBmode.
+ (arm_gen_dicompare_reg): Handle LE/GT/LEU/GEU comparisons against
+ a constant.
+ (arm_gen_compare_reg): Handle compare (CONST, X) when the mode
+ is CC_RSBmode.
+ (maybe_get_arm_condition_code): CC_RSBmode now returns the same codes
+ as CCmode.
+ * config/arm/arm.md (rsb_imm_compare_scratch): New pattern.
+ (rscsi3_<CC_EXTEND>out_scratch): New pattern.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-modes.def (CC_NV, CC_B): New CC modes.
+ * config/arm/arm.c (arm_select_cc_mode): Recognize constructs that
+ need these modes.
+ (arm_gen_dicompare_reg): New code to early expand the sub-operations
+ of EQ, NE, LT, GE, LTU and GEU.
+ * config/arm/iterators.md (CC_EXTEND): New code attribute.
+ * config/arm/predicates.md (arm_adcimm_operand): New predicate..
+ * config/arm/arm.md (cmpsi3_carryin_<CC_EXTEND>out): New pattern.
+ (cmpsi3_imm_carryin_<CC_EXTEND>out): Likewise.
+ (cmpsi3_0_carryin_<CC_EXTEND>out): Likewise.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (cbranchdi4): Accept reg_or_int_operand for
+ operand 2.
+ (cstoredi4): Similarly, but for operand 3.
+ * config/arm/arm.c (arm_canoncialize_comparison): Allow
+ canonicalization of unsigned compares with a constant on Arm.
+ Prefer using const+1 and adjusting the comparison over swapping the
+ operands whenever the original constant was not valid.
+ (arm_gen_dicompare_reg): If Y is not a valid operand, force it to a
+ register here.
+ (arm_validize_comparison): Do not force invalid DImode operands to
+ registers here.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (arm_select_cc_mode): For DImode equality tests
+ return CC_Zmode if comparing against a constant where one word is
+ zero.
+ (arm_gen_compare_reg): Split DImode handling to ...
+ (arm_gen_dicompare_reg): ... here. Handle equality comparisons
+ against simple constants.
+ * config/arm/arm.md (arm_cmpdi_zero): Delete pattern.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (subsi3_carryin_shift_alt): New pattern.
+ (rsbsi3_carryin_shift_alt): Likewise.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (negscc_borrow): New pattern.
+ (mov_negscc): Don't split if the insn would match negscc_borrow.
+ * config/arm/thumb2.md (thumb2_mov_negscc): Likewise.
+ (thumb2_mov_negscc_strict_it): Likewise.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (arm_insn_cost): New function.
+ (TARGET_INSN_COST): Override default definition.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (arm_rtx_costs_internal, case MINUS): Handle
+ borrow operations.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (strip_carry_operation): New function.
+ (arm_rtx_costs_internal, case PLUS): Handle addtion with carry-in
+ for SImode.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/predicates.md (arm_carry_operation): New special
+ predicate.
+ * config/arm/iterators.md (LTUGEU): Delete iterator.
+ (cnb): Delete code attribute.
+ (optab): Delete ltu and geu elements.
+ * config/arm/arm.md (addsi3_carryin): Renamed from
+ addsi3_carryin_<optab>. Remove iterator and use arm_carry_operand.
+ (add0si3_carryin): Similarly, but from add0si3_carryin_<optab>.
+ (addsi3_carryin_alt2): Similarly, but from addsi3_carryin_alt2_<optab>.
+ (addsi3_carryin_clobercc): Similarly.
+ (addsi3_carryin_shift): Similarly. Do not allow register shifts in
+ Thumb2 state.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (arm_subdi3): Delete insn.
+ (zextendsidi_negsi, negdi_extendsidi): Delete insn_and_split.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-modes.def (CC_RSB): New CC mode.
+ * config/arm/predicates.md (arm_borrow_operation): Handle CC_RSBmode.
+ * config/arm/arm.c (arm_select_cc_mode): Detect when we should
+ return CC_RSBmode.
+ (maybe_get_arm_condition_code): Handle CC_RSBmode.
+ * config/arm/arm.md (subsi3_carryin): Make this pattern available to
+ expand.
+ (subdi3): Rewrite to early-expand the sub-operations.
+ (rsb_im_compare): New pattern.
+ (negdi2): Delete.
+ (negdi2_insn): Delete.
+ (arm_negsi2): Correct type attribute to alu_imm.
+ (negsi2_0compare): New insn pattern.
+ (negsi2_carryin): New insn pattern.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (addsi3_carryin_alt2): Use arm_not_operand for
+ operand 2.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
+ to match canonical form.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand.
+ (extend<mode>di2): Likewise.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
+ * config/arm/arm.c (arm_decompose_di_binop): New function.
+ * config/arm/arm.md (adddi3): Also accept any const_int for op2.
+ If not generating Thumb-1 code, decompose the operation into 32-bit
+ pieces.
+ * add0si_carryin_<optab>: New pattern.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm.md (adddi3): Only accept register operands.
+ (arm_adddi3): Convert to simple insn with no split. Do not accept
+ constants.
+ (adddi_sesidi_di): Delete patern.
+ (adddi_zesidi_di): Likewise.
+ (uaddv<mode>4): Use LTU as condition for branch.
+ (adddi3_compareV): Convert to simple insn with no split.
+ (addsi3_compareV_upper): Delete pattern.
+ (adddi3_compareC): Convert to simple insn with no split. Correct
+ flags setting expression.
+ (addsi3_compareC_upper): Delete pattern.
+ (addsi3_compareC): Correct flags setting expression.
+ (subdi3_compare1): Convert to simple insn with no split.
+ (subsi3_carryin_compare): Delete pattern.
+ (arm_subdi3): Convert to simple insn with no split.
+ (subdi_zesidi): Delete pattern.
+ (subdi_di_sesidi): Delete pattern.
+ (subdi_zesidi_di): Delete pattern.
+ (subdi_sesidi_di): Delete pattern.
+ (subdi_zesidi_zesidi): Delete pattern.
+ (negvdi3): Use s_register_operand.
+ (negdi2_compare): Convert to simple insn with no split.
+ (negdi2_insn): Likewise.
+ (negsi2_carryin_compare): Delete pattern.
+ (negdi_zero_extendsidi): Delete pattern.
+ (arm_cmpdi_insn): Convert to simple insn with no split.
+ (negdi2): Don't call gen_negdi2_neon.
+ * config/arm/neon.md (adddi3_neon): Delete pattern.
+ (subdi3_neon): Delete pattern.
+ (negdi2_neon): Delete pattern.
+ (splits for negdi2_neon): Delete splits.
+
+2019-10-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/92153
+ * ggc-page.c (release_pages): Read g->alloc_size before free rather
+ than after it.
+
+2019-10-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/t-multilib: Add rule to regenerate mutlilib header file
+ with any change to t-multilib, t-aprofile and t-rmprofile. Also add
+ new multilib variants and new mappings.
+
+2019-10-18 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/86040
+ * config/avr/avr.c (avr_out_lpm): Do not shortcut-return.
+
+2019-10-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+ Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/86753
+ * tree-vectorizer.h (scalar_cond_masked_key): New struct,
+ and define hashmap traits for it.
+ (loop_vec_info::scalar_cond_masked_set): New member.
+ (vect_record_loop_mask): Adjust prototype.
+ * tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree):
+ Implement method.
+ * tree-vect-loop.c (vectorizable_reduction): Pass NULL as last arg to
+ vect_record_loop_mask.
+ (vectorizable_live_operation): Likewise.
+ (vect_record_loop_mask): New param scalar_mask. Add entry
+ cond, loop_mask to scalar_cond_masked_set if scalar_mask is non NULL.
+ * tree-vect-stmts.c (check_load_store_masking): New param scalar_mask.
+ Pass it as last arg to vect_record_loop_mask.
+ (vectorizable_call): Pass scalar_mask as last arg to
+ vect_record_loop_mask.
+ (vectorizable_store): Likewise.
+ (vectorizable_load): Likewise.
+ (vectorizable_condition): Check if another part of vectorized code
+ applies loop_mask to condition or to it's inverse, and if yes,
+ apply loop_mask to result of vector comparison.
+
+2019-10-17 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.c (pa_output_indirect_call): Fix typos in last change.
+
+2019-10-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/92056
+ * tree-ssa-strlen.c (determine_min_objsize): Call init_object_sizes
+ before calling compute_builtin_object_size.
+
+2019-10-17 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/65342
+ * config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete.
+ (movdi_low_st): Delete.
+ * config/rs6000/rs6000.c
+ (darwin_rs6000_legitimate_lo_sum_const_p): New.
+ (mem_operand_gpr): Validate Mach-O LO_SUM cases separately.
+ * config/rs6000/rs6000.md (movsi_low): Delete.
+
+2019-10-17 Jason Merrill <jason@redhat.com>
+
+ * gimplify.h (get_initialized_tmp_var): Add default argument to
+ post_p.
+ * gimplify.c (gimplify_self_mod_expr, gimplify_omp_atomic): Remove
+ NULL post_p argument.
+ * targhooks (std_gimplify_va_arg_expr): Likewise.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
+ (STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
+ * tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
+ initialize STMT_VINFO_VEC_COND_REDUC_CODE.
+ * tree-vect-loop.c (vect_is_simple_reduction): Set
+ STMT_VINFO_REDUC_CODE.
+ (vectorizable_reduction): Remove dead and redundant code, use
+ STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.
+
+2019-10-17 Georg-Johann Lay <avr@gjlay.de>
+
+ Fix breakage introduced by r276985.
+
+ * config/avr/avr.c (avr_option_override): Remove set of
+ PARAM_ALLOW_STORE_DATA_RACES.
+ * common/config/avr/avr-common.c (avr_option_optimization_table)
+ [OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.
+
+2019-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.h (processor_costs): Add clear_ratio.
+ (CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
+ * config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
+ of 6 and move_ratio in all cost models.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (check_reduction_path): Compute reduction
+ operation here.
+ (vect_is_simple_reduction): Remove special-case of single-stmt
+ reduction path detection.
+
+2019-10-17 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.
+
+2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
+
+ * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
+ (aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
+ (aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
+ (aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
+ New combine patterns.
+ * config/aarch64/iterators.md (BSL_DUP): New int iterator for the
+ above.
+ (bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
+
+2019-10-17 Aldy Hernandez <aldyh@redhat.com>
+
+ * tree-vrp.c (value_range_base::dump): Display +INF for both
+ pointers and integers when appropriate.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_analyze_loop_2): Use same condition to decide
+ when to use versioning threshold.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (determine_peel_for_niter): New function contained
+ outlined code from ...
+ (vect_analyze_loop_2): ... here.
+
+2019-10-17 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * tree-vect-loop.c (vect_transform_loop): Move code from here...
+ * tree-vect-loop-manip.c (vect_loop_versioning): ... to here.
+ * tree-vectorizer.h (vect_loop_versioning): Remove unused parameters.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (needs_fold_left_reduction_p): Export.
+ (vect_is_simple_reduction): Move all validity checks ...
+ (vectorizable_reduction): ... here. Compute whether we
+ need a fold-left reduction here.
+ * tree-vect-patterns.c (vect_reassociating_reduction_p): Merge
+ both overloads, check needs_fold_left_reduction_p directly.
+ * tree-vectorizer.h (needs_fold_left_reduction_p): Declare.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-pre.c (create_component_ref_by_pieces_1): Fix
+ TARGET_MEM_REF creation.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/92129
+ * tree-vect-loop.c (vectorizable_reduction): Also fail
+ on GIMPLE_SINGLE_RHS.
+
+2019-10-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/92056
+ * tree-object-size.c (cond_expr_object_size): Return early if then_
+ processing resulted in unknown size.
+
+ PR tree-optimization/92115
+ * tree-ssa-ifcombine.c (ifcombine_ifandif): Force condition into
+ temporary if it could trap.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ PR debug/91887
+ * dwarf2out.c (gen_formal_parameter_die): Also try to match
+ context_die against a DW_TAG_GNU_formal_parameter_pack parent.
+
+2019-10-16 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-ssa-strlen.c (maybe_invalidate): Use
+ HOST_WIDE_INT_PRINT_UNSIGNED instead of "%zu".
+
+2019-10-16 Andrew Burgess <andrew.burgess@embecosm.com>
+ Jim Wilson <jimw@sifive.com>
+
+ * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
+ regs to SIBCALL_REGS.
+ * config/riscv/riscv.c (riscv_regno_to_class): Change argument
+ passing regs to SIBCALL_REGS.
+
+2019-10-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/83821
+ * tree-ssa-strlen.c (maybe_invalidate): Add argument. Consider
+ the length of a string when available.
+ (handle_builtin_memset) Add argument.
+ (handle_store, strlen_check_and_optimize_call): Same.
+ (check_and_optimize_stmt): Same. Pass it to callees.
+
+2019-10-16 Martin Sebor <msebor@redhat.com>
+
+ PR tree-optimization/91996
+ * tree-ssa-strlen.c (maybe_warn_pointless_strcmp): Improve location
+ information.
+ (compare_nonzero_chars): Add an overload.
+ (count_nonzero_bytes): Add an argument. Call overload above.
+ Handle non-constant lengths in some range.
+ (handle_store): Add an argument.
+ (check_and_optimize_stmt): Pass an argument to handle_store.
+
+2019-10-16 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.c (neon_valid_immediate): Clear bytes before use.
+
+2019-10-16 Mihailo Stojanovic <mistojanovic@wavecomp.com>
+
+ * config/mips/mips.c (mips_expand_builtin_insn): Force the
+ operands which correspond to the same input-output register to
+ have the same pseudo assigned to them.
+
2019-10-16 Ilya Leoshkevich <iii@linux.ibm.com>
* cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.
projects / thirdparty / gcc.git / blobdiff