+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (addsi3_carryin_shift_<optab>): Reorder operands
+ to match canonical form.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm.md (zero_extend<mode>di2): Convert to define_expand.
+ (extend<mode>di2): Likewise.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-protos.h (arm_decompose_di_binop): New prototype.
+ * config/arm/arm.c (arm_decompose_di_binop): New function.
+ * config/arm/arm.md (adddi3): Also accept any const_int for op2.
+ If not generating Thumb-1 code, decompose the operation into 32-bit
+ pieces.
+ * add0si_carryin_<optab>: New pattern.
+
+2019-10-18 Richard Earnshaw <rearnsha@arm.com>
+
+ * arm.md (adddi3): Only accept register operands.
+ (arm_adddi3): Convert to simple insn with no split. Do not accept
+ constants.
+ (adddi_sesidi_di): Delete patern.
+ (adddi_zesidi_di): Likewise.
+ (uaddv<mode>4): Use LTU as condition for branch.
+ (adddi3_compareV): Convert to simple insn with no split.
+ (addsi3_compareV_upper): Delete pattern.
+ (adddi3_compareC): Convert to simple insn with no split. Correct
+ flags setting expression.
+ (addsi3_compareC_upper): Delete pattern.
+ (addsi3_compareC): Correct flags setting expression.
+ (subdi3_compare1): Convert to simple insn with no split.
+ (subsi3_carryin_compare): Delete pattern.
+ (arm_subdi3): Convert to simple insn with no split.
+ (subdi_zesidi): Delete pattern.
+ (subdi_di_sesidi): Delete pattern.
+ (subdi_zesidi_di): Delete pattern.
+ (subdi_sesidi_di): Delete pattern.
+ (subdi_zesidi_zesidi): Delete pattern.
+ (negvdi3): Use s_register_operand.
+ (negdi2_compare): Convert to simple insn with no split.
+ (negdi2_insn): Likewise.
+ (negsi2_carryin_compare): Delete pattern.
+ (negdi_zero_extendsidi): Delete pattern.
+ (arm_cmpdi_insn): Convert to simple insn with no split.
+ (negdi2): Don't call gen_negdi2_neon.
+ * config/arm/neon.md (adddi3_neon): Delete pattern.
+ (subdi3_neon): Delete pattern.
+ (negdi2_neon): Delete pattern.
+ (splits for negdi2_neon): Delete splits.
+
+2019-10-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/92153
+ * ggc-page.c (release_pages): Read g->alloc_size before free rather
+ than after it.
+
+2019-10-18 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/arm/t-multilib: Add rule to regenerate mutlilib header file
+ with any change to t-multilib, t-aprofile and t-rmprofile. Also add
+ new multilib variants and new mappings.
+
+2019-10-18 Georg-Johann Lay <avr@gjlay.de>
+
+ PR target/86040
+ * config/avr/avr.c (avr_out_lpm): Do not shortcut-return.
+
+2019-10-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
+ Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/86753
+ * tree-vectorizer.h (scalar_cond_masked_key): New struct,
+ and define hashmap traits for it.
+ (loop_vec_info::scalar_cond_masked_set): New member.
+ (vect_record_loop_mask): Adjust prototype.
+ * tree-vectorizer.c (scalar_cond_masked_key::get_cond_ops_from_tree):
+ Implement method.
+ * tree-vect-loop.c (vectorizable_reduction): Pass NULL as last arg to
+ vect_record_loop_mask.
+ (vectorizable_live_operation): Likewise.
+ (vect_record_loop_mask): New param scalar_mask. Add entry
+ cond, loop_mask to scalar_cond_masked_set if scalar_mask is non NULL.
+ * tree-vect-stmts.c (check_load_store_masking): New param scalar_mask.
+ Pass it as last arg to vect_record_loop_mask.
+ (vectorizable_call): Pass scalar_mask as last arg to
+ vect_record_loop_mask.
+ (vectorizable_store): Likewise.
+ (vectorizable_load): Likewise.
+ (vectorizable_condition): Check if another part of vectorized code
+ applies loop_mask to condition or to it's inverse, and if yes,
+ apply loop_mask to result of vector comparison.
+
+2019-10-17 John David Anglin <danglin@gcc.gnu.org>
+
+ * config/pa/pa.c (pa_output_indirect_call): Fix typos in last change.
+
+2019-10-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/92056
+ * tree-ssa-strlen.c (determine_min_objsize): Call init_object_sizes
+ before calling compute_builtin_object_size.
+
+2019-10-17 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/65342
+ * config/rs6000/darwin.md (movdi_low, movsi_low_st): Delete.
+ (movdi_low_st): Delete.
+ * config/rs6000/rs6000.c
+ (darwin_rs6000_legitimate_lo_sum_const_p): New.
+ (mem_operand_gpr): Validate Mach-O LO_SUM cases separately.
+ * config/rs6000/rs6000.md (movsi_low): Delete.
+
+2019-10-17 Jason Merrill <jason@redhat.com>
+
+ * gimplify.h (get_initialized_tmp_var): Add default argument to
+ post_p.
+ * gimplify.c (gimplify_self_mod_expr, gimplify_omp_atomic): Remove
+ NULL post_p argument.
+ * targhooks (std_gimplify_va_arg_expr): Likewise.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (_stmt_vec_info::cond_reduc_code): Remove.
+ (STMT_VINFO_VEC_COND_REDUC_CODE): Likewise.
+ * tree-vectorizer.c (vec_info::new_stmt_vec_info): Do not
+ initialize STMT_VINFO_VEC_COND_REDUC_CODE.
+ * tree-vect-loop.c (vect_is_simple_reduction): Set
+ STMT_VINFO_REDUC_CODE.
+ (vectorizable_reduction): Remove dead and redundant code, use
+ STMT_VINFO_REDUC_CODE instead of STMT_VINFO_VEC_COND_REDUC_CODE.
+
+2019-10-17 Georg-Johann Lay <avr@gjlay.de>
+
+ Fix breakage introduced by r276985.
+
+ * config/avr/avr.c (avr_option_override): Remove set of
+ PARAM_ALLOW_STORE_DATA_RACES.
+ * common/config/avr/avr-common.c (avr_option_optimization_table)
+ [OPT_LEVELS_ALL]: Turn on -fallow-store-data-races.
+
+2019-10-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/i386/i386.h (processor_costs): Add clear_ratio.
+ (CLEAR_RATIO): Remove MIN and use ix86_cost->clear_ratio.
+ * config/i386/x86-tune-costs.h: Set clear_ratio to the minimum
+ of 6 and move_ratio in all cost models.
+
+2019-10-17 Richard Biener <rguenther@suse.de>
+
+ * tree-vect-loop.c (check_reduction_path): Compute reduction
+ operation here.
+ (vect_is_simple_reduction): Remove special-case of single-stmt
+ reduction path detection.
+
+2019-10-17 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/arm/arm-cpus.in (marvel-pj4): Add +fp to the architecture.
+
+2019-10-17 Yuliang Wang <yuliang.wang@arm.com>
+
+ * config/aarch64/aarch64-sve2.md (aarch64_sve2_eor3<mode>)
+ (aarch64_sve2_nor<mode>, aarch64_sve2_nand<mode>)
+ (aarch64_sve2_bsl<mode>, aarch64_sve2_nbsl<mode>)
+ (aarch64_sve2_bsl1n<mode>, aarch64_sve2_bsl2n<mode>):
+ New combine patterns.
+ * config/aarch64/iterators.md (BSL_DUP): New int iterator for the
+ above.
+ (bsl_1st, bsl_2nd, bsl_dup, bsl_mov): Attributes for the above.
+
2019-10-17 Aldy Hernandez <aldyh@redhat.com>
- PR tree-optimization/92131
* tree-vrp.c (value_range_base::dump): Display +INF for both
pointers and integers when appropriate.
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