xtensa: fix PR target/90922

[thirdparty/gcc.git] / gcc / ChangeLog

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 15bc6d734ad90749e8896677c939d4eb5833eff0..d8b56f6472fdc3166dea2d327dca4798fea8a467 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,108 @@
+2019-06-18  Max Filippov  <jcmvbkbc@gmail.com>
+
+       PR target/90922
+       * config/xtensa/xtensa.c (xtensa_expand_prologue): Add stack
+       pointer adjustment for the case of no callee-saved registers and
+       stack frame bigger than 128 bytes.
+
+2019-06-18  Thomas Schwinge  <thomas@codesourcery.com>
+
+       PR middle-end/90862
+       * omp-low.c (check_omp_nesting_restrictions): Handle
+       GF_OMP_TARGET_KIND_OACC_DECLARE.
+
+2019-06-18  Uroš Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (@cmp<mode>_1): Rename from cmp<mode>_1.
+       (@add<mode>3_carry): Rename from add<mode>3_carry.
+       (@sub<mode>3_carry_ccc): Rename from sub<mode>3_carry_ccc.
+       (@sub<mode>3_carry_ccgz): Rename form sub<mode>3_carry_ccgz.
+       (@copysign<mode>3_const): Rename from copysign<mode>3_const.
+       (@copysign<mode>3_var): Rename from copysign<mode>3_var.
+       (@xorsign<mode>3_1): Rename from xorsign<mode>3_1.
+       (@x86_shift<mode>_adj_1): Rename from x86_shift<mode>_adj_1.
+       (@x86_shift<mode>_adj_2): Rename from x86_shift<mode>_adj_2.
+       (@x86_shift<mode>_adj_3): Rename from x86_shift<mode>_adj_3.
+       (cmpstrnsi): Use gen_cmp_1.
+       (lwp_slwpcb): Use gen_lwp_slwpcb_1.
+       (@lwp_slwpcb<mode>_1): Rename from lwp_slwpcb<mode>_1.
+       (@umonitor_<mode>): Rename from umonitor_<mode>.
+       * config/i386/i386-expand.c (ix86_expand_copysign):
+       Use gen_copysign3_const and gen_copysign3_var.
+       (ix86_expand_xorsign): Use gen_xorsign3_1.
+       (ix86_expand_branch): Use gen_sub3_carry_ccc,
+       gen_sub3_carry_ccgz and gen_cmp1.
+       (ix86_expand_int_addcc): Use gen_sub3_carry and gen_add3_carry.
+       (ix86_split_ashl): Use gen_x86_shift_adj_1 and gen_x86_shift_adj_2.
+       (ix86_split_ashr): Use gen_x86_shift_adj_1 and gen_x86_shift_adj_3.
+       (ix86_split_lshr): Ditto.
+       (ix86_expand_builtin) <case IX86_BUILTIN_UMONITOR>: Use gen_umonitor.
+
+2019-06-18  Jason Merrill  <jason@redhat.com>
+
+       * tree.c (build_constructor): Add MEM_STAT_DECL.
+
+2019-06-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-modes.def (CC_NZC): New CC_MODE.
+       * config/aarch64/aarch64-sve.md (*<optab><mode>3_cc)
+       (ptest_ptrue<mode>, while_ult<GPI:mode><PRED_ALL:mode>)
+       (*while_ult<GPI:mode><PRED_ALL:mode>_cc, *cmp<cmp_op><mode>)
+       (*cmp<cmp_op><mode>_ptest, *cmp<cmp_op><mode>_cc)
+       (*pred_cmp<cmp_op><mode>_combine, *pred_cmp<cmp_op><mode>)
+       (vec_cmp<mode><vpred>, vec_cmpu<mode><vpred>, cbranch<mode>4):
+       Use CC_NZC instead of CC.
+       * config/aarch64/aarch64.md (condjump): Print a '.' in SVE conditions.
+       * config/aarch64/aarch64.c (aarch64_sve_condition_codes): New variable.
+       (aarch64_print_operand): Handle E_CC_NZCmode.
+       (aarch64_emit_sve_ptrue_op_cc): Use gen_set_clobber_cc_nzc instead
+       of gen_set_clobber_cc.
+
+2019-06-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve.md: Tabify file.
+
+2019-06-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_pfalse_reg): Declare.
+       * config/aarch64/aarch64.c (aarch64_pfalse_reg): New function.
+       * config/aarch64/aarch64-sve.md: Use it.
+
+2019-06-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-protos.h (aarch64_ptrue_reg): Declare.
+       * config/aarch64/aarch64.c (aarch64_ptrue_reg): New functions.
+       (aarch64_expand_sve_widened_duplicate, aarch64_expand_sve_mem_move)
+       (aarch64_maybe_expand_sve_subreg_move, aarch64_evpc_rev_local)
+       (aarch64_expand_sve_vec_cmp_int): Use it.
+       (aarch64_expand_sve_vec_cmp_float): Likewise.
+       * config/aarch64/aarch64-sve.md: Likewise throughout.
+
+2019-06-18  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve.md (*cond_<optab><mode>_0): Delete.
+       (*cond_<optab><mode>_z): Fold into...
+       (*cond_<optab><mode>_any): ...here.  Also handle cases in which
+       operand 4 can be tied to operand 0 (either inherently or via RA).
+
+2019-06-18  Richard Biener  <rguenther@suse.de>
+
+       PR debug/90900
+       * cfgexpand.c (expand_debug_expr): Treat NOTE_P DECL_RTL
+       as if optimized away.
+
+2019-06-18  Tom de Vries  <tdevries@suse.de>
+
+       * config/nvptx/nvptx-protos.h (gen_set_softstack_insn): Remove.
+       * config/nvptx/nvptx.c (gen_set_softstack_insn): Remove.
+       * config/nvptx/nvptx.md (define_insn "set_softstack_<mode>"):
+       Rename to ...
+       (define_insn "@set_softstack_<mode>"): ... this.
+       (define_insn "omp_simt_enter_<mode>"): Rename to ...
+       (define_insn "@omp_simt_enter_<mode>"): ... this.
+       (define_insn "omp_simt_exit_<mode>"): Rename to ...
+       (define_insn "@omp_simt_exit_<mode>"): ... this.
+
 2019-06-18  Richard Sandiford  <richard.sandiford@arm.com>
 
        * tree-vect-loop-manip.c (vect_set_loop_masks_directly): Remove