RISC-V: Include more registers in SIBCALL_REGS.

RISC-V: Include more registers in SIBCALL_REGS.

This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
also adds the missing riscv_regno_to_class change.

Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions.  I see about a 0.01% code size reduction for the
C and libstdc++ libraries.

	gcc/
	* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
	regs to SIBCALL_REGS.
	* config/riscv/riscv.c (riscv_regno_to_class): Change argument
	passing regs to SIBCALL_REGS.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@277082 138bc75d-0d04-0410-961f-82ee72b054a4