RISC-V: Include more registers in SIBCALL_REGS.

This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
also adds the missing riscv_regno_to_class change.

Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
There were no regressions.  I see about a 0.01% code size reduction for the
C and libstdc++ libraries.

	gcc/
	* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
	regs to SIBCALL_REGS.
	* config/riscv/riscv.c (riscv_regno_to_class): Change argument
	passing regs to SIBCALL_REGS.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@277082 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b81945b6eb2c86bed4ed303bc0babe4a04b303cd..5c56e0abfb910732c219f6e61f0903303ee97407 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-10-16  Andrew Burgess  <andrew.burgess@embecosm.com>
+           Jim Wilson  <jimw@sifive.com>
+
+       * config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
+       regs to SIBCALL_REGS.
+       * config/riscv/riscv.c (riscv_regno_to_class): Change argument
+       passing regs to SIBCALL_REGS.
+
 2019-10-16  Martin Sebor  <msebor@redhat.com>
 
        PR tree-optimization/83821

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index b8a8778b92c62321bf0a752b211d266046c46591..77a3ad94aa8e57fada289eeb3d328bf9784b3104 100644 (file)
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -256,9 +256,9 @@ enum riscv_microarchitecture_type riscv_microarchitecture;
 const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
   GR_REGS,     GR_REGS,        GR_REGS,        GR_REGS,
   GR_REGS,     GR_REGS,        SIBCALL_REGS,   SIBCALL_REGS,
-  JALR_REGS,   JALR_REGS,      JALR_REGS,      JALR_REGS,
-  JALR_REGS,   JALR_REGS,      JALR_REGS,      JALR_REGS,
-  JALR_REGS,   JALR_REGS,      JALR_REGS,      JALR_REGS,
+  JALR_REGS,   JALR_REGS,      SIBCALL_REGS,   SIBCALL_REGS,
+  SIBCALL_REGS,        SIBCALL_REGS,   SIBCALL_REGS,   SIBCALL_REGS,
+  SIBCALL_REGS,        SIBCALL_REGS,   JALR_REGS,      JALR_REGS,
   JALR_REGS,   JALR_REGS,      JALR_REGS,      JALR_REGS,
   JALR_REGS,   JALR_REGS,      JALR_REGS,      JALR_REGS,
   SIBCALL_REGS,        SIBCALL_REGS,   SIBCALL_REGS,   SIBCALL_REGS,

diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 5fc9be8edbf212454623b1c978fc940803f56917..246494663f64870a2e09c120660153d1130606b5 100644 (file)
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -400,7 +400,7 @@ enum reg_class
 #define REG_CLASS_CONTENTS                                             \
 {                                                                      \
   { 0x00000000, 0x00000000, 0x00000000 },      /* NO_REGS */           \
-  { 0xf00000c0, 0x00000000, 0x00000000 },      /* SIBCALL_REGS */      \
+  { 0xf003fcc0, 0x00000000, 0x00000000 },      /* SIBCALL_REGS */      \
   { 0xffffffc0, 0x00000000, 0x00000000 },      /* JALR_REGS */         \
   { 0xffffffff, 0x00000000, 0x00000000 },      /* GR_REGS */           \
   { 0x00000000, 0xffffffff, 0x00000000 },      /* FP_REGS */           \