S/390: arch13: vector shift double by bit builtins

gcc/ChangeLog:

2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>

	* config/s390/s390-builtin-types.def: Add new builtin function
	types.
	* config/s390/s390-builtins.def (s390_vec_sldb, s390_vec_srdb):
	New overloaded builtins.
	(s390_vec_sldb, s390_vec_srdb): New low-level builtins.  and
	s390_vsrd.
	* config/s390/s390.md (UNSPEC_VEC_SLDB): Rename to ...
	(UNSPEC_VEC_SLDBYTE): ... this.
	(UNSPEC_VEC_SLDBIT, UNSPEC_VEC_SRDBIT): New constant definitions.
	* config/s390/vecintrin.h (vec_sldb, vec_srdb): New builtin name
	definitions.
	* config/s390/vx-builtins.md ("vec_sld<mode>", "vec_sldw<mode>"):
	Rename UNSPEC_VEC_SLDB to UNSPEC_VEC_SLDBYTE.
	("vec_sldb<mode>", "vec_srdb<mode>"): New insn definitions.

gcc/testsuite/ChangeLog:

2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>

	* gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c: New test.
	* gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270089 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bf0b3276f914795ce04aadaa337d73c07e8038f1..bfc101f3754ee6dd1a77cf6040eb8596bf408571 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,20 @@
+2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       * config/s390/s390-builtin-types.def: Add new builtin function
+       types.
+       * config/s390/s390-builtins.def (s390_vec_sldb, s390_vec_srdb):
+       New overloaded builtins.
+       (s390_vec_sldb, s390_vec_srdb): New low-level builtins.  and
+       s390_vsrd.
+       * config/s390/s390.md (UNSPEC_VEC_SLDB): Rename to ...
+       (UNSPEC_VEC_SLDBYTE): ... this.
+       (UNSPEC_VEC_SLDBIT, UNSPEC_VEC_SRDBIT): New constant definitions.
+       * config/s390/vecintrin.h (vec_sldb, vec_srdb): New builtin name
+       definitions.
+       * config/s390/vx-builtins.md ("vec_sld<mode>", "vec_sldw<mode>"):
+       Rename UNSPEC_VEC_SLDB to UNSPEC_VEC_SLDBYTE.
+       ("vec_sldb<mode>", "vec_srdb<mode>"): New insn definitions.
+
 2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>
 
        ("*vec_splats_bswap_vec<mode>", "*vec_splats_bswap_elem<mode>"):

diff --git a/gcc/config/s390/s390-builtin-types.def b/gcc/config/s390/s390-builtin-types.def
index ff53ec541f8db914c572fc1d1a9eaea15c9e8849..c0dd2086cde91fa47a6e64a171407498b0cde74b 100644 (file)
--- a/gcc/config/s390/s390-builtin-types.def
+++ b/gcc/config/s390/s390-builtin-types.def
@@ -285,6 +285,7 @@ DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INT
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_INTPTR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_INTPTR)
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_OV4SI)
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UCHAR, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UCHAR)
+DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_UINT, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_UINT)
 DEF_FN_TYPE_3 (BT_FN_OV4SI_OV4SI_OV4SI_ULONGLONG, BT_OV4SI, BT_OV4SI, BT_OV4SI, BT_ULONGLONG)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UCHAR_INT, BT_UV16QI, BT_UV16QI, BT_UCHAR, BT_INT)
 DEF_FN_TYPE_3 (BT_FN_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT)
@@ -513,6 +514,7 @@ DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_BV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI,
 DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INT)
 DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR)
 DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UCHAR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UCHAR)
+DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UINT, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UINT)
 DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_ULONGLONG, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_UV16QI_UV16QI_UV16QI_UV16QI_INTPTR, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_UV16QI, BT_INTPTR)
@@ -544,6 +546,7 @@ DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI)
 DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_BV2DI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_INT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_INT)
 DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UCHAR)
+DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UINT, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UINT)
 DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONG, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_ULONGLONGCONSTPTR_UCHAR, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_ULONGLONGCONSTPTR, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_UV2DI_UV2DI_UV2DI_UV16QI, BT_UV2DI, BT_UV2DI, BT_UV2DI, BT_UV16QI)
@@ -581,6 +584,7 @@ DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_BV4SI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_BV4
 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INT)
 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_INTPTR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_INTPTR)
 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UCHAR)
+DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINT, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINT)
 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UINTCONSTPTR_UCHAR, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UINTCONSTPTR, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_ULONGLONG, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_UV4SI_UV4SI_UV4SI_UV16QI, BT_UV4SI, BT_UV4SI, BT_UV4SI, BT_UV16QI)
@@ -621,6 +625,7 @@ DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_BV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_BV8
 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INT)
 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_INTPTR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_INTPTR)
 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UCHAR, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UCHAR)
+DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UINT, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UINT)
 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_ULONGLONG, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV16QI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_UV8HI_UV8HI_UV8HI_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI, BT_UV8HI)
@@ -651,6 +656,7 @@ DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI)
 DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_BV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_BV16QI)
 DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INT, BT_V16QI, BT_V16QI, BT_V16QI, BT_INT)
 DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_INTPTR, BT_V16QI, BT_V16QI, BT_V16QI, BT_INTPTR)
+DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UINT, BT_V16QI, BT_V16QI, BT_V16QI, BT_UINT)
 DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_ULONGLONG, BT_V16QI, BT_V16QI, BT_V16QI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_UV16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V16QI_V16QI_V16QI_V16QI, BT_V16QI, BT_V16QI, BT_V16QI, BT_V16QI)
@@ -675,6 +681,7 @@ DEF_OV_TYPE (BT_OV_V2DF_V2DF_UV2DI_DBLCONSTPTR_UCHAR, BT_V2DF, BT_V2DF, BT_UV2DI
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF, BT_V2DF, BT_V2DF, BT_V2DF)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_BV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_INT, BT_V2DF, BT_V2DF, BT_V2DF, BT_INT)
+DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UINT, BT_V2DF, BT_V2DF, BT_V2DF, BT_UINT)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_ULONGLONG, BT_V2DF, BT_V2DF, BT_V2DF, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV16QI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V2DF_V2DF_V2DF_UV2DI, BT_V2DF, BT_V2DF, BT_V2DF, BT_UV2DI)
@@ -705,6 +712,7 @@ DEF_OV_TYPE (BT_OV_V2DI_V2DI_UV8HI, BT_V2DI, BT_V2DI, BT_UV8HI)
 DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI, BT_V2DI, BT_V2DI, BT_V2DI)
 DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_BV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_BV2DI)
 DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_INT, BT_V2DI, BT_V2DI, BT_V2DI, BT_INT)
+DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UINT, BT_V2DI, BT_V2DI, BT_V2DI, BT_UINT)
 DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_ULONGLONG, BT_V2DI, BT_V2DI, BT_V2DI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV16QI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V2DI_V2DI_V2DI_UV2DI, BT_V2DI, BT_V2DI, BT_V2DI, BT_UV2DI)
@@ -728,6 +736,7 @@ DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_UV4SI)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_UV4SI_FLTCONSTPTR_UCHAR, BT_V4SF, BT_V4SF, BT_UV4SI, BT_FLTCONSTPTR, BT_UCHAR)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF, BT_V4SF, BT_V4SF, BT_V4SF)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_BV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_BV4SI)
+DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UINT, BT_V4SF, BT_V4SF, BT_V4SF, BT_UINT)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_ULONGLONG, BT_V4SF, BT_V4SF, BT_V4SF, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV16QI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V4SF_V4SF_V4SF_UV4SI, BT_V4SF, BT_V4SF, BT_V4SF, BT_UV4SI)
@@ -759,6 +768,7 @@ DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI, BT_V4SI, BT_V4SI, BT_V4SI)
 DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_BV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_BV4SI)
 DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INT, BT_V4SI, BT_V4SI, BT_V4SI, BT_INT)
 DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_INTPTR, BT_V4SI, BT_V4SI, BT_V4SI, BT_INTPTR)
+DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UINT, BT_V4SI, BT_V4SI, BT_V4SI, BT_UINT)
 DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_ULONGLONG, BT_V4SI, BT_V4SI, BT_V4SI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV16QI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V4SI_V4SI_V4SI_UV4SI, BT_V4SI, BT_V4SI, BT_V4SI, BT_UV4SI)
@@ -794,6 +804,7 @@ DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI, BT_V8HI, BT_V8HI, BT_V8HI)
 DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_BV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_BV8HI)
 DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INT, BT_V8HI, BT_V8HI, BT_V8HI, BT_INT)
 DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_INTPTR, BT_V8HI, BT_V8HI, BT_V8HI, BT_INTPTR)
+DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UINT, BT_V8HI, BT_V8HI, BT_V8HI, BT_UINT)
 DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_ULONGLONG, BT_V8HI, BT_V8HI, BT_V8HI, BT_ULONGLONG)
 DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV16QI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV16QI)
 DEF_OV_TYPE (BT_OV_V8HI_V8HI_V8HI_UV8HI, BT_V8HI, BT_V8HI, BT_V8HI, BT_UV8HI)

diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def
index e4cfa80adaa691017d3689a5f6053762b60e497f..6ee921d24992d8c2fc94cff5d2199e245f48d7c0 100644 (file)
--- a/gcc/config/s390/s390-builtins.def
+++ b/gcc/config/s390/s390-builtins.def
@@ -2923,3 +2923,31 @@ B_DEF      (s390_vsterf,                eltswapv4si,        0,
 B_DEF      (s390_vsterg,                eltswapv2di,        0,                  B_VX,               0,                   BT_FN_V2DI_V2DI)
 B_DEF      (s390_vsterf_flt,            eltswapv4sf,        0,                  B_VXE,              0,                   BT_FN_V4SF_V4SF)
 B_DEF      (s390_vsterg_dbl,            eltswapv2df,        0,                  B_VX,               0,                   BT_FN_V2DF_V2DF)
+
+OB_DEF     (s390_vec_sldb,              s390_vec_sldb_s8,   s390_vec_sldb_dbl,  B_VXE2,             BT_FN_OV4SI_OV4SI_OV4SI_UINT)
+OB_DEF_VAR (s390_vec_sldb_s8,           s390_vsld,          0,                  O3_U3,              BT_OV_V16QI_V16QI_V16QI_UINT)
+OB_DEF_VAR (s390_vec_sldb_u8,           s390_vsld,          0,                  O3_U3,              BT_OV_UV16QI_UV16QI_UV16QI_UINT)
+OB_DEF_VAR (s390_vec_sldb_s16,          s390_vsld,          0,                  O3_U3,              BT_OV_V8HI_V8HI_V8HI_UINT)
+OB_DEF_VAR (s390_vec_sldb_u16,          s390_vsld,          0,                  O3_U3,              BT_OV_UV8HI_UV8HI_UV8HI_UINT)
+OB_DEF_VAR (s390_vec_sldb_s32,          s390_vsld,          0,                  O3_U3,              BT_OV_V4SI_V4SI_V4SI_UINT)
+OB_DEF_VAR (s390_vec_sldb_u32,          s390_vsld,          0,                  O3_U3,              BT_OV_UV4SI_UV4SI_UV4SI_UINT)
+OB_DEF_VAR (s390_vec_sldb_s64,          s390_vsld,          0,                  O3_U3,              BT_OV_V2DI_V2DI_V2DI_UINT)
+OB_DEF_VAR (s390_vec_sldb_u64,          s390_vsld,          0,                  O3_U3,              BT_OV_UV2DI_UV2DI_UV2DI_UINT)
+OB_DEF_VAR (s390_vec_sldb_flt,          s390_vsld,          0,                  O3_U3,              BT_OV_V4SF_V4SF_V4SF_UINT)
+OB_DEF_VAR (s390_vec_sldb_dbl,          s390_vsld,          0,                  O3_U3,              BT_OV_V2DF_V2DF_V2DF_UINT)
+
+B_DEF      (s390_vsld,                  vec_sldbv16qi,      0,                  B_VXE2,             O3_U3,              BT_FN_UV16QI_UV16QI_UV16QI_INT)
+
+OB_DEF     (s390_vec_srdb,              s390_vec_srdb_s8,   s390_vec_srdb_dbl,  B_VXE2,             BT_FN_OV4SI_OV4SI_OV4SI_UINT)
+OB_DEF_VAR (s390_vec_srdb_s8,           s390_vsrd,          0,                  O3_U3,              BT_OV_V16QI_V16QI_V16QI_UINT)
+OB_DEF_VAR (s390_vec_srdb_u8,           s390_vsrd,          0,                  O3_U3,              BT_OV_UV16QI_UV16QI_UV16QI_UINT)
+OB_DEF_VAR (s390_vec_srdb_s16,          s390_vsrd,          0,                  O3_U3,              BT_OV_V8HI_V8HI_V8HI_UINT)
+OB_DEF_VAR (s390_vec_srdb_u16,          s390_vsrd,          0,                  O3_U3,              BT_OV_UV8HI_UV8HI_UV8HI_UINT)
+OB_DEF_VAR (s390_vec_srdb_s32,          s390_vsrd,          0,                  O3_U3,              BT_OV_V4SI_V4SI_V4SI_UINT)
+OB_DEF_VAR (s390_vec_srdb_u32,          s390_vsrd,          0,                  O3_U3,              BT_OV_UV4SI_UV4SI_UV4SI_UINT)
+OB_DEF_VAR (s390_vec_srdb_s64,          s390_vsrd,          0,                  O3_U3,              BT_OV_V2DI_V2DI_V2DI_UINT)
+OB_DEF_VAR (s390_vec_srdb_u64,          s390_vsrd,          0,                  O3_U3,              BT_OV_UV2DI_UV2DI_UV2DI_UINT)
+OB_DEF_VAR (s390_vec_srdb_flt,          s390_vsrd,          0,                  O3_U3,              BT_OV_V4SF_V4SF_V4SF_UINT)
+OB_DEF_VAR (s390_vec_srdb_dbl,          s390_vsrd,          0,                  O3_U3,              BT_OV_V2DF_V2DF_V2DF_UINT)
+
+B_DEF      (s390_vsrd,                  vec_srdbv16qi,      0,                  B_VXE2,             O3_U3,              BT_FN_UV16QI_UV16QI_UV16QI_INT)

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index bdc7385cfe4e7b04275d464bbfe4dba431a4f059..56ad11fe3d71db0781eff4a80095cd667ee5ac9c 100644 (file)
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -194,7 +194,9 @@
    UNSPEC_VEC_RL_MASK
    UNSPEC_VEC_SLL
    UNSPEC_VEC_SLB
-   UNSPEC_VEC_SLDB
+   UNSPEC_VEC_SLDBYTE
+   UNSPEC_VEC_SLDBIT
+   UNSPEC_VEC_SRDBIT
    UNSPEC_VEC_SRAL
    UNSPEC_VEC_SRAB
    UNSPEC_VEC_SRL

diff --git a/gcc/config/s390/vecintrin.h b/gcc/config/s390/vecintrin.h
index 05707a136c1d7badcda61020caeee408f274bf8b..fb60a77ba06dc03044207c547137befe0368d0d4 100644 (file)
--- a/gcc/config/s390/vecintrin.h
+++ b/gcc/config/s390/vecintrin.h
@@ -327,4 +327,6 @@ __lcbb(const void *ptr, int bndry)
 #define vec_fp_test_data_class __builtin_s390_vec_fp_test_data_class
 #define vec_revb __builtin_s390_vec_revb
 #define vec_reve __builtin_s390_vec_reve
+#define vec_sldb __builtin_s390_vec_sldb
+#define vec_srdb __builtin_s390_vec_srdb
 #endif /* _VECINTRIN_H */

diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 1595ffb369567da698c2d093fe42f79a2e56233b..1c42d4e679b0630a531dafb86e594a39f7bfe911 100644 (file)
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -1030,7 +1030,7 @@
        (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
                      (match_operand:V_HW 2 "register_operand" "v")
                      (match_operand:QI 3 "const_int_operand"  "C")]
-                    UNSPEC_VEC_SLDB))]
+                    UNSPEC_VEC_SLDBYTE))]
   "TARGET_VX"
   "vsldb\t%v0,%v1,%v2,%b3"
   [(set_attr "op_type" "VRI")])
@@ -1040,12 +1040,36 @@
        (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "")
                      (match_operand:V_HW 2 "register_operand" "")
                      (match_operand:QI 3 "const_int_operand"  "")]
-                    UNSPEC_VEC_SLDB))]
+                    UNSPEC_VEC_SLDBYTE))]
   "TARGET_VX"
 {
   operands[3] = GEN_INT (INTVAL (operands[3]) << 2);
 })
 
+; Vector shift left double by bit
+
+(define_insn "vec_sldb<mode>"
+  [(set (match_operand:V_HW 0 "register_operand"              "=v")
+       (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
+                     (match_operand:V_HW 2 "register_operand" "v")
+                     (match_operand:QI 3 "const_int_operand"  "C")]
+                    UNSPEC_VEC_SLDBIT))]
+  "TARGET_VXE2"
+  "vsld\t%v0,%v1,%v2,%b3"
+  [(set_attr "op_type" "VRI")])
+
+; Vector shift right double by bit
+
+(define_insn "vec_srdb<mode>"
+  [(set (match_operand:V_HW 0 "register_operand"              "=v")
+       (unspec:V_HW [(match_operand:V_HW 1 "register_operand" "v")
+                     (match_operand:V_HW 2 "register_operand" "v")
+                     (match_operand:QI 3 "const_int_operand"  "C")]
+                    UNSPEC_VEC_SRDBIT))]
+  "TARGET_VXE2"
+  "vsrd\t%v0,%v1,%v2,%b3"
+  [(set_attr "op_type" "VRI")])
+
 ; Vector shift right arithmetic
 
 (define_insn "vec_sral<VI_HW:mode><VI_HW_QHS:mode>"

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dfd5f16857a8fc386e9ee6d60c31b6700446dca3..693655b5e5d30a4abff4eb56e85f0162fb03b2cb 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>
+
+       * gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c: New test.
+       * gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c: New test.
+
 2019-04-02  Andreas Krebbel  <krebbel@linux.ibm.com>
 
        * gcc.target/s390/zvector/replicate-bswap-1.c: New test.

diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c
new file mode 100644 (file)
index 0000000..5fe1bb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */
+
+#include <vecintrin.h>
+
+vector unsigned char
+foo1 (vector unsigned char a, vector unsigned char b)
+{
+  return vec_sldb (a, b, 0);
+}
+
+vector signed char
+foo2 (vector signed char a, vector signed char b)
+{
+  return vec_sldb (a, b, 1);
+}
+
+
+vector unsigned short
+foo3 (vector unsigned short a, vector unsigned short b)
+{
+  return vec_sldb (a, b, 2);
+}
+
+vector signed short
+foo4 (vector signed short a, vector signed short b)
+{
+  return vec_sldb (a, b, 3);
+}
+
+vector unsigned int
+foo5 (vector unsigned int a, vector unsigned int *b)
+{
+  return vec_sldb (a, *b, 4);
+}
+
+vector signed int
+foo6 (vector signed int a, vector signed int b)
+{
+  return vec_sldb (a, b, 5);
+}
+
+
+vector unsigned long long
+foo7 (vector unsigned long long a, vector unsigned long long b)
+{
+  return vec_sldb (a, (vector unsigned long long){ 1, 2 }, 6);
+}
+
+vector signed long long
+foo8 (vector signed long long a, vector signed long long b)
+{
+  return vec_sldb (a, b, 7);
+}
+
+
+vector float
+foo9 (vector float a, vector float b)
+{
+  return vec_sldb (a, b, 1);
+}
+
+vector double
+foo10 (vector double a, vector double b)
+{
+  return vec_sldb (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 10 } } */

diff --git a/gcc/testsuite/gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c
new file mode 100644 (file)
index 0000000..dce3b8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c
@@ -0,0 +1,69 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mzarch -march=arch13 -mzvector -fno-asynchronous-unwind-tables -dp" } */
+
+#include <vecintrin.h>
+
+vector unsigned char
+foo1 (vector unsigned char a, vector unsigned char b)
+{
+  return vec_srdb (a, b, 0);
+}
+
+vector signed char
+foo2 (vector signed char a, vector signed char b)
+{
+  return vec_srdb (a, b, 1);
+}
+
+
+vector unsigned short
+foo3 (vector unsigned short a, vector unsigned short b)
+{
+  return vec_srdb (a, b, 2);
+}
+
+vector signed short
+foo4 (vector signed short a, vector signed short b)
+{
+  return vec_srdb (a, b, 3);
+}
+
+vector unsigned int
+foo5 (vector unsigned int a, vector unsigned int *b)
+{
+  return vec_srdb (a, *b, 4);
+}
+
+vector signed int
+foo6 (vector signed int a, vector signed int b)
+{
+  return vec_srdb (a, b, 5);
+}
+
+
+vector unsigned long long
+foo7 (vector unsigned long long a, vector unsigned long long b)
+{
+  return vec_srdb (a, (vector unsigned long long){ 1, 2 }, 6);
+}
+
+vector signed long long
+foo8 (vector signed long long a, vector signed long long b)
+{
+  return vec_srdb (a, b, 7);
+}
+
+
+vector float
+foo9 (vector float a, vector float b)
+{
+  return vec_srdb (a, b, 1);
+}
+
+vector double
+foo10 (vector double a, vector double b)
+{
+  return vec_srdb (a, b, 3);
+}
+
+/* { dg-final { scan-assembler-times "vsrd" 10 } } */