x86: Use explicit shift count in double-precision shifts

Don't use implicit shift count in double-precision shifts in AT&T syntax
since they aren't in Intel SDM.  Keep the 's' modifier for backward
compatibility with inline asm statements.

	PR target/114590
	* config/i386/i386.md (x86_64_shld): Use explicit shift count in
	AT&T syntax.
	(x86_64_shld_ndd): Likewise.
	(x86_shld): Likewise.
	(x86_shld_ndd): Likewise.
	(x86_64_shrd): Likewise.
	(x86_64_shrd_ndd): Likewise.
	(x86_shrd): Likewise.
	(x86_shrd_ndd): Likewise.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6ac401154e47d477625e30efee4faafe034705c0..bb2c72f3473e685e9eff0977617247558840e500 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -14503,7 +14503,7 @@
                              (and:QI (match_dup 2) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "shld{q}\t{%s2%1, %0|%0, %1, %2}"
+  "shld{q}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
@@ -14524,7 +14524,7 @@
                              (and:QI (match_dup 3) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shld{q}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shld{q}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
 
@@ -14681,7 +14681,7 @@
                              (and:QI (match_dup 2) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "shld{l}\t{%s2%1, %0|%0, %1, %2}"
+  "shld{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")
@@ -14703,7 +14703,7 @@
                              (and:QI (match_dup 3) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shld{l}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shld{l}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])
 
@@ -15792,7 +15792,7 @@
                              (and:QI (match_dup 2) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
-  "shrd{q}\t{%s2%1, %0|%0, %1, %2}"
+  "shrd{q}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
@@ -15813,7 +15813,7 @@
                              (and:QI (match_dup 3) (const_int 63)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shrd{q}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shrd{q}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "DI")])
 
@@ -15971,7 +15971,7 @@
                              (and:QI (match_dup 2) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   ""
-  "shrd{l}\t{%s2%1, %0|%0, %1, %2}"
+  "shrd{l}\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")
@@ -15993,7 +15993,7 @@
                              (and:QI (match_dup 3) (const_int 31)))) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_APX_NDD"
-  "shrd{l}\t{%s3%2, %1, %0|%0, %1, %2, %3}"
+  "shrd{l}\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ishift")
    (set_attr "mode" "SI")])