})
(define_insn_and_split "*ssse3_pshufbv8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")
- (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yv")
- (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")
+ [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw")
+ (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yw")
+ (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw")
(match_operand:V4SI 4 "reg_or_const_vector_operand"
"i,3,3")]
UNSPEC_PSHUFB))
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-Og -march=x86-64 -mavx512vl -fsanitize=thread -fstack-protector-all" } */
+
+typedef char __attribute__((__vector_size__(8))) C;
+typedef int __attribute__((__vector_size__(8))) U;
+typedef int __attribute__((__vector_size__(16))) V;
+typedef int __attribute__((__vector_size__(32))) W;
+typedef long long __attribute__((__vector_size__(64))) L;
+typedef _Float64 __attribute__((__vector_size__(16))) F;
+typedef _Float64 __attribute__((__vector_size__(64))) G;
+C c;
+int i;
+
+U foo0( W v256u32_0,
+ W v256s32_0,
+ V v128u64_0,
+ V v128s64_0,
+ W v256u64_0,
+ W v256s64_0,
+ L v512s64_0,
+ W v256u128_0,
+ W v256s128_0,
+ V v128f32_0,
+ W v256f32_0,
+ F F_0,
+ W v256f64_0,
+ G G_0) {
+ C U_1 = __builtin_ia32_pshufb(c, c);
+ G_0 += __builtin_convertvector(v512s64_0, G);
+ F F_1 = __builtin_shufflevector(F_0, G_0, 2, 2);
+ W W_r = v256u32_0 + v256s32_0 + v256u64_0 + v256s64_0 + v256u128_0 +
+ v256s128_0 + v256f32_0 + v256f64_0;
+ V V_r = ((union {
+ W a;
+ V b;
+ })W_r)
+ .b +
+ i + v128u64_0 + v128s64_0 + v128f32_0 +
+ (V)F_1;
+ U U_r = ((union {
+ V a;
+ U b;
+ })V_r)
+ .b +
+ (U)U_1;
+ return U_r;
+}