[PR target/113001] Fix incorrect operand swapping in conditional move

This bug totally fell off my radar.  Sorry about that.

We have some special casing the conditional move expander to simplify a
conditional move when comparing a register against zero and that same register
is one of the arms.

Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or (ne
(reg) (const_int 0)) where reg is the false arm need not use the fully
generalized conditional move, thus saving an instruction for those cases.

In the NE case we swapped the operands, but didn't swap the condition, which
led to the ICE due to an unrecognized pattern.  THe backend actually has
distinct patterns for those two cases.  So swapping the operands is neither
needed nor advisable.

Regression tested on rv64gc and verified the new tests pass.

Pushing to the trunk.

	PR target/113001
	PR target/112871
gcc/
	* config/riscv/riscv.cc (expand_conditional_move): Do not swap
	operands when the comparison operand is the same as the false
	arm for a NE test.

gcc/testsuite
	* gcc.target/riscv/zicond-ice-3.c: New test.
	* gcc.target/riscv/zicond-ice-4.c: New test.

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 691d967de29024711152a30e42a8b0401f5ef31a..680c4a728e924fcf625932b4495ec51a2a184809 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4633,8 +4633,6 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
               || (code == NE && rtx_equal_p (alt, op0)))
            {
              rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
-             if (!rtx_equal_p (cons, op0))
-               std::swap (alt, cons);
              alt = force_reg (mode, alt);
              emit_insn (gen_rtx_SET (dest,
                                      gen_rtx_IF_THEN_ELSE (mode, cond,

diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c
new file mode 100644 (file)
index 0000000..6509868
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */
+
+long a, b;
+int c, d;
+void e(long *f) {
+  (b = *f) && --b;
+  for (; c;)
+    ;
+}
+void g() {
+  for (; d; d--)
+    e(&a);
+}

diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ice-4.c b/gcc/testsuite/gcc.target/riscv/zicond-ice-4.c
new file mode 100644 (file)
index 0000000..2be02c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zicond-ice-4.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32d" { target { rv32 } } } */
+
+short a, c;
+int b, d, i;
+volatile char e;
+static int f[] = {1, 1};
+long g;
+int volatile h;
+short(j)() { return b ? a : 0; }
+void k() {
+l:
+  h;
+  g = 0;
+  for (; g <= 2; g++) {
+    d | ((i || j() & (0 == f[g])) ^ i) && e;
+    if (c)
+      goto l;
+  }
+}
+