+(define_expand "subvsi4"
+ [(match_operand:SI 0 "s_register_operand")
+ (match_operand:SI 1 "arm_rhs_operand")
+ (match_operand:SI 2 "arm_add_operand")
+ (match_operand 3 "")]
+ "TARGET_32BIT"
+{
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2]))
+ {
+ /* If both operands are constants we can decide the result statically. */
+ wi::overflow_type overflow;
+ wide_int val = wi::sub (rtx_mode_t (operands[1], SImode),
+ rtx_mode_t (operands[2], SImode),
+ SIGNED, &overflow);
+ emit_move_insn (operands[0], GEN_INT (val.to_shwi ()));
+ if (overflow != wi::OVF_NONE)
+ emit_jump_insn (gen_jump (operands[3]));
+ DONE;
+ }
+ else if (CONST_INT_P (operands[2]))
+ {
+ operands[2] = GEN_INT (-INTVAL (operands[2]));
+ /* Special case for INT_MIN. */
+ if (INTVAL (operands[2]) == 0x80000000)
+ emit_insn (gen_subvsi3_intmin (operands[0], operands[1]));
+ else
+ emit_insn (gen_addsi3_compareV_imm (operands[0], operands[1],
+ operands[2]));
+ }
+ else if (CONST_INT_P (operands[1]))
+ emit_insn (gen_subvsi3_imm1 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_subvsi3 (operands[0], operands[1], operands[2]));
+
+ arm_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
+ DONE;
+})
+
+(define_expand "subvdi4"
+ [(match_operand:DI 0 "s_register_operand")
+ (match_operand:DI 1 "s_register_operand")
+ (match_operand:DI 2 "s_register_operand")