Daily bump.

diff --git a/ChangeLog b/ChangeLog
index 1a4009c9576b6900bdc4988e4df148c6312f1d29..2bcc08b1c51702fcb50c34e12f93e628004b7a57 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,7 @@
+2024-03-04  demin.han  <demin.han@starfivetech.com>
+
+       * MAINTAINERS: Add myself
+
 2024-02-28  Fangrui Song  <maskray@gcc.gnu.org>
 
        * MAINTAINERS: Add myself.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 321c6b0a90a974a36f39d59d5161391869c179e4..5eb0d89fa7ecbef24f55c4e4f090f86f8519dca1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,326 @@
+2024-03-04  David Faust  <david.faust@oracle.com>
+
+       * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
+       * config/bpf/bpf.cc (bpf_expand_setmem): New.
+       * config/bpf/bpf.md (setmemdi): New define_expand.
+
+2024-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+       PR rtl-optimization/113010
+       * combine.cc (simplify_comparison): Guard the
+       WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
+       and initialize inner_mode.
+
+2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
+       VMLALDAVAXQ_U cases.
+       (VMLALDAVXQ): Remove iterator.
+       (VMLALDAVXQ_P): Likewise.
+       (VMLALDAVAXQ): Likewise.
+       * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
+       mode iterator attribute with V4BI mode.
+       * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
+       VMLALDAVAXQ_U): Remove unused unspecs.
+
+2024-03-04  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+
+       * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
+       * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
+       attribute.
+       * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
+       vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
+       vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
+       vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
+       vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
+       vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
+       vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
+       vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
+       vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
+       vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
+
+2024-03-04  Stam Markianos-Wright  <stam.markianos-wright@arm.com>
+
+       * config/arm/arm.md (mve_unpredicated_insn): New attribute.
+       * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
+       (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
+       (MVE_VPT_PREDICABLE_INSN_P): Likewise.
+       * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
+       * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
+       (arm_vcx1q<a>v16qi): Likewise.
+       (arm_vcx1qav16qi): Likewise.
+       (arm_vcx1qv16qi): Likewise.
+       (arm_vcx2q<a>_p_v16qi): Likewise.
+       (arm_vcx2q<a>v16qi): Likewise.
+       (arm_vcx2qav16qi): Likewise.
+       (arm_vcx2qv16qi): Likewise.
+       (arm_vcx3q<a>_p_v16qi): Likewise.
+       (arm_vcx3q<a>v16qi): Likewise.
+       (arm_vcx3qav16qi): Likewise.
+       (arm_vcx3qv16qi): Likewise.
+       (@mve_<mve_insn>q_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_<supf>v4si): Likewise.
+       (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_f<mode>): Likewise.
+       (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_m_f<mode>): Likewise.
+       (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
+       (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
+       (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
+       (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
+       (mve_v<absneg_str>q_f<mode>): Likewise.
+       (mve_<mve_addsubmul>q<mode>): Likewise.
+       (mve_<mve_addsubmul>q_f<mode>): Likewise.
+       (mve_vadciq_<supf>v4si): Likewise.
+       (mve_vadciq_m_<supf>v4si): Likewise.
+       (mve_vadcq_<supf>v4si): Likewise.
+       (mve_vadcq_m_<supf>v4si): Likewise.
+       (mve_vandq_<supf><mode>): Likewise.
+       (mve_vandq_f<mode>): Likewise.
+       (mve_vandq_m_<supf><mode>): Likewise.
+       (mve_vandq_m_f<mode>): Likewise.
+       (mve_vandq_s<mode>): Likewise.
+       (mve_vandq_u<mode>): Likewise.
+       (mve_vbicq_<supf><mode>): Likewise.
+       (mve_vbicq_f<mode>): Likewise.
+       (mve_vbicq_m_<supf><mode>): Likewise.
+       (mve_vbicq_m_f<mode>): Likewise.
+       (mve_vbicq_m_n_<supf><mode>): Likewise.
+       (mve_vbicq_n_<supf><mode>): Likewise.
+       (mve_vbicq_s<mode>): Likewise.
+       (mve_vbicq_u<mode>): Likewise.
+       (@mve_vclzq_s<mode>): Likewise.
+       (mve_vclzq_u<mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
+       (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
+       (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
+       (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
+       (mve_vcvtaq_<supf><mode>): Likewise.
+       (mve_vcvtaq_m_<supf><mode>): Likewise.
+       (mve_vcvtbq_f16_f32v8hf): Likewise.
+       (mve_vcvtbq_f32_f16v4sf): Likewise.
+       (mve_vcvtbq_m_f16_f32v8hf): Likewise.
+       (mve_vcvtbq_m_f32_f16v4sf): Likewise.
+       (mve_vcvtmq_<supf><mode>): Likewise.
+       (mve_vcvtmq_m_<supf><mode>): Likewise.
+       (mve_vcvtnq_<supf><mode>): Likewise.
+       (mve_vcvtnq_m_<supf><mode>): Likewise.
+       (mve_vcvtpq_<supf><mode>): Likewise.
+       (mve_vcvtpq_m_<supf><mode>): Likewise.
+       (mve_vcvtq_from_f_<supf><mode>): Likewise.
+       (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
+       (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
+       (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
+       (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
+       (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
+       (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
+       (mve_vcvtq_to_f_<supf><mode>): Likewise.
+       (mve_vcvttq_f16_f32v8hf): Likewise.
+       (mve_vcvttq_f32_f16v4sf): Likewise.
+       (mve_vcvttq_m_f16_f32v8hf): Likewise.
+       (mve_vcvttq_m_f32_f16v4sf): Likewise.
+       (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
+       (mve_vdwdupq_wb_u<mode>_insn): Likewise.
+       (mve_veorq_s><mode>): Likewise.
+       (mve_veorq_u><mode>): Likewise.
+       (mve_veorq_f<mode>): Likewise.
+       (mve_vidupq_m_wb_u<mode>_insn): Likewise.
+       (mve_vidupq_u<mode>_insn): Likewise.
+       (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
+       (mve_viwdupq_wb_u<mode>_insn): Likewise.
+       (mve_vldrbq_<supf><mode>): Likewise.
+       (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
+       (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
+       (mve_vldrbq_z_<supf><mode>): Likewise.
+       (mve_vldrdq_gather_base_<supf>v2di): Likewise.
+       (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
+       (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
+       (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
+       (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
+       (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
+       (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
+       (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
+       (mve_vldrhq_<supf><mode>): Likewise.
+       (mve_vldrhq_fv8hf): Likewise.
+       (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_offset_fv8hf): Likewise.
+       (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
+       (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
+       (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
+       (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
+       (mve_vldrhq_z_<supf><mode>): Likewise.
+       (mve_vldrhq_z_fv8hf): Likewise.
+       (mve_vldrwq_<supf>v4si): Likewise.
+       (mve_vldrwq_fv4sf): Likewise.
+       (mve_vldrwq_gather_base_<supf>v4si): Likewise.
+       (mve_vldrwq_gather_base_fv4sf): Likewise.
+       (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
+       (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
+       (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
+       (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
+       (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
+       (mve_vldrwq_gather_base_z_fv4sf): Likewise.
+       (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
+       (mve_vldrwq_gather_offset_fv4sf): Likewise.
+       (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
+       (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
+       (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
+       (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
+       (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
+       (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
+       (mve_vldrwq_z_<supf>v4si): Likewise.
+       (mve_vldrwq_z_fv4sf): Likewise.
+       (mve_vmvnq_s<mode>): Likewise.
+       (mve_vmvnq_u<mode>): Likewise.
+       (mve_vornq_<supf><mode>): Likewise.
+       (mve_vornq_f<mode>): Likewise.
+       (mve_vornq_m_<supf><mode>): Likewise.
+       (mve_vornq_m_f<mode>): Likewise.
+       (mve_vornq_s<mode>): Likewise.
+       (mve_vornq_u<mode>): Likewise.
+       (mve_vorrq_<supf><mode>): Likewise.
+       (mve_vorrq_f<mode>): Likewise.
+       (mve_vorrq_m_<supf><mode>): Likewise.
+       (mve_vorrq_m_f<mode>): Likewise.
+       (mve_vorrq_m_n_<supf><mode>): Likewise.
+       (mve_vorrq_n_<supf><mode>): Likewise.
+       (mve_vorrq_s<mode>): Likewise.
+       (mve_vorrq_s<mode>): Likewise.
+       (mve_vsbciq_<supf>v4si): Likewise.
+       (mve_vsbciq_m_<supf>v4si): Likewise.
+       (mve_vsbcq_<supf>v4si): Likewise.
+       (mve_vsbcq_m_<supf>v4si): Likewise.
+       (mve_vshlcq_<supf><mode>): Likewise.
+       (mve_vshlcq_m_<supf><mode>): Likewise.
+       (mve_vshrq_m_n_<supf><mode>): Likewise.
+       (mve_vshrq_n_<supf><mode>): Likewise.
+       (mve_vstrbq_<supf><mode>): Likewise.
+       (mve_vstrbq_p_<supf><mode>): Likewise.
+       (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
+       (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
+       (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
+       (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
+       (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
+       (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
+       (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
+       (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
+       (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
+       (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
+       (mve_vstrhq_<supf><mode>): Likewise.
+       (mve_vstrhq_fv8hf): Likewise.
+       (mve_vstrhq_p_<supf><mode>): Likewise.
+       (mve_vstrhq_p_fv8hf): Likewise.
+       (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
+       (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
+       (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
+       (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
+       (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
+       (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
+       (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
+       (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
+       (mve_vstrwq_<supf>v4si): Likewise.
+       (mve_vstrwq_fv4sf): Likewise.
+       (mve_vstrwq_p_<supf>v4si): Likewise.
+       (mve_vstrwq_p_fv4sf): Likewise.
+       (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
+       (mve_vstrwq_scatter_base_fv4sf): Likewise.
+       (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
+       (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
+       (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
+       (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
+       (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
+       (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
+       (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
+       (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
+       (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
+       (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
+       (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
+       (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
+       (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
+       (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
+
+2024-03-04  Marek Polacek  <polacek@redhat.com>
+
+       * doc/extend.texi: Update [[gnu::no_dangling]].
+
+2024-03-04  Andrew Stubbs  <ams@baylibre.com>
+
+       * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
+       * expr.cc (store_constructor): Likewise.
+       (do_store_flag): Likewise.
+
+2024-03-04  Mark Wielaard  <mark@klomp.org>
+
+       * common.opt.urls: Regenerate.
+       * config/avr/avr.opt.urls: Likewise.
+       * config/i386/i386.opt.urls: Likewise.
+       * config/pru/pru.opt.urls: Likewise.
+       * config/riscv/riscv.opt.urls: Likewise.
+       * config/rs6000/rs6000.opt.urls: Likewise.
+
+2024-03-04  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/114197
+       * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
+       there are volatile bitfield accesses.
+       (pass_if_conversion::execute): Throw away result if the
+       if-converted and original loops are not nested as expected.
+
+2024-03-04  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/114164
+       * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
+       the code generated for mask argument setup is not supported.
+
+2024-03-04  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/114203
+       * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
+       adjustment before making the result defined at zero.
+
+2024-03-04  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/114192
+       * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
+       appropriate def for the live out stmt in case of an alternate
+       exit.
+
+2024-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+       PR middle-end/114209
+       * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
+       unshare_expr when creating a MEM_REF from MEM_REF.
+       (bitint_large_huge::lower_stmt): Call unshare_expr.
+
+2024-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/114184
+       * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
+       is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
+       register.
+
+2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>
+
+       PR target/114187
+       * simplify-rtx.cc (simplify_context::simplify_subreg): Call
+       lowpart_subreg to perform type conversion, to avoid confusion
+       over the offset to use in the call to simplify_reg_subreg.
+
 2024-03-03  Greg McGary  <gkm@rivosinc.com>
 
        PR rtl-optimization/113010

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index e000c3cff3f3bf2b22d26fc03e55ec6f3ec70642..8585b3d500e81a199a5baaab54fdabd7a3555ac8 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20240304
+20240305

diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 6a8168165cd535980bc5e23b88c229ae8f829751..a8f5bfbf77201db6f2461fa256f0b45c53b7d623 100644 (file)
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,7 @@
+2024-03-04  Mark Wielaard  <mark@klomp.org>
+
+       * c.opt.urls: Regenerate.
+
 2024-02-22  Jakub Jelinek  <jakub@redhat.com>
 
        PR c/114007

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 347e55c7017ef6ac33e6af4f8f4deda473aeea19..e6a6fbd1eaa810ba580e35c97058d2fbe947a3a7 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2024-03-04  Nathaniel Shead  <nathanieloshead@gmail.com>
+
+       * name-lookup.cc (walk_module_binding): Remove completed FIXME.
+       (do_nonmember_using_decl): Mark redeclared entities as exported
+       when needed. Check for re-exporting internal linkage types.
+
 2024-03-01  Patrick Palka  <ppalka@redhat.com>
 
        PR c++/104919

diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 3adc420b45b0b374fe0422c98cb153e55ecf0b46..95188be48b337594a7ae284d1dcf4943f43cb5d9 100644 (file)
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,39 @@
+2024-03-04  Gaius Mulley  <gaiusmod2@gmail.com>
+
+       PR modula2/114227
+       * gm2-libs-iso/M2RTS.mod (ProcedureChain): Remove.
+       (ProcedureList): Remove.
+       (ExecuteReverse): Remove.
+       (ExecuteTerminationProcedures): Rewrite.
+       (ExecuteInitialProcedures): Rewrite.
+       (AppendProc): Remove.
+       (InstallTerminationProcedure): Rewrite.
+       (InstallInitialProcedure): Rewrite.
+       (InitProcList): Remove.
+       * gm2-libs/M2Dependent.def (InstallTerminationProcedure):
+       New procedure.
+       (ExecuteTerminationProcedures): New procedure.
+       (InstallInitialProcedure): New procedure.
+       (ExecuteInitialProcedures): New procedure.
+       * gm2-libs/M2Dependent.mod (ProcedureChain): New type.
+       (ProcedureList): New type.
+       (ExecuteReverse): New procedure.
+       (ExecuteTerminationProcedures): New procedure.
+       (ExecuteInitialProcedures): New procedure.
+       (AppendProc): New procedure.
+       (InstallTerminationProcedure): New procedure.
+       (InstallInitialProcedure): New procedure.
+       (InitProcList): New procedure.
+       * gm2-libs/M2RTS.mod (ProcedureChain): Remove.
+       (ProcedureList): Remove.
+       (ExecuteReverse): Remove.
+       (ExecuteTerminationProcedures): Rewrite.
+       (ExecuteInitialProcedures): Rewrite.
+       (AppendProc): Remove.
+       (InstallTerminationProcedure): Rewrite.
+       (InstallInitialProcedure): Rewrite.
+       (InitProcList): Remove.
+
 2024-02-25  Gaius Mulley  <gaiusmod2@gmail.com>
 
        PR modula2/113749

diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog
index c6cda1ead22571f5dc0801807f50391d4ec8cfc5..4d2e8b9a62b26ae5f72bde1a6aa5e172bf3ad172 100644 (file)
--- a/gcc/po/ChangeLog
+++ b/gcc/po/ChangeLog
@@ -1,3 +1,7 @@
+2024-03-04  Joseph Myers  <josmyers@redhat.com>
+
+       * sv.po: Update.
+
 2024-02-26  Joseph Myers  <josmyers@redhat.com>
 
        * sv.po, zh_CN.po: Update.

diff --git a/gcc/rust/ChangeLog b/gcc/rust/ChangeLog
index c8049e30fff76233efd252f926fb553dbf99859d..b37ca0e56f43abaeef5246805dc476987799924a 100644 (file)
--- a/gcc/rust/ChangeLog
+++ b/gcc/rust/ChangeLog
@@ -1,3 +1,7 @@
+2024-03-04  Mark Wielaard  <mark@klomp.org>
+
+       * lang.opt.urls: Regenerate.
+
 2024-02-21  0xn4utilus  <gyanendrabanjare8@gmail.com>
 
        * checks/errors/rust-ast-validation.cc (ASTValidation::visit):

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 297ea5c0e51ede52ff99ce99a035d2595b624460..53798655f4e5ccadc4b6d57d6b9509446d3a3f20 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,53 @@
+2024-03-04  Nathaniel Shead  <nathanieloshead@gmail.com>
+
+       * g++.dg/modules/using-12.C: New test.
+       * g++.dg/modules/using-13.h: New test.
+       * g++.dg/modules/using-13_a.C: New test.
+       * g++.dg/modules/using-13_b.C: New test.
+
+2024-03-04  David Faust  <david.faust@oracle.com>
+
+       * gcc.target/bpf/memset-1.c: New test.
+
+2024-03-04  Jan Dubiec  <jdx@o2.pl>
+
+       * gcc.c-torture/execute/20101011-1.c: Do not test on H8 series.
+
+2024-03-04  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/114197
+       * gcc.dg/torture/pr114197.c: New testcase.
+
+2024-03-04  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/114203
+       * gcc.dg/torture/pr114203.c: New testcase.
+
+2024-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+       PR middle-end/114209
+       * gcc.dg/bitint-97.c: New test.
+
+2024-03-04  Xi Ruoyao  <xry111@xry111.site>
+
+       PR testsuite/113418
+       * gcc.dg/pr104992.c (dg-options): Use -fdump-tree-forwprop2
+       instead of -fdump-tree-optimized.
+       (dg-final): Scan forwprop2 dump instead of optimized, and remove
+       the use of vect_int_mod.
+       * lib/target-supports.exp (check_effective_target_vect_int_mod):
+       Remove because it's not used anymore.
+
+2024-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/114184
+       * gcc.target/i386/pr114184.c: New test.
+
+2024-03-04  Roger Sayle  <roger@nextmovesoftware.com>
+
+       PR target/114187
+       * g++.target/i386/pr114187.C: New test case.
+
 2024-03-03  Greg McGary  <gkm@rivosinc.com>
 
        * gcc.c-torture/execute/pr113010.c: New test.

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 4c61f82f4c4360cb5ac84ce81aefe76cc29fefb9..4ef20efc0b9a3d23c85e31820702b99da73d6bae 100644 (file)
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,9 @@
+2024-03-04  Jakub Jelinek  <jakub@redhat.com>
+
+       PR libgomp/114216
+       * target.c (gomp_target_rev): Change host_fn type and corresponding
+       cast from void (*)() to void (*) (void *).
+
 2024-03-01  Jakub Jelinek  <jakub@redhat.com>
            Tobias Burnus  <tburnus@baylibre.com>
 

diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog
index 5b4a78579e0abf0aa0d9ef2ba6cfd2ef35ef4fba..a305046a34ef140efaf1bc183db07db4eec81fae 100644 (file)
--- a/libstdc++-v3/ChangeLog
+++ b/libstdc++-v3/ChangeLog
@@ -1,3 +1,11 @@
+2024-03-04  Jonathan Wakely  <jwakely@redhat.com>
+
+       PR libstdc++/114147
+       * include/std/tuple (tuple::tuple(allocator_arg_t, const Alloc&)):
+       Add missing overload of allocator-extended default constructor.
+       (tuple<T1,T2>::tuple(allocator_arg_t, const Alloc&)): Likewise.
+       * testsuite/20_util/tuple/cons/114147.cc: New test.
+
 2024-02-29  Jonathan Wakely  <jwakely@redhat.com>
 
        * include/std/format (basic_format_arg::handle::__maybe_const_t):