rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932]

As PR109932 shows, builtins __builtin_{un,}pack_vector_int128
should be guarded under vsx rather than power7, as their
corresponding bif patterns have the conditions TARGET_VSX
and VECTOR_MEM_ALTIVEC_OR_VSX_P (V1TImode).  This patch is to
move __builtin_{un,}pack_vector_int128 to stanza vsx to ensure
their supports.

	PR target/109932

gcc/ChangeLog:

	* config/rs6000/rs6000-builtins.def (__builtin_pack_vector_int128,
	__builtin_unpack_vector_int128): Move from stanza power7 to vsx.

gcc/testsuite/ChangeLog:

	* gcc.target/powerpc/pr109932-1.c: New test.
	* gcc.target/powerpc/pr109932-2.c: New test.

(cherry picked from commit ff83d1b47aadcdaf80a4fda84b0dc00bb2cd3641)

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index dd39a27be4077e85b6935198f5a57ef645bbdf60..d2c0565dc62304914064ca42c0e94a76bbe7a5ab 100644 (file)
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2008,6 +2008,13 @@
   const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>);
     XXSPLTD_V2DI vsx_xxspltd_v2di {}
 
+  const vsq __builtin_pack_vector_int128 (unsigned long long, \
+                                          unsigned long long);
+    PACK_V1TI packv1ti {}
+
+  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
+    UNPACK_V1TI unpackv1ti {}
+
 
 ; Power7 builtins (ISA 2.06).
 [power7]
@@ -2029,16 +2036,9 @@
   const unsigned int __builtin_divweu (unsigned int, unsigned int);
     DIVWEU diveu_si {}
 
-  const vsq __builtin_pack_vector_int128 (unsigned long long, \
-                                          unsigned long long);
-    PACK_V1TI packv1ti {}
-
   void __builtin_ppc_speculation_barrier ();
     SPECBARR speculation_barrier {}
 
-  const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>);
-    UNPACK_V1TI unpackv1ti {}
-
 
 ; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing).
 [power7-64]

diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-1.c b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
new file mode 100644 (file)
index 0000000..3e3f9ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-1.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+

diff --git a/gcc/testsuite/gcc.target/powerpc/pr109932-2.c b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
new file mode 100644 (file)
index 0000000..3e3f9ea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr109932-2.c
@@ -0,0 +1,16 @@
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mno-vsx" } */
+
+/* Verify there is no ICE but one expected error message instead.  */
+
+#include <altivec.h>
+
+extern vector signed __int128 res_vslll;
+extern unsigned long long aull[2];
+
+void
+testVectorInt128Pack ()
+{
+  res_vslll = __builtin_pack_vector_int128 (aull[0], aull[1]); /* { dg-error "'__builtin_pack_vector_int128' requires the '-mvsx' option" } */
+}
+