Fix gcc.dg/vect/vect-shift-1.c failure.

* config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
DImode not VECINT24 for operand 2.

From-SVN: r105113

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a16029498b7fc2b3e277c3a2c25494791d4588ff..86ba1b278dfe22fb9990e69a62f251773824d8bb 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 2005-10-07  James E. Wilson  <wilson@specifix.com>
 
+       * config/ia64/vect.md (ashl<mode>3, ashr<mode>3, lshr<mode>3): Use
+       DImode not VECINT24 for operand 2.
+
        PR target/23644
        * doc/invoke.texi (IA-64 Options, item -mtune): Renamed from
        -mtune-arch.

diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index 3d4669bc8bc21665745ceb41101dccd3cbd39997..94380bfcc492690759255fa1f8a4a5892da01516 100644 (file)
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -318,7 +318,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
        (ashift:VECINT24
          (match_operand:VECINT24 1 "gr_register_operand" "r")
-         (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+         (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshl<vecsize> %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])
@@ -327,7 +327,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
        (ashiftrt:VECINT24
          (match_operand:VECINT24 1 "gr_register_operand" "r")
-         (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+         (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshr<vecsize> %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])
@@ -336,7 +336,7 @@
   [(set (match_operand:VECINT24 0 "gr_register_operand" "=r")
        (lshiftrt:VECINT24
          (match_operand:VECINT24 1 "gr_register_operand" "r")
-         (match_operand:VECINT24 2 "gr_reg_or_5bit_operand" "rn")))]
+         (match_operand:DI 2 "gr_reg_or_5bit_operand" "rn")))]
   ""
   "pshr<vecsize>.u %0 = %1, %2"
   [(set_attr "itanium_class" "mmshf")])