&& !arm_const_double_rtx (operands[1])
&& !(TARGET_VFP_DOUBLE && vfp3_const_double_rtx (operands[1])))
{
- rtx clobreg = gen_reg_rtx (DFmode);
+ rtx clobreg = gen_reg_rtx (DImode);
emit_insn (gen_no_literal_pool_df_immediate (operands[0], operands[1],
clobreg));
DONE;
(define_insn_and_split "no_literal_pool_df_immediate"
[(set (match_operand:DF 0 "s_register_operand" "=w")
(match_operand:DF 1 "const_double_operand" "F"))
- (clobber (match_operand:DF 2 "s_register_operand" "=r"))]
+ (clobber (match_operand:DI 2 "s_register_operand" "=r"))]
"arm_disable_literal_pool
&& TARGET_VFP_BASE
&& !arm_const_double_rtx (operands[1])
unsigned HOST_WIDE_INT ival = zext_hwi (buf[order], 32);
ival |= (zext_hwi (buf[1 - order], 32) << 32);
rtx cst = gen_int_mode (ival, DImode);
- emit_move_insn (simplify_gen_subreg (DImode, operands[2], DFmode, 0), cst);
- emit_move_insn (operands[0], operands[2]);
+ emit_move_insn (operands[2], cst);
+ emit_move_insn (operands[0],
+ simplify_gen_subreg (DFmode, operands[2], DImode, 0));
DONE;
}
)
--- /dev/null
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_hard_ok } */
+/* { dg-options "-O2 -march=armv7-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mbig-endian -mpure-code" } */
+double f() { return 5.0; }