* config/mips/mips.c (mips_expand_builtin_insn): Force the

	operands which correspond to the same input-output register to
	have the same pseudo assigned to them.

	* gcc.target/mips/msa-dpadd-dpsub.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@277071 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2424b977a5dd22c1702b8a6d2c22117bacb995e1..11d3f13a5135e727a5fd4f7609bc87e248b3f3a4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-10-16  Mihailo Stojanovic  <mistojanovic@wavecomp.com>
+
+       * config/mips/mips.c (mips_expand_builtin_insn): Force the
+       operands which correspond to the same input-output register to
+       have the same pseudo assigned to them.
+
 2019-10-16  Ilya Leoshkevich  <iii@linux.ibm.com>
 
        * cfgrtl.c (find_partition_fixes): Remove bbs_in_cold_partition.

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 7f6a0db46fd31a7f05e5c08f71cef60383bf6860..3a77097766887e238b8d3da9f7758300ecfb30ba 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -16960,6 +16960,26 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
       std::swap (ops[1], ops[3]);
       break;
 
+    case CODE_FOR_msa_dpadd_s_w:
+    case CODE_FOR_msa_dpadd_s_h:
+    case CODE_FOR_msa_dpadd_s_d:
+    case CODE_FOR_msa_dpadd_u_w:
+    case CODE_FOR_msa_dpadd_u_h:
+    case CODE_FOR_msa_dpadd_u_d:
+    case CODE_FOR_msa_dpsub_s_w:
+    case CODE_FOR_msa_dpsub_s_h:
+    case CODE_FOR_msa_dpsub_s_d:
+    case CODE_FOR_msa_dpsub_u_w:
+    case CODE_FOR_msa_dpsub_u_h:
+    case CODE_FOR_msa_dpsub_u_d:
+      /* Force the operands which correspond to the same in-out register
+         to have the same pseudo assigned to them.  If the input operand
+         is not REG, create one for it.  */
+      if (!REG_P (ops[1].value))
+       ops[1].value = copy_to_mode_reg (ops[1].mode, ops[1].value);
+      create_output_operand (&ops[0], ops[1].value, ops[1].mode);
+      break;
+
     default:
       break;
   }

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2c1d794c928b44f332ce10a103208bcbb7a237f1..2641821dad8e474fd0f738df67cc48419bcb672f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-10-16  Mihailo Stojanovic  <mistojanovic@wavecomp.com>
+
+       * gcc.target/mips/msa-dpadd-dpsub.c: New test.
+
 2019-10-16  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * gcc.target/aarch64/symbol-range.c: Improve testcase.

diff --git a/gcc/testsuite/gcc.target/mips/msa-dpadd-dpsub.c b/gcc/testsuite/gcc.target/mips/msa-dpadd-dpsub.c
new file mode 100644 (file)
index 0000000..c665bdf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/msa-dpadd-dpsub.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mfp64 -mhard-float -mmsa" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+typedef short v8i16 __attribute__ ((vector_size (16)));
+typedef int v4i32 __attribute__ ((vector_size (16)));
+
+void foo (int *x, v8i16 *y, v8i16 *z)
+{
+       v4i32 acc[4];
+
+    acc[0] = __builtin_msa_ld_w(x, 0);
+    acc[1] = __builtin_msa_ld_w(x, 16);
+    acc[2] = __builtin_msa_ld_w(x, 32);
+    acc[3] = __builtin_msa_ld_w(x, 48);
+               
+    acc[0] = __builtin_msa_dpadd_s_w(acc[0], y[0], z[0]);
+    acc[1] = __builtin_msa_dpadd_s_w(acc[1], y[1], z[0]);
+    acc[2] = __builtin_msa_dpsub_s_w(acc[2], y[0], z[1]);
+    acc[3] = __builtin_msa_dpsub_s_w(acc[3], y[1], z[1]);
+
+    __builtin_msa_st_w(acc[0], x, 0);
+    __builtin_msa_st_w(acc[1], x, 16);
+    __builtin_msa_st_w(acc[2], x, 32);
+    __builtin_msa_st_w(acc[3], x, 48);
+}
+
+/* { dg-final { scan-assembler-not "move.v" } } */