+(define_expand "addsi3_cin_vout_reg"
+ [(parallel
+ [(set (match_dup 3)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI (match_dup 4)
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand")))
+ (sign_extend:DI (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))])]
+ "TARGET_32BIT"
+ {
+ operands[3] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
+)
+
+(define_insn "*addsi3_cin_vout_reg_insn"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 3 "arm_carry_operation" "")
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "%0,r")))
+ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "l,r")))
+ (sign_extend:DI
+ (plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
+ (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand" "=l,r")
+ (plus:SI (plus:SI (match_dup 4) (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_32BIT"
+ "@
+ adcs%?\\t%0, %0, %2
+ adcs%?\\t%0, %1, %2"
+ [(set_attr "type" "alus_sreg")
+ (set_attr "arch" "t2,*")
+ (set_attr "length" "2,4")]
+)
+
+(define_expand "addsi3_cin_vout_imm"
+ [(parallel
+ [(set (match_dup 3)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI (match_dup 4)
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (match_dup 2))
+ (sign_extend:DI (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (plus:SI (match_dup 5) (match_dup 1))
+ (match_operand 2 "arm_adcimm_operand")))])]
+ "TARGET_32BIT"
+ {
+ operands[3] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[4] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[5] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
+)
+
+(define_insn "*addsi3_cin_vout_imm_insn"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (plus:DI
+ (match_operand:DI 3 "arm_carry_operation" "")
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r,r")))
+ (match_operand 2 "arm_adcimm_operand" "I,K"))
+ (sign_extend:DI
+ (plus:SI (plus:SI (match_operand:SI 4 "arm_carry_operation" "")
+ (match_dup 1))
+ (match_dup 2)))))
+ (set (match_operand:SI 0 "s_register_operand" "=r,r")
+ (plus:SI (plus:SI (match_dup 4) (match_dup 1))
+ (match_dup 2)))]
+ "TARGET_32BIT"
+ "@
+ adcs%?\\t%0, %1, %2
+ sbcs%?\\t%0, %1, #%B2"
+ [(set_attr "type" "alus_imm")]
+)
+
+(define_expand "addsi3_cin_vout_0"
+ [(parallel
+ [(set (match_dup 2)
+ (compare:CC_V
+ (plus:DI (match_dup 3)
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand")))
+ (sign_extend:DI (plus:SI (match_dup 4) (match_dup 1)))))
+ (set (match_operand:SI 0 "s_register_operand")
+ (plus:SI (match_dup 4) (match_dup 1)))])]
+ "TARGET_32BIT"
+ {
+ operands[2] = gen_rtx_REG (CC_Vmode, CC_REGNUM);
+ rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM);
+ operands[3] = gen_rtx_LTU (DImode, ccin, const0_rtx);
+ operands[4] = gen_rtx_LTU (SImode, ccin, const0_rtx);
+ }
+)
+
+(define_insn "*addsi3_cin_vout_0_insn"
+ [(set (reg:CC_V CC_REGNUM)
+ (compare:CC_V
+ (plus:DI
+ (match_operand:DI 2 "arm_carry_operation" "")
+ (sign_extend:DI (match_operand:SI 1 "s_register_operand" "r")))
+ (sign_extend:DI (plus:SI
+ (match_operand:SI 3 "arm_carry_operation" "")
+ (match_dup 1)))))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (plus:SI (match_dup 3) (match_dup 1)))]
+ "TARGET_32BIT"
+ "adcs%?\\t%0, %1, #0"
+ [(set_attr "type" "alus_imm")]
+)
+