Fix misoptimization of mask and shift.

PR target/21684
* config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0.

Co-Authored-By: Kevin Winchester <winchester@amirix.com>
From-SVN: r103228

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6fa630143dbf7ea13afe57f4ccfe8f36b88a886b..06898fded4461fa6a526ec12ed215ce723528164 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2005-08-17  James E Wilson  <wilson@specifix.com>
+           Kevin Winchester  <winchester@amirix.com>
+
+       PR target/21684
+       * config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0.
+
 2005-08-17  Uros Bizjak  <uros@kss-loka.si>
 
        PR target/23268

diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index f0afa88191b97f3573ad0014275d562c2a556029..d9960dc0edb95d7a9f1048824194dfd4de13a045 100644 (file)
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -820,12 +820,10 @@ extern const enum reg_class reg_class_from_letter[];
 /* Nonzero if access to memory by bytes is slow and undesirable.  */
 #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES
 
-/* Immediate shift counts are truncated by the output routines (or was it
-   the assembler?).  Shift counts in a register are truncated by ARM.  Note
-   that the native compiler puts too large (> 32) immediate shift counts
-   into a register and shifts by the register, letting the ARM decide what
-   to do instead of doing that itself.  */
-#define SHIFT_COUNT_TRUNCATED 1
+/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected
+   5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this
+   target.  */
+#define SHIFT_COUNT_TRUNCATED 0
 
 /* All integers have the same format so truncation is easy.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC)  1