RISC-V Adjust long unconditional branch sequence

Andrew and I independently noted the long unconditional branch sequence was
using the "call" pseudo op.  Technically it works, but it's a bit odd.  This
patch flips it to use the "jump" pseudo-op.

This was tested with a hacked-up local compiler which forced all branches/jumps
to be long jumps.  Naturally it triggered some failures for scan-asm tests but
no execution regressions (which is mostly what I was testing for).

I've updated the long branch support item in the RISE wiki to indicate that we
eventually want a register scavenging approach with a fallback to $ra in the
future so that we don't muck up the return address predictors.  It's not
super-high priority and shouldn't be terrible to implement given we've got the
$ra fallback when a suitable register can not be found.

gcc/
	* config/riscv/riscv.md (jump): Adjust sequence to use a "jump"
	pseudo op instead of a "call" pseudo op.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c26541bd5cea3977a9f97ac233c25ce85d7566be..23d91331290b0e08071d13244e3557ab302d6be0 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2924,7 +2924,7 @@
   /* Hopefully this does not happen often as this is going
      to clobber $ra and muck up the return stack predictors.  */
   if (get_attr_length (insn) == 8)
-    return "call\t%l0";
+    return "jump\t%l0,ra";
 
   return "j\t%l0";
 }