]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[Arm] Add support for missing CPUs
authorDennis Zhang <dennis.zhang@arm.com>
Fri, 23 Aug 2019 08:25:44 +0000 (08:25 +0000)
committerKyrylo Tkachov <ktkachov@gcc.gnu.org>
Fri, 23 Aug 2019 08:25:44 +0000 (08:25 +0000)
This patch adds '-mcpu' options for following CPUs:
Cortex-M35P, Cortex-A77, Cortex-A76AE.

Related specifications are as following:
https://developer.arm.com/ip-products/processors/cortex-m
https://developer.arm.com/ip-products/processors/cortex-a

2019-08-23  Dennis Zhang  <dennis.zhang@arm.com>

* config/arm/arm-cpus.in (cortex-m35p): New entry.
(cortex-a76ae): Likewise.
(cortex-a77): Likewise
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* doc/invoke.texi (ARM Options): Document cortex-m35p, cortx-a76ae,
cortex-a77 CPU options.

From-SVN: r274845

gcc/ChangeLog
gcc/config/arm/arm-cpus.in
gcc/config/arm/arm-tables.opt
gcc/config/arm/arm-tune.md
gcc/doc/invoke.texi

index 8e7ab45e7615dab83db990348bf91a85bdd67ac6..bd47b7736f1d1dc2e4995887ce673ed84e05734f 100644 (file)
@@ -1,3 +1,13 @@
+2019-08-23  Dennis Zhang  <dennis.zhang@arm.com>
+
+       * config/arm/arm-cpus.in (cortex-m35p): New entry.
+       (cortex-a76ae): Likewise.
+       (cortex-a77): Likewise
+       * config/arm/arm-tables.opt: Regenerate.
+       * config/arm/arm-tune.md: Likewise.
+       * doc/invoke.texi (ARM Options): Document cortex-m35p, cortx-a76ae,
+       cortex-a77 CPU options.
+
 2019-08-23  Martin Liska  <mliska@suse.cz>
 
        * profile.c (instrument_values): Do not set
index 3a55f6ac6d2b104400554a7b05cf8d7791341461..f8a3b3db67a537163bfe787d78c8f2edc4253ab3 100644 (file)
@@ -1331,6 +1331,28 @@ begin cpu cortex-a76
  part d0b
 end cpu cortex-a76
 
+begin cpu cortex-a76ae
+ cname cortexa76ae
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod+simd
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+ vendor 41
+ part d0e
+end cpu cortex-a76ae
+
+begin cpu cortex-a77
+ cname cortexa77
+ tune for cortex-a57
+ tune flags LDSCHED
+ architecture armv8.2-a+fp16+dotprod+simd
+ option crypto add FP_ARMv8 CRYPTO
+ costs cortex_a57
+ vendor 41
+ part d0d
+end cpu cortex-a77
+
 begin cpu neoverse-n1
  cname neoversen1
  alias !ares
@@ -1379,6 +1401,15 @@ begin cpu cortex-m33
  costs v7m
 end cpu cortex-m33
 
+begin cpu cortex-m35p
+ cname cortexm35p
+ tune flags LDSCHED
+ architecture armv8-m.main+dsp+fp
+ option nofp remove ALL_FP
+ option nodsp remove armv7em
+ costs v7m
+end cpu cortex-m35p
+
 # V8 R-profile implementations.
 begin cpu cortex-r52
  cname cortexr52
index bba54aea3d604be11f71cc0e2f81e3ee11e7a8e3..aeb5b3fbf629e5cfae4d5f6d4d5f1a9c7752a511 100644 (file)
@@ -234,6 +234,12 @@ Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75)
 EnumValue
 Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76)
 
+EnumValue
+Enum(processor_type) String(cortex-a76ae) Value( TARGET_CPU_cortexa76ae)
+
+EnumValue
+Enum(processor_type) String(cortex-a77) Value( TARGET_CPU_cortexa77)
+
 EnumValue
 Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
 
@@ -249,6 +255,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
 EnumValue
 Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
 
+EnumValue
+Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p)
+
 EnumValue
 Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
 
index b9dfb66ec84219d862396c37dd6a587d4a955efe..6fa5bb27750600847f3654b24aaa60d15a3722b8 100644 (file)
@@ -44,7 +44,8 @@
        cortexa73,exynosm1,xgene1,
        cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
        cortexa73cortexa53,cortexa55,cortexa75,
-       cortexa76,neoversen1,cortexa75cortexa55,
-       cortexa76cortexa55,cortexm23,cortexm33,
+       cortexa76,cortexa76ae,cortexa77,
+       neoversen1,cortexa75cortexa55,cortexa76cortexa55,
+       cortexm23,cortexm33,cortexm35p,
        cortexr52"
        (const (symbol_ref "((enum attr_tune) arm_tune)")))
index 08e6b5223e5b7ba83743f16125ff44d26ddf90d9..7a356840d78cd6a092b926f6b6f4a387168024ea 100644 (file)
@@ -17650,10 +17650,12 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
 @samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
 @samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
 @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
-@samp{cortex-a76}, @samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
+@samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77},
+@samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
 @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
 @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
 @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
+@samp{cortex-m35p},
 @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
 @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
 @samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
@@ -17717,14 +17719,14 @@ The following extension options are common to the listed CPUs:
 
 @table @samp
 @item +nodsp
-Disable the DSP instructions on @samp{cortex-m33}.
+Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}.
 
 @item  +nofp
 Disables the floating-point instructions on @samp{arm9e},
 @samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
 @samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
 @samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
-@samp{cortex-m4}, @samp{cortex-m7} and @samp{cortex-m33}.
+@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}.
 Disables the floating-point and SIMD instructions on
 @samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
 @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},