[committed] Provide suitable output template for zero_extendqihi2 on H8

Segher's recent combine change, quite unexpectedly, triggered a regression on
the H8 port.  It failed to build newlib.

The zero_extendqihi2 pattern provided two alternatives.  One where the source
and destination matched.  That turns into a suitable instruction trivially.
The second alternative was actually meant to capture cases where the value is
coming from memory.

What was missing here was the reg->reg case where the source and destination do
not match.  That fell into the second case which was requested to be split by
the pattern's output template.

The splitter had a suitable condition to make sure it only triggered in the
right cases.  Unfortunately with the pattern requiring a split in a case where
the splitter was going to fail led to the fault.

So regardless of what's going on in the combiner, this code was just wrong.
Fixed thusly by providing a suitable output template for the reg->reg case.

Regression tested on h8300-elf.  Pushing to the trunk.

gcc/

	* config/h8300/extensions.md (zero_extendqihi*): Add output
	template for reg->reg case where the regs don't match.

diff --git a/gcc/config/h8300/extensions.md b/gcc/config/h8300/extensions.md
index 7149dc0ac52ef0157ce516bfa0f1b340d8ade883..a1e8c4abd37e369b3d3baf6ed1018cf36ba9d308 100644 (file)
--- a/gcc/config/h8300/extensions.md
+++ b/gcc/config/h8300/extensions.md
@@ -12,8 +12,8 @@
   })
 
 (define_insn_and_split "*zero_extendqihi2"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-       (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))]
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+       (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,r,g>")))]
   ""
   "#"
   "&& reload_completed"
@@ -21,14 +21,15 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn "*zero_extendqihi2<cczn>"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-       (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,g>")))
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+       (zero_extend:HI (match_operand:QI 1 "general_operand_src" "0,r,g>")))
    (clobber (reg:CC CC_REG))]
   ""
   "@
   extu.w       %T0
+  mov.b\t%X1,%R0\;extu.w\t%T0
   #"
-  [(set_attr "length" "2,10")])
+  [(set_attr "length" "2,4,10")])
 
 ;; Split the zero extension of a general operand (actually a memory
 ;; operand) into a load of the operand and the actual zero extension