Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 47b872b682d292c94e1bf091312d2109a0f1926b..4bbcc038b3aa6ef49268c392ccbb58b5a1fa7ab4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,279 @@
+2023-07-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/110717
+       * config/i386/i386-features.cc
+       (general_scalar_chain::compute_convert_gain): Calculate gain
+       for extend higpart case.
+       (general_scalar_chain::convert_op): Handle
+       ASHIFTRT/ASHIFT combined RTX.
+       (general_scalar_to_vector_candidate_p): Enable ASHIFTRT for
+       SImode for SSE2 targets.  Handle ASHIFTRT/ASHIFT combined RTX.
+       * config/i386/i386.md (*extend<dwi>2_doubleword_highpart):
+       New define_insn_and_split pattern.
+       (*extendv2di2_highpart_stv): Ditto.
+
+2023-07-20  Vladimir N. Makarov  <vmakarov@redhat.com>
+
+       * lra-constraints.cc (simplify_operand_subreg): Check frame pointer
+       simplification.
+
+2023-07-20  Andrew Pinski  <apinski@marvell.com>
+
+       * combine.cc (dump_combine_stats): Remove.
+       (dump_combine_total_stats): Remove.
+       (total_attempts, total_merges, total_extras,
+       total_successes): Remove.
+       (combine_instructions): Don't increment total stats
+       instead use statistics_counter_event.
+       * dumpfile.cc (print_combine_total_stats): Remove.
+       * dumpfile.h (print_combine_total_stats): Remove.
+       (dump_combine_total_stats): Remove.
+       * passes.cc (finish_optimization_passes):
+       Don't call print_combine_total_stats.
+       * rtl.h (dump_combine_total_stats): Remove.
+       (dump_combine_stats): Remove.
+
+2023-07-20  Jan Hubicka  <jh@suse.cz>
+
+       * tree-ssa-loop-ch.cc (should_duplicate_loop_header_p): Use BIT instead of TRUTH
+       logical ops.
+
+2023-07-20  Martin Jambor  <mjambor@suse.cz>
+
+       * doc/invoke.texi (analyzer-text-art-string-ellipsis-threshold): New.
+       (analyzer-text-art-ideal-canvas-width): Likewise.
+       (analyzer-text-art-string-ellipsis-head-len): Likewise.
+       (analyzer-text-art-string-ellipsis-tail-len): Likewise.
+
+2023-07-20  Ju-Zhe Zhong  <juzhe.zhong@rivai.ai>
+
+       * tree-vect-stmts.cc (check_load_store_for_partial_vectors):
+       Refine code structure.
+
+2023-07-20  Jan Hubicka  <jh@suse.cz>
+
+       * tree-ssa-loop-ch.cc (edge_range_query): Rename to ...
+       (get_range_query): ... this one; do
+       (static_loop_exit): Add query parametr, turn ranger to reference.
+       (loop_static_stmt_p): New function.
+       (loop_static_op_p): New function.
+       (loop_iv_derived_p): Remove.
+       (loop_combined_static_and_iv_p): New function.
+       (should_duplicate_loop_header_p): Discover combined onditionals;
+       do not track iv derived; improve dumps.
+       (pass_ch::execute): Fix whitespace.
+
+2023-07-20  Richard Biener  <rguenther@suse.de>
+
+       PR tree-optimization/110204
+       * tree-ssa-sccvn.cc (eliminate_dom_walker::eliminate_avail):
+       Look through copies generated by PRE.
+
+2023-07-20  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * tree-vect-stmts.cc (get_group_load_store_type): Account for
+       `gap` when checking if need to peel twice.
+
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       PR middle-end/77928
+       * doc/extend.texi: Document iseqsig builtin.
+       * builtins.cc (fold_builtin_iseqsig): New function.
+       (fold_builtin_2): Handle BUILT_IN_ISEQSIG.
+       (is_inexpensive_builtin): Handle BUILT_IN_ISEQSIG.
+       * builtins.def (BUILT_IN_ISEQSIG): New built-in.
+
+2023-07-20  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/vector.md: Fix incorrect match_operand.
+
+2023-07-20  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/i386/i386-expand.cc (ix86_expand_move): Don't call
+       force_reg, to use SUBREG rather than create a new pseudo when
+       inserting DFmode fields into TImode with insvti_{high,low}part.
+       * config/i386/i386.md (*concat<mode><dwi>3_3): Split into two
+       define_insn_and_split...
+       (*concatditi3_3): 64-bit implementation.  Provide alternative
+       that allows register allocation to use SSE registers that is
+       split into vec_concatv2di after reload.
+       (*concatsidi3_3): 32-bit implementation.
+
+2023-07-20  Richard Biener  <rguenther@suse.de>
+
+       PR middle-end/61747
+       * internal-fn.cc (expand_vec_cond_optab_fn): When the
+       value operands are equal to the original comparison operands
+       preserve that equality by re-using the comparison expansion.
+       * optabs.cc (emit_conditional_move): When the value operands
+       are equal to the comparison operands and would be forced to
+       a register by prepare_cmp_insn do so earlier, preserving the
+       equality.
+
+2023-07-20  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/vector.md: Align pattern format.
+
+2023-07-20  Haochen Jiang  <haochen.jiang@intel.com>
+
+       * doc/invoke.texi: Remove AVX512VP2INTERSECT in
+       Granite Rapids{, D} from documentation.
+
+2023-07-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+       * config/riscv/autovec.md
+       (len_mask_gather_load<VNX16_QHSD:mode><VNX16_QHSDI:mode>):
+       Refactor RVV machine modes.
+       (len_mask_gather_load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
+       (len_mask_gather_load<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
+       (len_mask_gather_load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
+       (len_mask_gather_load<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
+       (len_mask_gather_load<mode><mode>): Ditto.
+       (len_mask_gather_load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
+       (len_mask_scatter_store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
+       (len_mask_scatter_store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
+       (len_mask_scatter_store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
+       (len_mask_scatter_store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
+       (len_mask_scatter_store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
+       (len_mask_scatter_store<mode><mode>): Ditto.
+       (len_mask_scatter_store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
+       * config/riscv/riscv-modes.def (VECTOR_BOOL_MODE): Ditto.
+       (ADJUST_NUNITS): Ditto.
+       (ADJUST_ALIGNMENT): Ditto.
+       (ADJUST_BYTESIZE): Ditto.
+       (ADJUST_PRECISION): Ditto.
+       (RVV_MODES): Ditto.
+       (RVV_WHOLE_MODES): Ditto.
+       (RVV_FRACT_MODE): Ditto.
+       (RVV_NF8_MODES): Ditto.
+       (RVV_NF4_MODES): Ditto.
+       (VECTOR_MODES_WITH_PREFIX): Ditto.
+       (VECTOR_MODE_WITH_PREFIX): Ditto.
+       (RVV_TUPLE_MODES): Ditto.
+       (RVV_NF2_MODES): Ditto.
+       (RVV_TUPLE_PARTIAL_MODES): Ditto.
+       * config/riscv/riscv-v.cc (struct mode_vtype_group): Ditto.
+       (ENTRY): Ditto.
+       (TUPLE_ENTRY): Ditto.
+       (get_vlmul): Ditto.
+       (get_nf): Ditto.
+       (get_ratio): Ditto.
+       (preferred_simd_mode): Ditto.
+       (autovectorize_vector_modes): Ditto.
+       * config/riscv/riscv-vector-builtins.cc (DEF_RVV_TYPE): Ditto.
+       * config/riscv/riscv-vector-builtins.def (DEF_RVV_TYPE): Ditto.
+       (vbool64_t): Ditto.
+       (vbool32_t): Ditto.
+       (vbool16_t): Ditto.
+       (vbool8_t): Ditto.
+       (vbool4_t): Ditto.
+       (vbool2_t): Ditto.
+       (vbool1_t): Ditto.
+       (vint8mf8_t): Ditto.
+       (vuint8mf8_t): Ditto.
+       (vint8mf4_t): Ditto.
+       (vuint8mf4_t): Ditto.
+       (vint8mf2_t): Ditto.
+       (vuint8mf2_t): Ditto.
+       (vint8m1_t): Ditto.
+       (vuint8m1_t): Ditto.
+       (vint8m2_t): Ditto.
+       (vuint8m2_t): Ditto.
+       (vint8m4_t): Ditto.
+       (vuint8m4_t): Ditto.
+       (vint8m8_t): Ditto.
+       (vuint8m8_t): Ditto.
+       (vint16mf4_t): Ditto.
+       (vuint16mf4_t): Ditto.
+       (vint16mf2_t): Ditto.
+       (vuint16mf2_t): Ditto.
+       (vint16m1_t): Ditto.
+       (vuint16m1_t): Ditto.
+       (vint16m2_t): Ditto.
+       (vuint16m2_t): Ditto.
+       (vint16m4_t): Ditto.
+       (vuint16m4_t): Ditto.
+       (vint16m8_t): Ditto.
+       (vuint16m8_t): Ditto.
+       (vint32mf2_t): Ditto.
+       (vuint32mf2_t): Ditto.
+       (vint32m1_t): Ditto.
+       (vuint32m1_t): Ditto.
+       (vint32m2_t): Ditto.
+       (vuint32m2_t): Ditto.
+       (vint32m4_t): Ditto.
+       (vuint32m4_t): Ditto.
+       (vint32m8_t): Ditto.
+       (vuint32m8_t): Ditto.
+       (vint64m1_t): Ditto.
+       (vuint64m1_t): Ditto.
+       (vint64m2_t): Ditto.
+       (vuint64m2_t): Ditto.
+       (vint64m4_t): Ditto.
+       (vuint64m4_t): Ditto.
+       (vint64m8_t): Ditto.
+       (vuint64m8_t): Ditto.
+       (vfloat16mf4_t): Ditto.
+       (vfloat16mf2_t): Ditto.
+       (vfloat16m1_t): Ditto.
+       (vfloat16m2_t): Ditto.
+       (vfloat16m4_t): Ditto.
+       (vfloat16m8_t): Ditto.
+       (vfloat32mf2_t): Ditto.
+       (vfloat32m1_t): Ditto.
+       (vfloat32m2_t): Ditto.
+       (vfloat32m4_t): Ditto.
+       (vfloat32m8_t): Ditto.
+       (vfloat64m1_t): Ditto.
+       (vfloat64m2_t): Ditto.
+       (vfloat64m4_t): Ditto.
+       (vfloat64m8_t): Ditto.
+       * config/riscv/riscv-vector-switch.def (ENTRY): Ditto.
+       (TUPLE_ENTRY): Ditto.
+       * config/riscv/riscv-vsetvl.cc (change_insn): Ditto.
+       * config/riscv/riscv.cc (riscv_valid_lo_sum_p): Ditto.
+       (riscv_v_adjust_nunits): Ditto.
+       (riscv_v_adjust_bytesize): Ditto.
+       (riscv_v_adjust_precision): Ditto.
+       (riscv_convert_vector_bits): Ditto.
+       * config/riscv/riscv.h (riscv_v_adjust_nunits): Ditto.
+       * config/riscv/riscv.md: Ditto.
+       * config/riscv/vector-iterators.md: Ditto.
+       * config/riscv/vector.md
+       (@pred_indexed_<order>store<VNX16_QHSD:mode><VNX16_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
+       (@pred_indexed_<order>store<VNX32_QHS:mode><VNX32_QHSI:mode>): Ditto.
+       (@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
+       (@pred_indexed_<order>store<VNX64_QH:mode><VNX64_QHI:mode>): Ditto.
+       (@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
+       (@pred_indexed_<order>store<VNX128_Q:mode><VNX128_Q:mode>): Ditto.
+       (@pred_indexed_<order>load<V1T:mode><V1I:mode>): Ditto.
+       (@pred_indexed_<order>load<V1T:mode><VNX1_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>load<V2T:mode><V2I:mode>): Ditto.
+       (@pred_indexed_<order>load<V2T:mode><VNX2_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>load<V4T:mode><V4I:mode>): Ditto.
+       (@pred_indexed_<order>load<V4T:mode><VNX4_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>load<V8T:mode><V8I:mode>): Ditto.
+       (@pred_indexed_<order>load<V8T:mode><VNX8_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>load<V16T:mode><V16I:mode>): Ditto.
+       (@pred_indexed_<order>load<V16T:mode><VNX16_QHSI:mode>): Ditto.
+       (@pred_indexed_<order>load<V32T:mode><V32I:mode>): Ditto.
+       (@pred_indexed_<order>load<V32T:mode><VNX32_QHI:mode>): Ditto.
+       (@pred_indexed_<order>load<V64T:mode><V64I:mode>): Ditto.
+       (@pred_indexed_<order>store<V1T:mode><V1I:mode>): Ditto.
+       (@pred_indexed_<order>store<V1T:mode><VNX1_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>store<V2T:mode><V2I:mode>): Ditto.
+       (@pred_indexed_<order>store<V2T:mode><VNX2_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>store<V4T:mode><V4I:mode>): Ditto.
+       (@pred_indexed_<order>store<V4T:mode><VNX4_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>store<V8T:mode><V8I:mode>): Ditto.
+       (@pred_indexed_<order>store<V8T:mode><VNX8_QHSDI:mode>): Ditto.
+       (@pred_indexed_<order>store<V16T:mode><V16I:mode>): Ditto.
+       (@pred_indexed_<order>store<V16T:mode><VNX16_QHSI:mode>): Ditto.
+       (@pred_indexed_<order>store<V32T:mode><V32I:mode>): Ditto.
+       (@pred_indexed_<order>store<V32T:mode><VNX32_QHI:mode>): Ditto.
+       (@pred_indexed_<order>store<V64T:mode><V64I:mode>): Ditto.
+
 2023-07-19  Vladimir N. Makarov  <vmakarov@redhat.com>
 
        * lra-int.h (lra_update_fp2sp_elimination): New prototype.

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 4b8414aa23fdee0c09fdaebae679b32090139f67..0e7d73c191435c05e211b9a04ed50d70b0a7ae22 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230720
+20230721

diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 253327442de87b034d3860f49ec22a854e88428d..119adee9cdd42816bffacd0e70c9b2e62f3a45e6 100644 (file)
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,9 @@
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       PR middle-end/77928
+       * c-common.cc (check_builtin_function_arguments):
+       Handle BUILT_IN_ISEQSIG.
+
 2023-07-05  Robin Dapp  <rdapp@ventanamicro.com>
            Juzhe-Zhong  <juzhe.zhong@rivai.ai>
 

diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog
index 59491e545d961950ef36059bb31a1f2538fd939c..db9ce602f1a7596b89fc55d7570d968d60e0e3bd 100644 (file)
--- a/gcc/cp/ChangeLog
+++ b/gcc/cp/ChangeLog
@@ -1,3 +1,9 @@
+2023-07-20  Marek Polacek  <polacek@redhat.com>
+
+       PR c++/110114
+       * call.cc (implicit_conversion_1): Return early if the type isn't
+       complete.
+
 2023-07-19  Marek Polacek  <polacek@redhat.com>
 
        PR c++/110745

diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog
index 3663a74b9814570a74651e906f2695c79faa057b..fba7799afb3a60224f13c535a6cff1534332ddd0 100644 (file)
--- a/gcc/fortran/ChangeLog
+++ b/gcc/fortran/ChangeLog
@@ -1,3 +1,15 @@
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * trans-intrinsic.cc (conv_intrinsic_ieee_comparison): Only
+       define it once.
+
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * f95-lang.cc (gfc_init_builtin_functions): Add __builtin_iseqsig.
+       * trans-intrinsic.cc (conv_intrinsic_ieee_comparison): New
+       function.
+       (gfc_conv_ieee_arithmetic_function): Handle IEEE comparisons.
+
 2023-07-19  Tobias Burnus  <tobias@codesourcery.com>
 
        PR fortran/107424

diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog
index 718c6f5f901eb4428aa20e8216ded865bf2c164d..5197a0062e20b1212ae79f4a5431d4e44cb959be 100644 (file)
--- a/gcc/m2/ChangeLog
+++ b/gcc/m2/ChangeLog
@@ -1,3 +1,24 @@
+2023-07-20  Gaius Mulley  <gaiusmod2@gmail.com>
+
+       * gm2-compiler/M2SymInit.mod (IsExempt): Remove parameter exemption.
+       (CheckIndrX): Call SetupLAlias between lhs and content.
+       (trashParam): Re-write.
+       (SetVarLRInitialized): Indicate shadow and heap are initialized.
+       Call SetupIndr between shadow and heap.
+       * gm2-compiler/P2SymBuild.mod: Import
+       PutProcedureParameterHeapVars.
+       (EndBuildProcedure): Call PutProcedureParameterHeapVars.
+       * gm2-compiler/SymbolTable.def (GetParameterHeapVar): New
+       procedure function.
+       (PutProcedureParameterHeapVars): New procedure function.
+       * gm2-compiler/SymbolTable.mod (MakeParameterHeapVar): New
+       procedure function.
+       (GetParameterHeapVar): New procedure function.
+       (PuttParameterHeapVar): New procedure function.
+       (PutProcedureParameterHeapVars): New procedure.
+       (VarParam): HeapVar new record field.
+       (PutVarParam): HeapVar assigned to NulSym.
+
 2023-07-19  Gaius Mulley  <gaiusmod2@gmail.com>
 
        PR modula2/110284

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4345065bb9fa6ff2face1bd2d4122af309e3b367..c52e8ae4c2284a9524ea9c52802900207653546a 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,86 @@
+2023-07-20  Gaius Mulley  <gaiusmod2@gmail.com>
+
+       * gm2/switches/uninit-variable-checking/procedures/fail/testdispose3.mod: New test.
+       * gm2/switches/uninit-variable-checking/procedures/fail/testdispose4.mod: New test.
+       * gm2/switches/uninit-variable-checking/procedures/pass/testdispose3.mod: New test.
+       * gm2/switches/uninit-variable-checking/procedures/pass/testdispose4.mod: New test.
+
+2023-07-20  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/110717
+       * gcc.target/i386/pr110717.c: New test.
+
+2023-07-20  Marek Polacek  <polacek@redhat.com>
+
+       * g++.dg/tree-ssa/allocator-opt1.C: Force _GLIBCXX_USE_CXX11_ABI to 1.
+
+2023-07-20  Marek Polacek  <polacek@redhat.com>
+
+       PR c++/110114
+       * g++.dg/cpp0x/initlist100.C: Adjust expected diagnostic.
+       * g++.dg/cpp2a/desig28.C: New test.
+       * g++.dg/cpp2a/desig29.C: New test.
+
+2023-07-20  Jan Hubicka  <jh@suse.cz>
+
+       * g++.dg/uninit-pred-loop-1_c.C: Allow warning.
+       * gcc.dg/tree-ssa/copy-headers-7.c: Add tests so exit conditition is
+       static; update template.
+       * gcc.dg/tree-ssa/ivopt_mult_1.c: Add test so exit condition is static.
+       * gcc.dg/tree-ssa/ivopt_mult_2.c: Add test so exit condition is static.
+       * gcc.dg/tree-ssa/copy-headers-8.c: New test.
+
+2023-07-20  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * gcc.dg/vect/vect-multi-peel-gaps.c: New test.
+
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * gfortran.dg/ieee/comparisons_1.f90: New test.
+       * gfortran.dg/ieee/comparisons_2.f90: New test.
+       * gfortran.dg/ieee/comparisons_3.F90: New test.
+
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       PR middle-end/77928
+       * gcc.dg/torture/builtin-iseqsig-1.c: New test.
+       * gcc.dg/torture/builtin-iseqsig-2.c: New test.
+       * gcc.dg/torture/builtin-iseqsig-3.c: New test.
+
+2023-07-20  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/base/pr110299-1.c: Adjust tests.
+       * gcc.target/riscv/rvv/base/pr110299-2.c: Ditto.
+
+2023-07-20  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * gcc.target/i386/pr88873.c: New test case.
+
+2023-07-20  Richard Biener  <rguenther@suse.de>
+
+       PR middle-end/61747
+       * g++.target/i386/pr61747.C: New testcase.
+
+2023-07-20  Lewis Hyatt  <lhyatt@gmail.com>
+
+       PR preprocessor/103902
+       * g++.dg/cpp0x/udlit-extended-id-1.C: Change "unsigned long" to
+       "size_t" throughout.
+       * g++.dg/cpp0x/udlit-extended-id-3.C: Likewise.
+
+2023-07-20  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+       * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-7.c:
+       Adapt test.
+       * gcc.target/riscv/rvv/autovec/gather-scatter/gather_load_run-8.c:
+       Ditto.
+       * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store-9.c:
+       Ditto.
+       * gcc.target/riscv/rvv/autovec/gather-scatter/mask_scatter_store_run-8.c
+       : Ditto.
+       * gcc.target/riscv/rvv/autovec/gather-scatter/scatter_store_run-8.c:
+       Ditto.
+
 2023-07-19  Marek Polacek  <polacek@redhat.com>
 
        PR c++/110745

diff --git a/libgfortran/ChangeLog b/libgfortran/ChangeLog
index 9edd4d78d9dbe02d5a51b904a252d3726acda3b8..3ee73b9b42a325381493553231e0d2134986e473 100644 (file)
--- a/libgfortran/ChangeLog
+++ b/libgfortran/ChangeLog
@@ -1,3 +1,8 @@
+2023-07-20  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * ieee/ieee_arithmetic.F90: Add IEEE_QUIET_* and
+       IEEE_SIGNALING_* functions.
+
 2023-06-11  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
 
        PR libfortran/109373

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 4f4fedb4581ca9ed29cd031957e31ac1fd898240..5a45496cdedc7e5ae511ca1523d067dd1bfa1af3 100644 (file)
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,9 @@
+2023-07-20  Tobias Burnus  <tobias@codesourcery.com>
+
+       * libgomp.texi (OpenMP Runtime Library Routines):
+       Split long list by adding sections and moving routines there.
+       (OMP_ALLOCATORS): Fix typo.
+
 2023-07-19  Tobias Burnus  <tobias@codesourcery.com>
 
        PR fortran/107424