projects / thirdparty / glibc.git / blame
| Commit | Line | Data |
|---|---|---|
| d115c0d8 | 1 | /* FPU control word bits. AM33/2.0 version. |
| d4697bc9 | 2 | Copyright (C) 1996-2014 Free Software Foundation, Inc. |
| d115c0d8 AO |
3 | This file is part of the GNU C Library. |
| 4 | Contributed by Alexandre Oliva <aoliva@redhat.com> | |
| 5 | based on the corresponding file in the mips port. | |
| 6 | ||
| 7 | The GNU C Library is free software; you can redistribute it and/or | |
| 8 | modify it under the terms of the GNU Lesser General Public | |
| 9 | License as published by the Free Software Foundation; either | |
| 10 | version 2.1 of the License, or (at your option) any later version. | |
| 11 | ||
| 12 | The GNU C Library is distributed in the hope that it will be useful, | |
| 13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 | Lesser General Public License for more details. | |
| 16 | ||
| 17 | You should have received a copy of the GNU Lesser General Public | |
| ab84e3ff PE |
18 | License along with the GNU C Library. If not, see |
| 19 | <http://www.gnu.org/licenses/>. */ | |
| d115c0d8 AO |
20 | |
| 21 | #ifndef _FPU_CONTROL_H | |
| 22 | #define _FPU_CONTROL_H | |
| 23 | ||
| 24 | /* AM33/2.0 FPU floating point control register bits. | |
| 25 | * | |
| 26 | * 31-22 -> reserved | |
| 27 | * 21-18 -> floating-point condition codes (L, G, E, U) | |
| 28 | * 17-16 -> rounding modes (00 is to-nearest; other values are reserved | |
| 29 | * 15 -> reserved (read as 0, write with 0) | |
| 30 | * 14-10 -> Exception Cause (inValid, divZero, Overflow, Underflow, Inexact) | |
| 31 | * 9- 5 -> Exception Enable | |
| 32 | * 4- 0 -> Exception Flag, cleared when exception cause is set | |
| 33 | */ | |
| 34 | ||
| 35 | #include <features.h> | |
| 36 | #include <fenv.h> | |
| 37 | ||
| 38 | /* masking of interrupts */ | |
| 39 | #define _FPU_MASK_V 0x0200 /* Invalid operation */ | |
| 40 | #define _FPU_MASK_Z 0x0100 /* Division by zero */ | |
| 41 | #define _FPU_MASK_O 0x0080 /* Overflow */ | |
| 42 | #define _FPU_MASK_U 0x0040 /* Underflow */ | |
| 43 | #define _FPU_MASK_I 0x0020 /* Inexact operation */ | |
| 44 | ||
| 45 | /* rounding control */ | |
| 46 | #define _FPU_RC_NEAREST 0x0 /* Only available mode */ | |
| 47 | ||
| 48 | #define _FPU_RESERVED 0xffc08000 /* Reserved bits in fpcr */ | |
| 49 | ||
| 50 | ||
| 51 | /* The fdlibm code requires strict IEEE double precision arithmetic, | |
| 52 | and no interrupts for exceptions, rounding to nearest. */ | |
| 53 | ||
| 54 | #define _FPU_DEFAULT 0x0000001f | |
| 55 | ||
| 56 | /* IEEE: same as above, but exceptions */ | |
| 57 | #define _FPU_IEEE 0x000003ff | |
| 58 | ||
| 59 | /* Type of the control word. */ | |
| 60 | typedef unsigned int fpu_control_t; | |
| 61 | ||
| 62 | /* Macros for accessing the hardware control word. _FPU_SETCW is | |
| 63 | defined such that it won't modify the EF bits, that are cleared | |
| 64 | when assigned bits that are set. Use SETFCW to get them actually | |
| 65 | reset. */ | |
| 66 | #define _FPU_SETFCW(cw) __asm__ ("fmov %0,fpcr" : : "ri" (cw)) | |
| 67 | #define _FPU_SETCW(cw) _FPU_SETFCW((cw) & ~FE_ALL_EXCEPT) | |
| 68 | #define _FPU_GETCW(cw) __asm__ ("fmov fpcr,%0" : "=r" (cw)) | |
| 69 | ||
| 70 | /* Default control word set at startup. */ | |
| 71 | extern fpu_control_t __fpu_control; | |
| 72 | ||
| 73 | #endif /* fpu_control.h */ |