[thirdparty/glibc.git] / ports / sysdeps / mips / sys / asm.h

/* Copyright (C) 1997-2013 Free Software Foundation, Inc.
   This file is part of the GNU C Library.
   Contributed by Ralf Baechle <ralf@gnu.org>.

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2.1 of the License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with the GNU C Library.  If not, see
   <http://www.gnu.org/licenses/>.  */

#ifndef _SYS_ASM_H
#define _SYS_ASM_H

#include <sgidefs.h>

#ifndef CAT
# define __CAT(str1,str2) str1##str2
# define CAT(str1,str2) __CAT(str1,str2)
#endif

/*
 * Macros to handle different pointer/register sizes for 32/64-bit code
 *
 * 64 bit address space isn't used yet, so we may use the R3000 32 bit
 * defines for now.
 */
#if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32
# define PTR .word
# define PTRSIZE 4
# define PTRLOG 2
#elif _MIPS_SIM == _ABI64
# define PTR .dword
# define PTRSIZE 8
# define PTRLOG 3
#endif

/*
 * PIC specific declarations
 */
#if _MIPS_SIM == _ABIO32
# ifdef __PIC__
#  define CPRESTORE(register) \
		.cprestore register
#  define CPLOAD(register) \
		.cpload register
# else
#  define CPRESTORE(register)
#  define CPLOAD(register)
# endif

# define CPADD(register) \
		.cpadd	register

/*
 * Set gp when at 1st instruction
 */
# define SETUP_GP					\
		.set noreorder;				\
		.cpload $25;				\
		.set reorder
/* Set gp when not at 1st instruction */
# define SETUP_GPX(r)					\
		.set noreorder;				\
		move r, $31;	 /* Save old ra.  */	\
		bal 10f; /* Find addr of cpload.  */	\
		nop;					\
10:							\
		.cpload $31;				\
		move $31, r;				\
		.set reorder
# define SETUP_GPX_L(r, l)				\
		.set noreorder;				\
		move r, $31;	 /* Save old ra.  */	\
		bal l;   /* Find addr of cpload.  */	\
		nop;					\
l:							\
		.cpload $31;				\
		move $31, r;				\
		.set reorder
# define SAVE_GP(x) \
		.cprestore x /* Save gp trigger t9/jalr conversion.	 */
# define SETUP_GP64(a, b)
# define SETUP_GPX64(a, b)
# define SETUP_GPX64_L(cp_reg, ra_save, l)
# define RESTORE_GP64
# define USE_ALT_CP(a)
#else /* _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32 */
/*
 * For callee-saved gp calling convention:
 */
# define SETUP_GP
# define SETUP_GPX(r)
# define SETUP_GPX_L(r, l)
# define SAVE_GP(x)

# define SETUP_GP64(gpoffset, proc) \
		.cpsetup $25, gpoffset, proc
# define SETUP_GPX64(cp_reg, ra_save)			\
		move ra_save, $31; /* Save old ra.  */	\
		.set noreorder;				\
		bal 10f; /* Find addr of .cpsetup.  */	\
		nop;					\
10:							\
		.set reorder;				\
		.cpsetup $31, cp_reg, 10b;		\
		move $31, ra_save
# define SETUP_GPX64_L(cp_reg, ra_save, l)  \
		move ra_save, $31; /* Save old ra.  */	\
		.set noreorder;				\
		bal l;   /* Find addr of .cpsetup.  */	\
		nop;					\
l:							\
		.set reorder;				\
		.cpsetup $31, cp_reg, l;		\
		move $31, ra_save
# define RESTORE_GP64 \
		.cpreturn
/* Use alternate register for context pointer.  */
# define USE_ALT_CP(reg)	\
		.cplocal reg
#endif /* _MIPS_SIM != _ABIO32 */

/*
 * Stack Frame Definitions
 */
#if _MIPS_SIM == _ABIO32
# define NARGSAVE 4 /* Space for 4 argument registers must be allocated.  */
#endif
#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32
# define NARGSAVE 0 /* No caller responsibilities.  */
#endif


/*
 * LEAF - declare leaf routine
 */
#define	LEAF(symbol)                                    \
		.globl	symbol;                         \
		.align	2;                              \
		.type	symbol,@function;               \
		.ent	symbol,0;                       \
symbol:		.frame	sp,0,ra

/*
 * NESTED - declare nested routine entry point
 */
#define	NESTED(symbol, framesize, rpc)                  \
		.globl	symbol;                         \
		.align	2;                              \
		.type	symbol,@function;               \
		.ent	symbol,0;                       \
symbol:		.frame	sp, framesize, rpc

/*
 * END - mark end of function
 */
#ifndef END
# define END(function)                                   \
		.end	function;		        \
		.size	function,.-function
#endif

/*
 * EXPORT - export definition of symbol
 */
#define	EXPORT(symbol)                                  \
		.globl	symbol;                         \
symbol:

/*
 * ABS - export absolute symbol
 */
#define	ABS(symbol,value)                               \
		.globl	symbol;                         \
symbol		=	value

#define	PANIC(msg)                                      \
		.set	push;				\
		.set	reorder;                        \
		la	a0,8f;                          \
		jal	panic;                          \
9:		b	9b;                             \
		.set	pop;				\
		TEXT(msg)

/*
 * Print formated string
 */
#define PRINT(string)                                   \
		.set	push;				\
		.set	reorder;                        \
		la	a0,8f;                          \
		jal	printk;                         \
		.set	pop;				\
		TEXT(string)

#define	TEXT(msg)                                       \
		.data;                                  \
8:		.asciiz	msg;                            \
		.previous;

/*
 * Build text tables
 */
#define TTABLE(string)                                  \
		.text;                                  \
		.word	1f;                             \
		.previous;                              \
		.data;                                  \
1:		.asciz	string;                         \
		.previous

/*
 * MIPS IV pref instruction.
 * Use with .set noreorder only!
 *
 * MIPS IV implementations are free to treat this as a nop.  The R5000
 * is one of them.  So we should have an option not to use this instruction.
 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
# define PREF(hint,addr)                                 \
		pref	hint,addr
# define PREFX(hint,addr)                                \
		prefx	hint,addr
#else
# define PREF(hint,addr)
# define PREFX(hint,addr)
#endif

/*
 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
 */
#if _MIPS_ISA == _MIPS_ISA_MIPS1
# define MOVN(rd,rs,rt)					\
		.set	push;				\
		.set	reorder;			\
		beqz	rt,9f;				\
		move	rd,rs;				\
		.set	pop;				\
9:
# define MOVZ(rd,rs,rt)					\
		.set	push;				\
		.set	reorder;			\
		bnez	rt,9f;				\
		move	rd,rt;				\
		.set	pop;				\
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
# define MOVN(rd,rs,rt)					\
		.set	push;				\
		.set	noreorder;			\
		bnezl	rt,9f;				\
		move	rd,rs;				\
		.set	pop;				\
9:
# define MOVZ(rd,rs,rt)					\
		.set	push;				\
		.set	noreorder;			\
		beqzl	rt,9f;				\
		movz	rd,rs;				\
		.set	pop;				\
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
# define MOVN(rd,rs,rt)					\
		movn	rd,rs,rt
# define MOVZ(rd,rs,rt)					\
		movz	rd,rs,rt
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */

/*
 * Stack alignment
 */
#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32
# define ALSZ	15
# define ALMASK	~15
#else
# define ALSZ	7
# define ALMASK	~7
#endif

/*
 * Size of a register
 */
#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32
# define SZREG	8
#else
# define SZREG	4
#endif

/*
 * Use the following macros in assemblercode to load/store registers,
 * pointers etc.
 */
#if (SZREG == 4)
# define REG_S sw
# define REG_L lw
#else
# define REG_S sd
# define REG_L ld
#endif

/*
 * How to add/sub/load/store/shift C int variables.
 */
#if (_MIPS_SZINT == 32)
# define INT_ADD	add
# define INT_ADDI	addi
# define INT_ADDU	addu
# define INT_ADDIU	addiu
# define INT_SUB	add
# define INT_SUBI	subi
# define INT_SUBU	subu
# define INT_SUBIU	subu
# define INT_L		lw
# define INT_S		sw
#endif

#if (_MIPS_SZINT == 64)
# define INT_ADD	dadd
# define INT_ADDI	daddi
# define INT_ADDU	daddu
# define INT_ADDIU	daddiu
# define INT_SUB	dadd
# define INT_SUBI	dsubi
# define INT_SUBU	dsubu
# define INT_SUBIU	dsubu
# define INT_L		ld
# define INT_S		sd
#endif

/*
 * How to add/sub/load/store/shift C long variables.
 */
#if (_MIPS_SZLONG == 32)
# define LONG_ADD	add
# define LONG_ADDI	addi
# define LONG_ADDU	addu
# define LONG_ADDIU	addiu
# define LONG_SUB	add
# define LONG_SUBI	subi
# define LONG_SUBU	subu
# define LONG_SUBIU	subu
# define LONG_L		lw
# define LONG_S		sw
# define LONG_SLL	sll
# define LONG_SLLV	sllv
# define LONG_SRL	srl
# define LONG_SRLV	srlv
# define LONG_SRA	sra
# define LONG_SRAV	srav
#endif

#if (_MIPS_SZLONG == 64)
# define LONG_ADD	dadd
# define LONG_ADDI	daddi
# define LONG_ADDU	daddu
# define LONG_ADDIU	daddiu
# define LONG_SUB	dadd
# define LONG_SUBI	dsubi
# define LONG_SUBU	dsubu
# define LONG_SUBIU	dsubu
# define LONG_L		ld
# define LONG_S		sd
# define LONG_SLL	dsll
# define LONG_SLLV	dsllv
# define LONG_SRL	dsrl
# define LONG_SRLV	dsrlv
# define LONG_SRA	dsra
# define LONG_SRAV	dsrav
#endif

/*
 * How to add/sub/load/store/shift pointers.
 */
#if (_MIPS_SIM == _ABIO32 && _MIPS_SZPTR == 32)
# define PTR_ADD	add
# define PTR_ADDI	addi
# define PTR_ADDU	addu
# define PTR_ADDIU	addiu
# define PTR_SUB	add
# define PTR_SUBI	subi
# define PTR_SUBU	subu
# define PTR_SUBIU	subu
# define PTR_L		lw
# define PTR_LA		la
# define PTR_S		sw
# define PTR_SLL	sll
# define PTR_SLLV	sllv
# define PTR_SRL	srl
# define PTR_SRLV	srlv
# define PTR_SRA	sra
# define PTR_SRAV	srav

# define PTR_SCALESHIFT	2
#endif

#if _MIPS_SIM == _ABIN32
# define PTR_ADD	add
# define PTR_ADDI	addi
# define PTR_ADDU	add /* no u */
# define PTR_ADDIU	addi /* no u */
# define PTR_SUB	add
# define PTR_SUBI	subi
# define PTR_SUBU	sub /* no u */
# define PTR_SUBIU	sub /* no u */
# define PTR_L		lw
# define PTR_LA		la
# define PTR_S		sw
# define PTR_SLL	sll
# define PTR_SLLV	sllv
# define PTR_SRL	srl
# define PTR_SRLV	srlv
# define PTR_SRA	sra
# define PTR_SRAV	srav

# define PTR_SCALESHIFT	2
#endif

#if (_MIPS_SIM == _ABIO32 && _MIPS_SZPTR == 64 /* o64??? */) \
    || _MIPS_SIM == _ABI64
# define PTR_ADD	dadd
# define PTR_ADDI	daddi
# define PTR_ADDU	daddu
# define PTR_ADDIU	daddiu
# define PTR_SUB	dadd
# define PTR_SUBI	dsubi
# define PTR_SUBU	dsubu
# define PTR_SUBIU	dsubu
# define PTR_L		ld
# define PTR_LA		dla
# define PTR_S		sd
# define PTR_SLL	dsll
# define PTR_SLLV	dsllv
# define PTR_SRL	dsrl
# define PTR_SRLV	dsrlv
# define PTR_SRA	dsra
# define PTR_SRAV	dsrav

# define PTR_SCALESHIFT	3
#endif

/*
 * Some cp0 registers were extended to 64bit for MIPS III.
 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS32)
# define MFC0	mfc0
# define MTC0	mtc0
#endif
#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
    (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
# define MFC0	dmfc0
# define MTC0	dmtc0
#endif

/* The MIPS archtectures do not have a uniform memory model.  Particular
   platforms may provide additional guarantees - for instance, the R4000
   LL and SC instructions implicitly perform a SYNC, and the 4K promises
   strong ordering.

   However, in the absence of those guarantees, we must assume weak ordering
   and SYNC explicitly where necessary.

   Some obsolete MIPS processors may not support the SYNC instruction.  This
   applies to "true" MIPS I processors; most of the processors which compile
   using MIPS I implement parts of MIPS II.  */

#ifndef MIPS_SYNC
# define MIPS_SYNC	sync
#endif

#endif /* sys/asm.h */
Commit	Line	Data
568035b7	1	/* Copyright (C) 1997-2013 Free Software Foundation, Inc.
74de4bb5 UD	2	This file is part of the GNU C Library.
	3	Contributed by Ralf Baechle <ralf@gnu.org>.
	4
	5	The GNU C Library is free software; you can redistribute it and/or
3214b89b AJ	6	modify it under the terms of the GNU Lesser General Public
	7	License as published by the Free Software Foundation; either
	8	version 2.1 of the License, or (at your option) any later version.
74de4bb5 UD	9
	10	The GNU C Library is distributed in the hope that it will be useful,
	11	but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
3214b89b	13	Lesser General Public License for more details.
74de4bb5	14
3214b89b	15	You should have received a copy of the GNU Lesser General Public
ab84e3ff PE	16	License along with the GNU C Library. If not, see
ab84e3ff PE	17	<http://www.gnu.org/licenses/>. */
74de4bb5 UD	18
	19	#ifndef _SYS_ASM_H
	20	#define _SYS_ASM_H
	21
	22	#include <sgidefs.h>
	23
	24	#ifndef CAT
2aee8949	25	# define __CAT(str1,str2) str1##str2
b1a0b02e	26	# define CAT(str1,str2) __CAT(str1,str2)
74de4bb5 UD	27	#endif
	28
	29	/*
	30	* Macros to handle different pointer/register sizes for 32/64-bit code
	31	*
	32	* 64 bit address space isn't used yet, so we may use the R3000 32 bit
	33	* defines for now.
	34	*/
73a227e2	35	#if _MIPS_SIM == _ABIO32 \|\| _MIPS_SIM == _ABIN32
b1a0b02e AO	36	# define PTR .word
	37	# define PTRSIZE 4
	38	# define PTRLOG 2
73a227e2	39	#elif _MIPS_SIM == _ABI64
b1a0b02e AO	40	# define PTR .dword
	41	# define PTRSIZE 8
	42	# define PTRLOG 3
	43	#endif
74de4bb5 UD	44
	45	/*
	46	* PIC specific declarations
	47	*/
73a227e2	48	#if _MIPS_SIM == _ABIO32
b1a0b02e AO	49	# ifdef __PIC__
b1a0b02e AO	50	# define CPRESTORE(register) \
74de4bb5	51	.cprestore register
b1a0b02e AO	52	# define CPLOAD(register) \
	53	.cpload register
	54	# else
	55	# define CPRESTORE(register)
	56	# define CPLOAD(register)
	57	# endif
	58
	59	# define CPADD(register) \
74de4bb5	60	.cpadd register
b1a0b02e AO	61
	62	/*
	63	* Set gp when at 1st instruction
	64	*/
	65	# define SETUP_GP \
	66	.set noreorder; \
	67	.cpload $25; \
	68	.set reorder
	69	/* Set gp when not at 1st instruction */
	70	# define SETUP_GPX(r) \
	71	.set noreorder; \
	72	move r, $31; /* Save old ra. */ \
	73	bal 10f; /* Find addr of cpload. */ \
	74	nop; \
	75	10: \
	76	.cpload $31; \
	77	move $31, r; \
	78	.set reorder
	79	# define SETUP_GPX_L(r, l) \
	80	.set noreorder; \
	81	move r, $31; /* Save old ra. */ \
	82	bal l; /* Find addr of cpload. */ \
	83	nop; \
	84	l: \
	85	.cpload $31; \
	86	move $31, r; \
	87	.set reorder
	88	# define SAVE_GP(x) \
	89	.cprestore x /* Save gp trigger t9/jalr conversion. */
	90	# define SETUP_GP64(a, b)
	91	# define SETUP_GPX64(a, b)
	92	# define SETUP_GPX64_L(cp_reg, ra_save, l)
	93	# define RESTORE_GP64
	94	# define USE_ALT_CP(a)
73a227e2	95	#else /* _MIPS_SIM == _ABI64 \|\| _MIPS_SIM == _ABIN32 */
b1a0b02e AO	96	/*
	97	* For callee-saved gp calling convention:
	98	*/
	99	# define SETUP_GP
	100	# define SETUP_GPX(r)
	101	# define SETUP_GPX_L(r, l)
	102	# define SAVE_GP(x)
	103
	104	# define SETUP_GP64(gpoffset, proc) \
	105	.cpsetup $25, gpoffset, proc
	106	# define SETUP_GPX64(cp_reg, ra_save) \
	107	move ra_save, $31; /* Save old ra. */ \
	108	.set noreorder; \
	109	bal 10f; /* Find addr of .cpsetup. */ \
	110	nop; \
	111	10: \
	112	.set reorder; \
	113	.cpsetup $31, cp_reg, 10b; \
	114	move $31, ra_save
	115	# define SETUP_GPX64_L(cp_reg, ra_save, l) \
	116	move ra_save, $31; /* Save old ra. */ \
	117	.set noreorder; \
	118	bal l; /* Find addr of .cpsetup. */ \
	119	nop; \
	120	l: \
	121	.set reorder; \
	122	.cpsetup $31, cp_reg, l; \
	123	move $31, ra_save
	124	# define RESTORE_GP64 \
	125	.cpreturn
	126	/* Use alternate register for context pointer. */
	127	# define USE_ALT_CP(reg) \
	128	.cplocal reg
73a227e2	129	#endif /* _MIPS_SIM != _ABIO32 */
b1a0b02e AO	130
	131	/*
	132	* Stack Frame Definitions
	133	*/
73a227e2	134	#if _MIPS_SIM == _ABIO32
b1a0b02e	135	# define NARGSAVE 4 /* Space for 4 argument registers must be allocated. */
74de4bb5	136	#endif
73a227e2	137	#if _MIPS_SIM == _ABI64 \|\| _MIPS_SIM == _ABIN32
b1a0b02e AO	138	# define NARGSAVE 0 /* No caller responsibilities. */
	139	#endif
	140
74de4bb5 UD	141
	142	/*
	143	* LEAF - declare leaf routine
	144	*/
	145	#define LEAF(symbol) \
	146	.globl symbol; \
	147	.align 2; \
	148	.type symbol,@function; \
	149	.ent symbol,0; \
	150	symbol: .frame sp,0,ra
	151
	152	/*
	153	* NESTED - declare nested routine entry point
	154	*/
	155	#define NESTED(symbol, framesize, rpc) \
	156	.globl symbol; \
	157	.align 2; \
	158	.type symbol,@function; \
	159	.ent symbol,0; \
	160	symbol: .frame sp, framesize, rpc
	161
	162	/*
	163	* END - mark end of function
	164	*/
b1a0b02e AO	165	#ifndef END
b1a0b02e AO	166	# define END(function) \
74de4bb5 UD	167	.end function; \
74de4bb5 UD	168	.size function,.-function
b1a0b02e	169	#endif
74de4bb5 UD	170
	171	/*
	172	* EXPORT - export definition of symbol
	173	*/
	174	#define EXPORT(symbol) \
	175	.globl symbol; \
	176	symbol:
	177
	178	/*
	179	* ABS - export absolute symbol
	180	*/
	181	#define ABS(symbol,value) \
	182	.globl symbol; \
	183	symbol = value
	184
	185	#define PANIC(msg) \
	186	.set push; \
	187	.set reorder; \
	188	la a0,8f; \
	189	jal panic; \
	190	9: b 9b; \
	191	.set pop; \
	192	TEXT(msg)
	193
	194	/*
	195	* Print formated string
	196	*/
	197	#define PRINT(string) \
	198	.set push; \
	199	.set reorder; \
	200	la a0,8f; \
	201	jal printk; \
	202	.set pop; \
	203	TEXT(string)
	204
	205	#define TEXT(msg) \
	206	.data; \
	207	8: .asciiz msg; \
	208	.previous;
	209
	210	/*
	211	* Build text tables
	212	*/
	213	#define TTABLE(string) \
	214	.text; \
	215	.word 1f; \
	216	.previous; \
	217	.data; \
	218	1: .asciz string; \
	219	.previous
	220
	221	/*
	222	* MIPS IV pref instruction.
	223	* Use with .set noreorder only!
	224	*
	225	* MIPS IV implementations are free to treat this as a nop. The R5000
	226	* is one of them. So we should have an option not to use this instruction.
	227	*/
f4e9c08c AO	228	#if (_MIPS_ISA == _MIPS_ISA_MIPS4) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS5) \|\| \
f4e9c08c AO	229	(_MIPS_ISA == _MIPS_ISA_MIPS32) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS64)
b1a0b02e	230	# define PREF(hint,addr) \
74de4bb5	231	pref hint,addr
b1a0b02e	232	# define PREFX(hint,addr) \
74de4bb5 UD	233	prefx hint,addr
74de4bb5 UD	234	#else
b290216f SE	235	# define PREF(hint,addr)
b290216f SE	236	# define PREFX(hint,addr)
74de4bb5 UD	237	#endif
	238
	239	/*
	240	* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
	241	*/
	242	#if _MIPS_ISA == _MIPS_ISA_MIPS1
b1a0b02e	243	# define MOVN(rd,rs,rt) \
74de4bb5 UD	244	.set push; \
74de4bb5 UD	245	.set reorder; \
b1a0b02e AO	246	beqz rt,9f; \
b1a0b02e AO	247	move rd,rs; \
74de4bb5 UD	248	.set pop; \
74de4bb5 UD	249	9:
b1a0b02e	250	# define MOVZ(rd,rs,rt) \
74de4bb5 UD	251	.set push; \
74de4bb5 UD	252	.set reorder; \
b1a0b02e AO	253	bnez rt,9f; \
b1a0b02e AO	254	move rd,rt; \
74de4bb5 UD	255	.set pop; \
	256	9:
	257	#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
	258	#if (_MIPS_ISA == _MIPS_ISA_MIPS2) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS3)
b1a0b02e	259	# define MOVN(rd,rs,rt) \
74de4bb5 UD	260	.set push; \
74de4bb5 UD	261	.set noreorder; \
b1a0b02e AO	262	bnezl rt,9f; \
b1a0b02e AO	263	move rd,rs; \
74de4bb5 UD	264	.set pop; \
74de4bb5 UD	265	9:
b1a0b02e	266	# define MOVZ(rd,rs,rt) \
74de4bb5 UD	267	.set push; \
74de4bb5 UD	268	.set noreorder; \
b1a0b02e AO	269	beqzl rt,9f; \
b1a0b02e AO	270	movz rd,rs; \
74de4bb5 UD	271	.set pop; \
	272	9:
	273	#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS3) */
f4e9c08c AO	274	#if (_MIPS_ISA == _MIPS_ISA_MIPS4) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS5) \|\| \
f4e9c08c AO	275	(_MIPS_ISA == _MIPS_ISA_MIPS32) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS64)
b1a0b02e	276	# define MOVN(rd,rs,rt) \
74de4bb5	277	movn rd,rs,rt
b1a0b02e	278	# define MOVZ(rd,rs,rt) \
74de4bb5 UD	279	movz rd,rs,rt
	280	#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS5) */
	281
	282	/*
	283	* Stack alignment
	284	*/
73a227e2	285	#if _MIPS_SIM == _ABI64 \|\| _MIPS_SIM == _ABIN32
b1a0b02e AO	286	# define ALSZ 15
b1a0b02e AO	287	# define ALMASK ~15
f4e9c08c AO	288	#else
	289	# define ALSZ 7
	290	# define ALMASK ~7
74de4bb5 UD	291	#endif
	292
	293	/*
	294	* Size of a register
	295	*/
73a227e2	296	#if _MIPS_SIM == _ABI64 \|\| _MIPS_SIM == _ABIN32
b1a0b02e	297	# define SZREG 8
74de4bb5	298	#else
b1a0b02e	299	# define SZREG 4
74de4bb5 UD	300	#endif
	301
	302	/*
	303	* Use the following macros in assemblercode to load/store registers,
	304	* pointers etc.
	305	*/
f4e9c08c	306	#if (SZREG == 4)
b1a0b02e AO	307	# define REG_S sw
	308	# define REG_L lw
	309	#else
	310	# define REG_S sd
	311	# define REG_L ld
74de4bb5 UD	312	#endif
	313
	314	/*
	315	* How to add/sub/load/store/shift C int variables.
	316	*/
	317	#if (_MIPS_SZINT == 32)
b1a0b02e AO	318	# define INT_ADD add
	319	# define INT_ADDI addi
	320	# define INT_ADDU addu
	321	# define INT_ADDIU addiu
	322	# define INT_SUB add
	323	# define INT_SUBI subi
	324	# define INT_SUBU subu
	325	# define INT_SUBIU subu
	326	# define INT_L lw
	327	# define INT_S sw
74de4bb5 UD	328	#endif
	329
	330	#if (_MIPS_SZINT == 64)
b1a0b02e AO	331	# define INT_ADD dadd
	332	# define INT_ADDI daddi
	333	# define INT_ADDU daddu
	334	# define INT_ADDIU daddiu
	335	# define INT_SUB dadd
	336	# define INT_SUBI dsubi
	337	# define INT_SUBU dsubu
	338	# define INT_SUBIU dsubu
	339	# define INT_L ld
	340	# define INT_S sd
74de4bb5 UD	341	#endif
	342
	343	/*
	344	* How to add/sub/load/store/shift C long variables.
	345	*/
	346	#if (_MIPS_SZLONG == 32)
b1a0b02e AO	347	# define LONG_ADD add
	348	# define LONG_ADDI addi
	349	# define LONG_ADDU addu
	350	# define LONG_ADDIU addiu
	351	# define LONG_SUB add
	352	# define LONG_SUBI subi
	353	# define LONG_SUBU subu
	354	# define LONG_SUBIU subu
	355	# define LONG_L lw
	356	# define LONG_S sw
	357	# define LONG_SLL sll
	358	# define LONG_SLLV sllv
	359	# define LONG_SRL srl
	360	# define LONG_SRLV srlv
	361	# define LONG_SRA sra
	362	# define LONG_SRAV srav
74de4bb5 UD	363	#endif
	364
	365	#if (_MIPS_SZLONG == 64)
b1a0b02e AO	366	# define LONG_ADD dadd
	367	# define LONG_ADDI daddi
	368	# define LONG_ADDU daddu
	369	# define LONG_ADDIU daddiu
	370	# define LONG_SUB dadd
	371	# define LONG_SUBI dsubi
	372	# define LONG_SUBU dsubu
	373	# define LONG_SUBIU dsubu
	374	# define LONG_L ld
	375	# define LONG_S sd
	376	# define LONG_SLL dsll
	377	# define LONG_SLLV dsllv
	378	# define LONG_SRL dsrl
	379	# define LONG_SRLV dsrlv
	380	# define LONG_SRA dsra
	381	# define LONG_SRAV dsrav
74de4bb5 UD	382	#endif
	383
	384	/*
	385	* How to add/sub/load/store/shift pointers.
	386	*/
73a227e2	387	#if (_MIPS_SIM == _ABIO32 && _MIPS_SZPTR == 32)
b1a0b02e AO	388	# define PTR_ADD add
	389	# define PTR_ADDI addi
	390	# define PTR_ADDU addu
	391	# define PTR_ADDIU addiu
	392	# define PTR_SUB add
	393	# define PTR_SUBI subi
	394	# define PTR_SUBU subu
	395	# define PTR_SUBIU subu
	396	# define PTR_L lw
	397	# define PTR_LA la
	398	# define PTR_S sw
	399	# define PTR_SLL sll
	400	# define PTR_SLLV sllv
	401	# define PTR_SRL srl
	402	# define PTR_SRLV srlv
	403	# define PTR_SRA sra
	404	# define PTR_SRAV srav
	405
	406	# define PTR_SCALESHIFT 2
74de4bb5 UD	407	#endif
74de4bb5 UD	408
73a227e2	409	#if _MIPS_SIM == _ABIN32
b1a0b02e AO	410	# define PTR_ADD add
	411	# define PTR_ADDI addi
	412	# define PTR_ADDU add /* no u */
	413	# define PTR_ADDIU addi /* no u */
	414	# define PTR_SUB add
	415	# define PTR_SUBI subi
	416	# define PTR_SUBU sub /* no u */
	417	# define PTR_SUBIU sub /* no u */
	418	# define PTR_L lw
	419	# define PTR_LA la
	420	# define PTR_S sw
	421	# define PTR_SLL sll
	422	# define PTR_SLLV sllv
	423	# define PTR_SRL srl
	424	# define PTR_SRLV srlv
	425	# define PTR_SRA sra
	426	# define PTR_SRAV srav
	427
	428	# define PTR_SCALESHIFT 2
	429	#endif
	430
73a227e2 AJ	431	#if (_MIPS_SIM == _ABIO32 && _MIPS_SZPTR == 64 /* o64??? */) \
73a227e2 AJ	432	\|\| _MIPS_SIM == _ABI64
b1a0b02e AO	433	# define PTR_ADD dadd
	434	# define PTR_ADDI daddi
	435	# define PTR_ADDU daddu
	436	# define PTR_ADDIU daddiu
	437	# define PTR_SUB dadd
	438	# define PTR_SUBI dsubi
	439	# define PTR_SUBU dsubu
	440	# define PTR_SUBIU dsubu
	441	# define PTR_L ld
	442	# define PTR_LA dla
	443	# define PTR_S sd
	444	# define PTR_SLL dsll
	445	# define PTR_SLLV dsllv
	446	# define PTR_SRL dsrl
	447	# define PTR_SRLV dsrlv
	448	# define PTR_SRA dsra
	449	# define PTR_SRAV dsrav
	450
	451	# define PTR_SCALESHIFT 3
74de4bb5 UD	452	#endif
	453
	454	/*
	455	* Some cp0 registers were extended to 64bit for MIPS III.
	456	*/
f4e9c08c AO	457	#if (_MIPS_ISA == _MIPS_ISA_MIPS1) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS2) \|\| \
f4e9c08c AO	458	(_MIPS_ISA == _MIPS_ISA_MIPS32)
b1a0b02e AO	459	# define MFC0 mfc0
b1a0b02e AO	460	# define MTC0 mtc0
74de4bb5 UD	461	#endif
74de4bb5 UD	462	#if (_MIPS_ISA == _MIPS_ISA_MIPS3) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS4) \|\| \
f4e9c08c	463	(_MIPS_ISA == _MIPS_ISA_MIPS5) \|\| (_MIPS_ISA == _MIPS_ISA_MIPS64)
b1a0b02e AO	464	# define MFC0 dmfc0
b1a0b02e AO	465	# define MTC0 dmtc0
74de4bb5 UD	466	#endif
74de4bb5 UD	467
63841821 AJ	468	/* The MIPS archtectures do not have a uniform memory model. Particular
	469	platforms may provide additional guarantees - for instance, the R4000
	470	LL and SC instructions implicitly perform a SYNC, and the 4K promises
	471	strong ordering.
	472
	473	However, in the absence of those guarantees, we must assume weak ordering
	474	and SYNC explicitly where necessary.
	475
	476	Some obsolete MIPS processors may not support the SYNC instruction. This
	477	applies to "true" MIPS I processors; most of the processors which compile
	478	using MIPS I implement parts of MIPS II. */
	479
	480	#ifndef MIPS_SYNC
	481	# define MIPS_SYNC sync
	482	#endif
	483
74de4bb5	484	#endif /* sys/asm.h */