[thirdparty/glibc.git] / sysdeps / powerpc / bits / atomic.h

/* Atomic operations.  PowerPC version.
   Copyright (C) 2003 Free Software Foundation, Inc.
   This file is part of the GNU C Library.
   Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2.1 of the License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with the GNU C Library; if not, write to the Free
   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
   02111-1307 USA.  */

#include <stdint.h>

typedef int8_t atomic8_t;
typedef uint8_t uatomic8_t;
typedef int_fast8_t atomic_fast8_t;
typedef uint_fast8_t uatomic_fast8_t;

typedef int16_t atomic16_t;
typedef uint16_t uatomic16_t;
typedef int_fast16_t atomic_fast16_t;
typedef uint_fast16_t uatomic_fast16_t;

typedef int32_t atomic32_t;
typedef uint32_t uatomic32_t;
typedef int_fast32_t atomic_fast32_t;
typedef uint_fast32_t uatomic_fast32_t;

typedef int64_t atomic64_t;
typedef uint64_t uatomic64_t;
typedef int_fast64_t atomic_fast64_t;
typedef uint_fast64_t uatomic_fast64_t;

typedef intptr_t atomicptr_t;
typedef uintptr_t uatomicptr_t;
typedef intmax_t atomic_max_t;
typedef uintmax_t uatomic_max_t;


#define __arch_compare_and_exchange_8_acq(mem, newval, oldval) \
  (abort (), 0)

#define __arch_compare_and_exchange_16_acq(mem, newval, oldval) \
  (abort (), 0)

#ifdef UP
#define __ARCH_ACQ_INSTR	""
#define __ARCH_REL_INSTR	""
#else
#define __ARCH_ACQ_INSTR	"isync"
#define __ARCH_REL_INSTR	"sync"
#endif

/*
 * XXX At present these have both acquire and release semantics.
 * Ultimately we should do separate _acq and _rel versions.
 */

/*
 * XXX this may not work properly on 64-bit if the register
 * containing oldval has the high half non-zero for some reason.
 */
#define __arch_compare_and_exchange_32_acq(mem, newval, oldval)	\
({								\
  unsigned int __tmp;						\
  __asm __volatile (__ARCH_REL_INSTR "\n"			\
		    "1:	lwarx	%0,0,%1\n"			\
		    "	subf.	%0,%2,%0\n"			\
		    "	bne	2f\n"				\
		    "	stwcx.	%3,0,%1\n"			\
		    "	bne-	1b\n"				\
		    "2:	" __ARCH_ACQ_INSTR			\
		    : "=&r" (__tmp)				\
		    : "r" (mem), "r" (oldval), "r" (newval)	\
		    : "cr0", "memory");				\
  __tmp != 0;							\
})

#ifdef __powerpc64__
#define __arch_compare_and_exchange_64_acq(mem, newval, oldval)	\
({								\
  unsigned long	__tmp;						\
  __asm __volatile (__ARCH_REL_INSTR "\n"			\
		    "1:	ldarx	%0,0,%1\n"			\
		    "	subf.	%0,%2,%0\n"			\
		    "	bne	2f\n"				\
		    "	stdcx.	%3,0,%1\n"			\
		    "	bne-	1b\n"				\
		    "2:	" __ARCH_ACQ_INSTR			\
		    : "=&r" (__tmp)				\
		    : "r" (mem), "r" (oldval), "r" (newval)	\
		    : "cr0", "memory");				\
  __tmp != 0;							\
})

#else /* powerpc32 */
#define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
  (abort (), 0)
#endif

#define atomic_full_barrier()	__asm ("sync" ::: "memory")
#ifdef __powerpc64__
#define atomic_read_barrier()	__asm ("lwsync" ::: "memory")
#else
#define atomic_read_barrier()	__asm ("sync" ::: "memory")
#endif
#define atomic_write_barrier()	__asm ("eieio" ::: "memory")
Commit	Line	Data
f3c13160 RM	1	/* Atomic operations. PowerPC version.
	2	Copyright (C) 2003 Free Software Foundation, Inc.
	3	This file is part of the GNU C Library.
	4	Contributed by Paul Mackerras <paulus@au.ibm.com>, 2003.
	5
	6	The GNU C Library is free software; you can redistribute it and/or
	7	modify it under the terms of the GNU Lesser General Public
	8	License as published by the Free Software Foundation; either
	9	version 2.1 of the License, or (at your option) any later version.
	10
	11	The GNU C Library is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	Lesser General Public License for more details.
	15
	16	You should have received a copy of the GNU Lesser General Public
	17	License along with the GNU C Library; if not, write to the Free
	18	Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
	19	02111-1307 USA. */
	20
	21	#include <stdint.h>
	22
	23	typedef int8_t atomic8_t;
	24	typedef uint8_t uatomic8_t;
	25	typedef int_fast8_t atomic_fast8_t;
	26	typedef uint_fast8_t uatomic_fast8_t;
	27
	28	typedef int16_t atomic16_t;
	29	typedef uint16_t uatomic16_t;
	30	typedef int_fast16_t atomic_fast16_t;
	31	typedef uint_fast16_t uatomic_fast16_t;
	32
	33	typedef int32_t atomic32_t;
	34	typedef uint32_t uatomic32_t;
	35	typedef int_fast32_t atomic_fast32_t;
	36	typedef uint_fast32_t uatomic_fast32_t;
	37
	38	typedef int64_t atomic64_t;
	39	typedef uint64_t uatomic64_t;
	40	typedef int_fast64_t atomic_fast64_t;
	41	typedef uint_fast64_t uatomic_fast64_t;
	42
	43	typedef intptr_t atomicptr_t;
	44	typedef uintptr_t uatomicptr_t;
	45	typedef intmax_t atomic_max_t;
	46	typedef uintmax_t uatomic_max_t;
	47
	48
	49	#define __arch_compare_and_exchange_8_acq(mem, newval, oldval) \
	50	(abort (), 0)
	51
	52	#define __arch_compare_and_exchange_16_acq(mem, newval, oldval) \
	53	(abort (), 0)
	54
	55	#ifdef UP
	56	#define __ARCH_ACQ_INSTR ""
	57	#define __ARCH_REL_INSTR ""
	58	#else
	59	#define __ARCH_ACQ_INSTR "isync"
	60	#define __ARCH_REL_INSTR "sync"
	61	#endif
	62
	63	/*
	64	* XXX At present these have both acquire and release semantics.
65	* Ultimately we should do separate _acq and _rel versions.
66	*/
67
68	/*
69	* XXX this may not work properly on 64-bit if the register
70	* containing oldval has the high half non-zero for some reason.
71	*/
72	#define __arch_compare_and_exchange_32_acq(mem, newval, oldval) \
73	({ \
74	unsigned int __tmp; \
75	__asm __volatile (__ARCH_REL_INSTR "\n" \
76	"1: lwarx %0,0,%1\n" \
77	" subf. %0,%2,%0\n" \
78	" bne 2f\n" \
79	" stwcx. %3,0,%1\n" \
80	" bne- 1b\n" \
81	"2: " __ARCH_ACQ_INSTR \
82	: "=&r" (__tmp) \
83	: "r" (mem), "r" (oldval), "r" (newval) \
84	: "cr0", "memory"); \
85	__tmp != 0; \
86	})
87
88	#ifdef __powerpc64__
89	#define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
90	({ \
91	unsigned long __tmp; \
92	__asm __volatile (__ARCH_REL_INSTR "\n" \
93	"1: ldarx %0,0,%1\n" \
94	" subf. %0,%2,%0\n" \
95	" bne 2f\n" \
96	" stdcx. %3,0,%1\n" \
97	" bne- 1b\n" \
98	"2: " __ARCH_ACQ_INSTR \
99	: "=&r" (__tmp) \
100	: "r" (mem), "r" (oldval), "r" (newval) \
101	: "cr0", "memory"); \
102	__tmp != 0; \
103	})
104
105	#else /* powerpc32 */
106	#define __arch_compare_and_exchange_64_acq(mem, newval, oldval) \
107	(abort (), 0)
108	#endif
109
110	#define atomic_full_barrier() __asm ("sync" ::: "memory")
111	#ifdef __powerpc64__
112	#define atomic_read_barrier() __asm ("lwsync" ::: "memory")
113	#else
114	#define atomic_read_barrier() __asm ("sync" ::: "memory")
115	#endif
116	#define atomic_write_barrier() __asm ("eieio" ::: "memory")