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d2e4346a SE |
1 | /* Initialize CPU feature data. AArch64 version. |
2 | This file is part of the GNU C Library. | |
04277e02 | 3 | Copyright (C) 2017-2019 Free Software Foundation, Inc. |
d2e4346a SE |
4 | |
5 | The GNU C Library is free software; you can redistribute it and/or | |
6 | modify it under the terms of the GNU Lesser General Public | |
7 | License as published by the Free Software Foundation; either | |
8 | version 2.1 of the License, or (at your option) any later version. | |
9 | ||
10 | The GNU C Library is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | Lesser General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU Lesser General Public | |
16 | License along with the GNU C Library; if not, see | |
5a82c748 | 17 | <https://www.gnu.org/licenses/>. */ |
d2e4346a SE |
18 | |
19 | #include <cpu-features.h> | |
20 | #include <sys/auxv.h> | |
f82e9672 | 21 | #include <elf/dl-hwcaps.h> |
d2e4346a | 22 | |
5a67c4fa SP |
23 | #define DCZID_DZP_MASK (1 << 4) |
24 | #define DCZID_BS_MASK (0xf) | |
25 | ||
28cfa3a4 SP |
26 | #if HAVE_TUNABLES |
27 | struct cpu_list | |
28 | { | |
29 | const char *name; | |
30 | uint64_t midr; | |
31 | }; | |
32 | ||
33 | static struct cpu_list cpu_list[] = { | |
9c9ec581 SE |
34 | {"falkor", 0x510FC000}, |
35 | {"thunderxt88", 0x430F0A10}, | |
36 | {"thunderx2t99", 0x431F0AF0}, | |
37 | {"thunderx2t99p1", 0x420F5160}, | |
fc2ba803 | 38 | {"phecda", 0x680F0000}, |
02f440c1 | 39 | {"ares", 0x411FD0C0}, |
07c3d1ec | 40 | {"emag", 0x503F0001}, |
9c9ec581 | 41 | {"generic", 0x0} |
28cfa3a4 SP |
42 | }; |
43 | ||
44 | static uint64_t | |
45 | get_midr_from_mcpu (const char *mcpu) | |
46 | { | |
47 | for (int i = 0; i < sizeof (cpu_list) / sizeof (struct cpu_list); i++) | |
f00bce74 | 48 | if (strcmp (mcpu, cpu_list[i].name) == 0) |
28cfa3a4 SP |
49 | return cpu_list[i].midr; |
50 | ||
51 | return UINT64_MAX; | |
52 | } | |
53 | #endif | |
54 | ||
d2e4346a SE |
55 | static inline void |
56 | init_cpu_features (struct cpu_features *cpu_features) | |
57 | { | |
28cfa3a4 SP |
58 | register uint64_t midr = UINT64_MAX; |
59 | ||
60 | #if HAVE_TUNABLES | |
61 | /* Get the tunable override. */ | |
dce452dc | 62 | const char *mcpu = TUNABLE_GET (glibc, cpu, name, const char *, NULL); |
28cfa3a4 SP |
63 | if (mcpu != NULL) |
64 | midr = get_midr_from_mcpu (mcpu); | |
65 | #endif | |
66 | ||
67 | /* If there was no useful tunable override, query the MIDR if the kernel | |
68 | allows it. */ | |
69 | if (midr == UINT64_MAX) | |
d2e4346a | 70 | { |
d0cd7980 | 71 | if (GLRO (dl_hwcap) & HWCAP_CPUID) |
28cfa3a4 SP |
72 | asm volatile ("mrs %0, midr_el1" : "=r"(midr)); |
73 | else | |
74 | midr = 0; | |
d2e4346a | 75 | } |
28cfa3a4 SP |
76 | |
77 | cpu_features->midr_el1 = midr; | |
5a67c4fa SP |
78 | |
79 | /* Check if ZVA is enabled. */ | |
80 | unsigned dczid; | |
81 | asm volatile ("mrs %0, dczid_el0" : "=r"(dczid)); | |
82 | ||
83 | if ((dczid & DCZID_DZP_MASK) == 0) | |
84 | cpu_features->zva_size = 4 << (dczid & DCZID_BS_MASK); | |
d2e4346a | 85 | } |