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cd815050 | 1 | /* Atomic operations. X86 version. |
04277e02 | 2 | Copyright (C) 2018-2019 Free Software Foundation, Inc. |
c10c099c | 3 | This file is part of the GNU C Library. |
c10c099c UD |
4 | |
5 | The GNU C Library is free software; you can redistribute it and/or | |
6 | modify it under the terms of the GNU Lesser General Public | |
7 | License as published by the Free Software Foundation; either | |
8 | version 2.1 of the License, or (at your option) any later version. | |
9 | ||
10 | The GNU C Library is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | Lesser General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU Lesser General Public | |
59ba27a6 PE |
16 | License along with the GNU C Library; if not, see |
17 | <http://www.gnu.org/licenses/>. */ | |
c10c099c | 18 | |
cd815050 L |
19 | #ifndef _X86_ATOMIC_MACHINE_H |
20 | #define _X86_ATOMIC_MACHINE_H 1 | |
c10c099c | 21 | |
9090848d | 22 | #include <stdint.h> |
cd815050 L |
23 | #include <tls.h> /* For tcbhead_t. */ |
24 | #include <libc-pointer-arith.h> /* For cast_to_integer. */ | |
c10c099c UD |
25 | |
26 | typedef int8_t atomic8_t; | |
27 | typedef uint8_t uatomic8_t; | |
28 | typedef int_fast8_t atomic_fast8_t; | |
29 | typedef uint_fast8_t uatomic_fast8_t; | |
30 | ||
31 | typedef int16_t atomic16_t; | |
32 | typedef uint16_t uatomic16_t; | |
33 | typedef int_fast16_t atomic_fast16_t; | |
34 | typedef uint_fast16_t uatomic_fast16_t; | |
35 | ||
36 | typedef int32_t atomic32_t; | |
37 | typedef uint32_t uatomic32_t; | |
38 | typedef int_fast32_t atomic_fast32_t; | |
39 | typedef uint_fast32_t uatomic_fast32_t; | |
40 | ||
41 | typedef int64_t atomic64_t; | |
42 | typedef uint64_t uatomic64_t; | |
43 | typedef int_fast64_t atomic_fast64_t; | |
44 | typedef uint_fast64_t uatomic_fast64_t; | |
45 | ||
46 | typedef intptr_t atomicptr_t; | |
47 | typedef uintptr_t uatomicptr_t; | |
48 | typedef intmax_t atomic_max_t; | |
49 | typedef uintmax_t uatomic_max_t; | |
50 | ||
51 | ||
bd4f43b4 | 52 | #ifndef LOCK_PREFIX |
c10c099c | 53 | # ifdef UP |
bd4f43b4 | 54 | # define LOCK_PREFIX /* nothing */ |
c10c099c | 55 | # else |
bd4f43b4 | 56 | # define LOCK_PREFIX "lock;" |
c10c099c UD |
57 | # endif |
58 | #endif | |
59 | ||
cd815050 L |
60 | #define USE_ATOMIC_COMPILER_BUILTINS 1 |
61 | ||
62 | #ifdef __x86_64__ | |
63 | # define __HAVE_64B_ATOMICS 1 | |
64 | # define SP_REG "rsp" | |
65 | # define SEG_REG "fs" | |
66 | # define BR_CONSTRAINT "q" | |
67 | # define IBR_CONSTRAINT "iq" | |
68 | #else | |
69 | # define __HAVE_64B_ATOMICS 0 | |
70 | # define SP_REG "esp" | |
71 | # define SEG_REG "gs" | |
72 | # define BR_CONSTRAINT "r" | |
73 | # define IBR_CONSTRAINT "ir" | |
74 | #endif | |
75 | #define ATOMIC_EXCHANGE_USES_CAS 0 | |
c10c099c | 76 | |
bc957d53 | 77 | #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ |
038a1a9f | 78 | __sync_val_compare_and_swap (mem, oldval, newval) |
bc957d53 | 79 | #define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \ |
038a1a9f | 80 | (! __sync_bool_compare_and_swap (mem, oldval, newval)) |
11bf311e UD |
81 | |
82 | ||
83 | #define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \ | |
84 | ({ __typeof (*mem) ret; \ | |
cd815050 L |
85 | __asm __volatile ("cmpl $0, %%" SEG_REG ":%P5\n\t" \ |
86 | "je 0f\n\t" \ | |
87 | "lock\n" \ | |
11bf311e UD |
88 | "0:\tcmpxchgb %b2, %1" \ |
89 | : "=a" (ret), "=m" (*mem) \ | |
cd815050 | 90 | : BR_CONSTRAINT (newval), "m" (*mem), "0" (oldval), \ |
11bf311e UD |
91 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
92 | ret; }) | |
93 | ||
94 | #define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \ | |
95 | ({ __typeof (*mem) ret; \ | |
cd815050 L |
96 | __asm __volatile ("cmpl $0, %%" SEG_REG ":%P5\n\t" \ |
97 | "je 0f\n\t" \ | |
98 | "lock\n" \ | |
11bf311e UD |
99 | "0:\tcmpxchgw %w2, %1" \ |
100 | : "=a" (ret), "=m" (*mem) \ | |
cd815050 | 101 | : BR_CONSTRAINT (newval), "m" (*mem), "0" (oldval), \ |
11bf311e UD |
102 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
103 | ret; }) | |
104 | ||
105 | #define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \ | |
106 | ({ __typeof (*mem) ret; \ | |
cd815050 L |
107 | __asm __volatile ("cmpl $0, %%" SEG_REG ":%P5\n\t" \ |
108 | "je 0f\n\t" \ | |
109 | "lock\n" \ | |
11bf311e UD |
110 | "0:\tcmpxchgl %2, %1" \ |
111 | : "=a" (ret), "=m" (*mem) \ | |
cd815050 L |
112 | : BR_CONSTRAINT (newval), "m" (*mem), "0" (oldval), \ |
113 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
11bf311e UD |
114 | ret; }) |
115 | ||
cd815050 L |
116 | #ifdef __x86_64__ |
117 | # define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \ | |
11bf311e UD |
118 | ({ __typeof (*mem) ret; \ |
119 | __asm __volatile ("cmpl $0, %%fs:%P5\n\t" \ | |
120 | "je 0f\n\t" \ | |
121 | "lock\n" \ | |
122 | "0:\tcmpxchgq %q2, %1" \ | |
123 | : "=a" (ret), "=m" (*mem) \ | |
c515fb51 L |
124 | : "q" ((atomic64_t) cast_to_integer (newval)), \ |
125 | "m" (*mem), \ | |
126 | "0" ((atomic64_t) cast_to_integer (oldval)), \ | |
11bf311e | 127 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
8099361e | 128 | ret; }) |
cd815050 L |
129 | # define do_exchange_and_add_val_64_acq(pfx, mem, value) 0 |
130 | # define do_add_val_64_acq(pfx, mem, value) do { } while (0) | |
131 | #else | |
132 | /* XXX We do not really need 64-bit compare-and-exchange. At least | |
133 | not in the moment. Using it would mean causing portability | |
134 | problems since not many other 32-bit architectures have support for | |
135 | such an operation. So don't define any code for now. If it is | |
136 | really going to be used the code below can be used on Intel Pentium | |
137 | and later, but NOT on i486. */ | |
138 | # define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \ | |
139 | ({ __typeof (*mem) ret = *(mem); \ | |
140 | __atomic_link_error (); \ | |
141 | ret = (newval); \ | |
142 | ret = (oldval); \ | |
143 | ret; }) | |
144 | ||
145 | # define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ | |
146 | ({ __typeof (*mem) ret = *(mem); \ | |
147 | __atomic_link_error (); \ | |
148 | ret = (newval); \ | |
149 | ret = (oldval); \ | |
150 | ret; }) | |
151 | ||
152 | # define do_exchange_and_add_val_64_acq(pfx, mem, value) \ | |
153 | ({ __typeof (value) __addval = (value); \ | |
154 | __typeof (*mem) __result; \ | |
155 | __typeof (mem) __memp = (mem); \ | |
156 | __typeof (*mem) __tmpval; \ | |
157 | __result = *__memp; \ | |
158 | do \ | |
159 | __tmpval = __result; \ | |
160 | while ((__result = pfx##_compare_and_exchange_val_64_acq \ | |
161 | (__memp, __result + __addval, __result)) == __tmpval); \ | |
162 | __result; }) | |
163 | ||
164 | # define do_add_val_64_acq(pfx, mem, value) \ | |
165 | { \ | |
166 | __typeof (value) __addval = (value); \ | |
167 | __typeof (mem) __memp = (mem); \ | |
168 | __typeof (*mem) __oldval = *__memp; \ | |
169 | __typeof (*mem) __tmpval; \ | |
170 | do \ | |
171 | __tmpval = __oldval; \ | |
172 | while ((__oldval = pfx##_compare_and_exchange_val_64_acq \ | |
173 | (__memp, __oldval + __addval, __oldval)) == __tmpval); \ | |
174 | } | |
175 | #endif | |
8099361e UD |
176 | |
177 | ||
f79466a8 | 178 | /* Note that we need no lock prefix. */ |
949ec764 | 179 | #define atomic_exchange_acq(mem, newvalue) \ |
f79466a8 UD |
180 | ({ __typeof (*mem) result; \ |
181 | if (sizeof (*mem) == 1) \ | |
182 | __asm __volatile ("xchgb %b0, %1" \ | |
a810e68c | 183 | : "=q" (result), "=m" (*mem) \ |
abfd53d1 | 184 | : "0" (newvalue), "m" (*mem)); \ |
f79466a8 UD |
185 | else if (sizeof (*mem) == 2) \ |
186 | __asm __volatile ("xchgw %w0, %1" \ | |
187 | : "=r" (result), "=m" (*mem) \ | |
abfd53d1 | 188 | : "0" (newvalue), "m" (*mem)); \ |
f79466a8 UD |
189 | else if (sizeof (*mem) == 4) \ |
190 | __asm __volatile ("xchgl %0, %1" \ | |
191 | : "=r" (result), "=m" (*mem) \ | |
abfd53d1 | 192 | : "0" (newvalue), "m" (*mem)); \ |
cd815050 | 193 | else if (__HAVE_64B_ATOMICS) \ |
f79466a8 UD |
194 | __asm __volatile ("xchgq %q0, %1" \ |
195 | : "=r" (result), "=m" (*mem) \ | |
c515fb51 L |
196 | : "0" ((atomic64_t) cast_to_integer (newvalue)), \ |
197 | "m" (*mem)); \ | |
cd815050 L |
198 | else \ |
199 | { \ | |
200 | result = 0; \ | |
201 | __atomic_link_error (); \ | |
202 | } \ | |
f79466a8 UD |
203 | result; }) |
204 | ||
205 | ||
cd815050 L |
206 | #define __arch_exchange_and_add_body(lock, pfx, mem, value) \ |
207 | ({ __typeof (*mem) __result; \ | |
208 | __typeof (value) __addval = (value); \ | |
c10c099c | 209 | if (sizeof (*mem) == 1) \ |
11bf311e | 210 | __asm __volatile (lock "xaddb %b0, %1" \ |
cd815050 L |
211 | : "=q" (__result), "=m" (*mem) \ |
212 | : "0" (__addval), "m" (*mem), \ | |
11bf311e | 213 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
c10c099c | 214 | else if (sizeof (*mem) == 2) \ |
11bf311e | 215 | __asm __volatile (lock "xaddw %w0, %1" \ |
cd815050 L |
216 | : "=r" (__result), "=m" (*mem) \ |
217 | : "0" (__addval), "m" (*mem), \ | |
11bf311e | 218 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
c10c099c | 219 | else if (sizeof (*mem) == 4) \ |
11bf311e | 220 | __asm __volatile (lock "xaddl %0, %1" \ |
cd815050 L |
221 | : "=r" (__result), "=m" (*mem) \ |
222 | : "0" (__addval), "m" (*mem), \ | |
11bf311e | 223 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
cd815050 | 224 | else if (__HAVE_64B_ATOMICS) \ |
11bf311e | 225 | __asm __volatile (lock "xaddq %q0, %1" \ |
cd815050 L |
226 | : "=r" (__result), "=m" (*mem) \ |
227 | : "0" ((atomic64_t) cast_to_integer (__addval)), \ | |
c515fb51 | 228 | "m" (*mem), \ |
11bf311e | 229 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
cd815050 L |
230 | else \ |
231 | __result = do_exchange_and_add_val_64_acq (pfx, (mem), __addval); \ | |
232 | __result; }) | |
c10c099c | 233 | |
bc957d53 | 234 | #define atomic_exchange_and_add(mem, value) \ |
038a1a9f | 235 | __sync_fetch_and_add (mem, value) |
11bf311e UD |
236 | |
237 | #define __arch_exchange_and_add_cprefix \ | |
cd815050 | 238 | "cmpl $0, %%" SEG_REG ":%P4\n\tje 0f\n\tlock\n0:\t" |
11bf311e UD |
239 | |
240 | #define catomic_exchange_and_add(mem, value) \ | |
cd815050 L |
241 | __arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, __arch_c, \ |
242 | mem, value) | |
11bf311e UD |
243 | |
244 | ||
cd815050 | 245 | #define __arch_add_body(lock, pfx, apfx, mem, value) \ |
11bf311e UD |
246 | do { \ |
247 | if (__builtin_constant_p (value) && (value) == 1) \ | |
248 | pfx##_increment (mem); \ | |
249 | else if (__builtin_constant_p (value) && (value) == -1) \ | |
250 | pfx##_decrement (mem); \ | |
251 | else if (sizeof (*mem) == 1) \ | |
252 | __asm __volatile (lock "addb %b1, %0" \ | |
253 | : "=m" (*mem) \ | |
cd815050 | 254 | : IBR_CONSTRAINT (value), "m" (*mem), \ |
11bf311e UD |
255 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
256 | else if (sizeof (*mem) == 2) \ | |
257 | __asm __volatile (lock "addw %w1, %0" \ | |
258 | : "=m" (*mem) \ | |
259 | : "ir" (value), "m" (*mem), \ | |
260 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
261 | else if (sizeof (*mem) == 4) \ | |
262 | __asm __volatile (lock "addl %1, %0" \ | |
263 | : "=m" (*mem) \ | |
264 | : "ir" (value), "m" (*mem), \ | |
265 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 | 266 | else if (__HAVE_64B_ATOMICS) \ |
11bf311e UD |
267 | __asm __volatile (lock "addq %q1, %0" \ |
268 | : "=m" (*mem) \ | |
c515fb51 L |
269 | : "ir" ((atomic64_t) cast_to_integer (value)), \ |
270 | "m" (*mem), \ | |
11bf311e | 271 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
cd815050 L |
272 | else \ |
273 | do_add_val_64_acq (apfx, (mem), (value)); \ | |
11bf311e | 274 | } while (0) |
c10c099c | 275 | |
cd815050 L |
276 | # define atomic_add(mem, value) \ |
277 | __arch_add_body (LOCK_PREFIX, atomic, __arch, mem, value) | |
11bf311e UD |
278 | |
279 | #define __arch_add_cprefix \ | |
cd815050 | 280 | "cmpl $0, %%" SEG_REG ":%P3\n\tje 0f\n\tlock\n0:\t" |
11bf311e UD |
281 | |
282 | #define catomic_add(mem, value) \ | |
cd815050 | 283 | __arch_add_body (__arch_add_cprefix, atomic, __arch_c, mem, value) |
c10c099c UD |
284 | |
285 | ||
286 | #define atomic_add_negative(mem, value) \ | |
287 | ({ unsigned char __result; \ | |
288 | if (sizeof (*mem) == 1) \ | |
bd4f43b4 | 289 | __asm __volatile (LOCK_PREFIX "addb %b2, %0; sets %1" \ |
c10c099c | 290 | : "=m" (*mem), "=qm" (__result) \ |
cd815050 | 291 | : IBR_CONSTRAINT (value), "m" (*mem)); \ |
c10c099c | 292 | else if (sizeof (*mem) == 2) \ |
bd4f43b4 | 293 | __asm __volatile (LOCK_PREFIX "addw %w2, %0; sets %1" \ |
c10c099c | 294 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 295 | : "ir" (value), "m" (*mem)); \ |
c10c099c | 296 | else if (sizeof (*mem) == 4) \ |
bd4f43b4 | 297 | __asm __volatile (LOCK_PREFIX "addl %2, %0; sets %1" \ |
c10c099c | 298 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 299 | : "ir" (value), "m" (*mem)); \ |
cd815050 | 300 | else if (__HAVE_64B_ATOMICS) \ |
bd4f43b4 | 301 | __asm __volatile (LOCK_PREFIX "addq %q2, %0; sets %1" \ |
c10c099c | 302 | : "=m" (*mem), "=qm" (__result) \ |
c515fb51 L |
303 | : "ir" ((atomic64_t) cast_to_integer (value)), \ |
304 | "m" (*mem)); \ | |
cd815050 L |
305 | else \ |
306 | __atomic_link_error (); \ | |
c10c099c UD |
307 | __result; }) |
308 | ||
309 | ||
310 | #define atomic_add_zero(mem, value) \ | |
311 | ({ unsigned char __result; \ | |
312 | if (sizeof (*mem) == 1) \ | |
bd4f43b4 | 313 | __asm __volatile (LOCK_PREFIX "addb %b2, %0; setz %1" \ |
c10c099c | 314 | : "=m" (*mem), "=qm" (__result) \ |
cd815050 | 315 | : IBR_CONSTRAINT (value), "m" (*mem)); \ |
c10c099c | 316 | else if (sizeof (*mem) == 2) \ |
bd4f43b4 | 317 | __asm __volatile (LOCK_PREFIX "addw %w2, %0; setz %1" \ |
c10c099c | 318 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 319 | : "ir" (value), "m" (*mem)); \ |
c10c099c | 320 | else if (sizeof (*mem) == 4) \ |
bd4f43b4 | 321 | __asm __volatile (LOCK_PREFIX "addl %2, %0; setz %1" \ |
c10c099c | 322 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 323 | : "ir" (value), "m" (*mem)); \ |
cd815050 | 324 | else if (__HAVE_64B_ATOMICS) \ |
bd4f43b4 | 325 | __asm __volatile (LOCK_PREFIX "addq %q2, %0; setz %1" \ |
c10c099c | 326 | : "=m" (*mem), "=qm" (__result) \ |
c515fb51 L |
327 | : "ir" ((atomic64_t) cast_to_integer (value)), \ |
328 | "m" (*mem)); \ | |
cd815050 L |
329 | else \ |
330 | __atomic_link_error (); \ | |
c10c099c UD |
331 | __result; }) |
332 | ||
333 | ||
cd815050 | 334 | #define __arch_increment_body(lock, pfx, mem) \ |
11bf311e UD |
335 | do { \ |
336 | if (sizeof (*mem) == 1) \ | |
337 | __asm __volatile (lock "incb %b0" \ | |
338 | : "=m" (*mem) \ | |
339 | : "m" (*mem), \ | |
340 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
341 | else if (sizeof (*mem) == 2) \ | |
342 | __asm __volatile (lock "incw %w0" \ | |
343 | : "=m" (*mem) \ | |
344 | : "m" (*mem), \ | |
345 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
346 | else if (sizeof (*mem) == 4) \ | |
347 | __asm __volatile (lock "incl %0" \ | |
348 | : "=m" (*mem) \ | |
349 | : "m" (*mem), \ | |
350 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 | 351 | else if (__HAVE_64B_ATOMICS) \ |
11bf311e UD |
352 | __asm __volatile (lock "incq %q0" \ |
353 | : "=m" (*mem) \ | |
354 | : "m" (*mem), \ | |
355 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 L |
356 | else \ |
357 | do_add_val_64_acq (pfx, mem, 1); \ | |
11bf311e UD |
358 | } while (0) |
359 | ||
cd815050 | 360 | #define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, __arch, mem) |
11bf311e UD |
361 | |
362 | #define __arch_increment_cprefix \ | |
cd815050 | 363 | "cmpl $0, %%" SEG_REG ":%P2\n\tje 0f\n\tlock\n0:\t" |
11bf311e UD |
364 | |
365 | #define catomic_increment(mem) \ | |
cd815050 | 366 | __arch_increment_body (__arch_increment_cprefix, __arch_c, mem) |
8099361e | 367 | |
c10c099c UD |
368 | |
369 | #define atomic_increment_and_test(mem) \ | |
370 | ({ unsigned char __result; \ | |
371 | if (sizeof (*mem) == 1) \ | |
cd815050 | 372 | __asm __volatile (LOCK_PREFIX "incb %b0; sete %b1" \ |
c10c099c | 373 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 374 | : "m" (*mem)); \ |
c10c099c | 375 | else if (sizeof (*mem) == 2) \ |
cd815050 | 376 | __asm __volatile (LOCK_PREFIX "incw %w0; sete %w1" \ |
c10c099c | 377 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 378 | : "m" (*mem)); \ |
c10c099c | 379 | else if (sizeof (*mem) == 4) \ |
bd4f43b4 | 380 | __asm __volatile (LOCK_PREFIX "incl %0; sete %1" \ |
c10c099c | 381 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 382 | : "m" (*mem)); \ |
cd815050 | 383 | else if (__HAVE_64B_ATOMICS) \ |
bd4f43b4 | 384 | __asm __volatile (LOCK_PREFIX "incq %q0; sete %1" \ |
c10c099c | 385 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 386 | : "m" (*mem)); \ |
cd815050 L |
387 | else \ |
388 | __atomic_link_error (); \ | |
c10c099c UD |
389 | __result; }) |
390 | ||
391 | ||
cd815050 | 392 | #define __arch_decrement_body(lock, pfx, mem) \ |
11bf311e UD |
393 | do { \ |
394 | if (sizeof (*mem) == 1) \ | |
395 | __asm __volatile (lock "decb %b0" \ | |
396 | : "=m" (*mem) \ | |
397 | : "m" (*mem), \ | |
398 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
399 | else if (sizeof (*mem) == 2) \ | |
400 | __asm __volatile (lock "decw %w0" \ | |
401 | : "=m" (*mem) \ | |
402 | : "m" (*mem), \ | |
403 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
404 | else if (sizeof (*mem) == 4) \ | |
405 | __asm __volatile (lock "decl %0" \ | |
406 | : "=m" (*mem) \ | |
407 | : "m" (*mem), \ | |
408 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 | 409 | else if (__HAVE_64B_ATOMICS) \ |
11bf311e UD |
410 | __asm __volatile (lock "decq %q0" \ |
411 | : "=m" (*mem) \ | |
412 | : "m" (*mem), \ | |
413 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 L |
414 | else \ |
415 | do_add_val_64_acq (pfx, mem, -1); \ | |
11bf311e UD |
416 | } while (0) |
417 | ||
cd815050 | 418 | #define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, __arch, mem) |
11bf311e UD |
419 | |
420 | #define __arch_decrement_cprefix \ | |
cd815050 | 421 | "cmpl $0, %%" SEG_REG ":%P2\n\tje 0f\n\tlock\n0:\t" |
11bf311e UD |
422 | |
423 | #define catomic_decrement(mem) \ | |
cd815050 | 424 | __arch_decrement_body (__arch_decrement_cprefix, __arch_c, mem) |
8099361e | 425 | |
c10c099c UD |
426 | |
427 | #define atomic_decrement_and_test(mem) \ | |
428 | ({ unsigned char __result; \ | |
429 | if (sizeof (*mem) == 1) \ | |
bd4f43b4 | 430 | __asm __volatile (LOCK_PREFIX "decb %b0; sete %1" \ |
c10c099c | 431 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 432 | : "m" (*mem)); \ |
c10c099c | 433 | else if (sizeof (*mem) == 2) \ |
bd4f43b4 | 434 | __asm __volatile (LOCK_PREFIX "decw %w0; sete %1" \ |
c10c099c | 435 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 436 | : "m" (*mem)); \ |
c10c099c | 437 | else if (sizeof (*mem) == 4) \ |
bd4f43b4 | 438 | __asm __volatile (LOCK_PREFIX "decl %0; sete %1" \ |
c10c099c | 439 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 440 | : "m" (*mem)); \ |
c10c099c | 441 | else \ |
bd4f43b4 | 442 | __asm __volatile (LOCK_PREFIX "decq %q0; sete %1" \ |
c10c099c | 443 | : "=m" (*mem), "=qm" (__result) \ |
abfd53d1 | 444 | : "m" (*mem)); \ |
c10c099c UD |
445 | __result; }) |
446 | ||
447 | ||
448 | #define atomic_bit_set(mem, bit) \ | |
11bf311e UD |
449 | do { \ |
450 | if (sizeof (*mem) == 1) \ | |
451 | __asm __volatile (LOCK_PREFIX "orb %b2, %0" \ | |
452 | : "=m" (*mem) \ | |
cd815050 | 453 | : "m" (*mem), IBR_CONSTRAINT (1L << (bit))); \ |
11bf311e UD |
454 | else if (sizeof (*mem) == 2) \ |
455 | __asm __volatile (LOCK_PREFIX "orw %w2, %0" \ | |
456 | : "=m" (*mem) \ | |
457 | : "m" (*mem), "ir" (1L << (bit))); \ | |
458 | else if (sizeof (*mem) == 4) \ | |
459 | __asm __volatile (LOCK_PREFIX "orl %2, %0" \ | |
460 | : "=m" (*mem) \ | |
461 | : "m" (*mem), "ir" (1L << (bit))); \ | |
462 | else if (__builtin_constant_p (bit) && (bit) < 32) \ | |
463 | __asm __volatile (LOCK_PREFIX "orq %2, %0" \ | |
464 | : "=m" (*mem) \ | |
465 | : "m" (*mem), "i" (1L << (bit))); \ | |
cd815050 | 466 | else if (__HAVE_64B_ATOMICS) \ |
11bf311e UD |
467 | __asm __volatile (LOCK_PREFIX "orq %q2, %0" \ |
468 | : "=m" (*mem) \ | |
469 | : "m" (*mem), "r" (1UL << (bit))); \ | |
cd815050 L |
470 | else \ |
471 | __atomic_link_error (); \ | |
11bf311e | 472 | } while (0) |
c10c099c UD |
473 | |
474 | ||
475 | #define atomic_bit_test_set(mem, bit) \ | |
476 | ({ unsigned char __result; \ | |
477 | if (sizeof (*mem) == 1) \ | |
bd4f43b4 | 478 | __asm __volatile (LOCK_PREFIX "btsb %3, %1; setc %0" \ |
c10c099c | 479 | : "=q" (__result), "=m" (*mem) \ |
cd815050 | 480 | : "m" (*mem), IBR_CONSTRAINT (bit)); \ |
c10c099c | 481 | else if (sizeof (*mem) == 2) \ |
bd4f43b4 | 482 | __asm __volatile (LOCK_PREFIX "btsw %3, %1; setc %0" \ |
c10c099c | 483 | : "=q" (__result), "=m" (*mem) \ |
002ff853 | 484 | : "m" (*mem), "ir" (bit)); \ |
c10c099c | 485 | else if (sizeof (*mem) == 4) \ |
bd4f43b4 | 486 | __asm __volatile (LOCK_PREFIX "btsl %3, %1; setc %0" \ |
c10c099c | 487 | : "=q" (__result), "=m" (*mem) \ |
002ff853 | 488 | : "m" (*mem), "ir" (bit)); \ |
cd815050 | 489 | else if (__HAVE_64B_ATOMICS) \ |
bd4f43b4 | 490 | __asm __volatile (LOCK_PREFIX "btsq %3, %1; setc %0" \ |
c10c099c | 491 | : "=q" (__result), "=m" (*mem) \ |
002ff853 | 492 | : "m" (*mem), "ir" (bit)); \ |
cd815050 L |
493 | else \ |
494 | __atomic_link_error (); \ | |
c10c099c | 495 | __result; }) |
f377d022 UD |
496 | |
497 | ||
6c03cd11 | 498 | #define __arch_and_body(lock, mem, mask) \ |
11bf311e UD |
499 | do { \ |
500 | if (sizeof (*mem) == 1) \ | |
6c03cd11 | 501 | __asm __volatile (lock "andb %b1, %0" \ |
11bf311e | 502 | : "=m" (*mem) \ |
cd815050 | 503 | : IBR_CONSTRAINT (mask), "m" (*mem), \ |
6c03cd11 | 504 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
11bf311e | 505 | else if (sizeof (*mem) == 2) \ |
6c03cd11 | 506 | __asm __volatile (lock "andw %w1, %0" \ |
11bf311e | 507 | : "=m" (*mem) \ |
6c03cd11 UD |
508 | : "ir" (mask), "m" (*mem), \ |
509 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
11bf311e | 510 | else if (sizeof (*mem) == 4) \ |
6c03cd11 | 511 | __asm __volatile (lock "andl %1, %0" \ |
11bf311e | 512 | : "=m" (*mem) \ |
6c03cd11 UD |
513 | : "ir" (mask), "m" (*mem), \ |
514 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 | 515 | else if (__HAVE_64B_ATOMICS) \ |
6c03cd11 | 516 | __asm __volatile (lock "andq %q1, %0" \ |
11bf311e | 517 | : "=m" (*mem) \ |
6c03cd11 UD |
518 | : "ir" (mask), "m" (*mem), \ |
519 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 L |
520 | else \ |
521 | __atomic_link_error (); \ | |
11bf311e UD |
522 | } while (0) |
523 | ||
6c03cd11 | 524 | #define __arch_cprefix \ |
cd815050 | 525 | "cmpl $0, %%" SEG_REG ":%P3\n\tje 0f\n\tlock\n0:\t" |
6c03cd11 UD |
526 | |
527 | #define atomic_and(mem, mask) __arch_and_body (LOCK_PREFIX, mem, mask) | |
528 | ||
529 | #define catomic_and(mem, mask) __arch_and_body (__arch_cprefix, mem, mask) | |
530 | ||
11bf311e | 531 | |
cd815050 | 532 | #define __arch_or_body(lock, mem, mask) \ |
11bf311e UD |
533 | do { \ |
534 | if (sizeof (*mem) == 1) \ | |
a810e68c | 535 | __asm __volatile (lock "orb %b1, %0" \ |
11bf311e | 536 | : "=m" (*mem) \ |
cd815050 | 537 | : IBR_CONSTRAINT (mask), "m" (*mem), \ |
11bf311e UD |
538 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
539 | else if (sizeof (*mem) == 2) \ | |
77151937 | 540 | __asm __volatile (lock "orw %w1, %0" \ |
11bf311e UD |
541 | : "=m" (*mem) \ |
542 | : "ir" (mask), "m" (*mem), \ | |
543 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
544 | else if (sizeof (*mem) == 4) \ | |
545 | __asm __volatile (lock "orl %1, %0" \ | |
546 | : "=m" (*mem) \ | |
547 | : "ir" (mask), "m" (*mem), \ | |
548 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 | 549 | else if (__HAVE_64B_ATOMICS) \ |
77151937 | 550 | __asm __volatile (lock "orq %q1, %0" \ |
11bf311e UD |
551 | : "=m" (*mem) \ |
552 | : "ir" (mask), "m" (*mem), \ | |
553 | "i" (offsetof (tcbhead_t, multiple_threads))); \ | |
cd815050 L |
554 | else \ |
555 | __atomic_link_error (); \ | |
11bf311e UD |
556 | } while (0) |
557 | ||
558 | #define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask) | |
559 | ||
6c03cd11 | 560 | #define catomic_or(mem, mask) __arch_or_body (__arch_cprefix, mem, mask) |
c47ca964 TR |
561 | |
562 | /* We don't use mfence because it is supposedly slower due to having to | |
563 | provide stronger guarantees (e.g., regarding self-modifying code). */ | |
564 | #define atomic_full_barrier() \ | |
cd815050 | 565 | __asm __volatile (LOCK_PREFIX "orl $0, (%%" SP_REG ")" ::: "memory") |
c47ca964 TR |
566 | #define atomic_read_barrier() __asm ("" ::: "memory") |
567 | #define atomic_write_barrier() __asm ("" ::: "memory") | |
9090848d | 568 | |
cd815050 L |
569 | #define atomic_spin_nop() __asm ("pause") |
570 | ||
9090848d | 571 | #endif /* atomic-machine.h */ |