sysdeps/powerpc/fpu_control.h

   1 /* FPU control word definitions.  PowerPC version.
   2    Copyright (C) 1996-2019 Free Software Foundation, Inc.
   3    This file is part of the GNU C Library.
   4
   5    The GNU C Library is free software; you can redistribute it and/or
   6    modify it under the terms of the GNU Lesser General Public
   7    License as published by the Free Software Foundation; either
   8    version 2.1 of the License, or (at your option) any later version.
   9
  10    The GNU C Library is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13    Lesser General Public License for more details.
  14
  15    You should have received a copy of the GNU Lesser General Public
  16    License along with the GNU C Library; if not, see
  17    <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef _FPU_CONTROL_H
  20 #define _FPU_CONTROL_H
  21
  22 #if defined __SPE__ || (defined __NO_FPRS__ && !defined _SOFT_FLOAT)
  23 # error "SPE/e500 is no longer supported"
  24 #endif
  25
  26 #ifdef _SOFT_FLOAT
  27
  28 # define _FPU_RESERVED 0xffffffff
  29 # define _FPU_DEFAULT  0x00000000 /* Default value.  */
  30 typedef unsigned int fpu_control_t;
  31 # define _FPU_GETCW(cw) (cw) = 0
  32 # define _FPU_SETCW(cw) (void) (cw)
  33 extern fpu_control_t __fpu_control;
  34
  35 #else /* PowerPC 6xx floating-point.  */
  36
  37 /* rounding control */
  38 # define _FPU_RC_NEAREST 0x00   /* RECOMMENDED */
  39 # define _FPU_RC_DOWN    0x03
  40 # define _FPU_RC_UP      0x02
  41 # define _FPU_RC_ZERO    0x01
  42
  43 # define _FPU_MASK_RC (_FPU_RC_NEAREST|_FPU_RC_DOWN|_FPU_RC_UP|_FPU_RC_ZERO)
  44
  45 # define _FPU_MASK_NI  0x04 /* non-ieee mode */
  46
  47 /* masking of interrupts */
  48 # define _FPU_MASK_ZM  0x10 /* zero divide */
  49 # define _FPU_MASK_OM  0x40 /* overflow */
  50 # define _FPU_MASK_UM  0x20 /* underflow */
  51 # define _FPU_MASK_XM  0x08 /* inexact */
  52 # define _FPU_MASK_IM  0x80 /* invalid operation */
  53
  54 # define _FPU_RESERVED 0xffffff00 /* These bits are reserved are not changed. */
  55
  56 /* The fdlibm code requires no interrupts for exceptions.  */
  57 # define _FPU_DEFAULT  0x00000000 /* Default value.  */
  58
  59 /* IEEE:  same as above, but (some) exceptions;
  60    we leave the 'inexact' exception off.
  61  */
  62 # define _FPU_IEEE     0x000000f0
  63
  64 /* Type of the control word.  */
  65 typedef unsigned int fpu_control_t;
  66
  67 /* Macros for accessing the hardware control word.  */
  68 # define __FPU_MFFS()                                           \
  69   ({register double __fr;                                       \
  70     __asm__ ("mffs %0" : "=f" (__fr));                          \
  71     __fr;                                                       \
  72   })
  73
  74 # define _FPU_GETCW(cw)                                         \
  75   ({union { double __d; unsigned long long __ll; } __u;         \
  76     __u.__d = __FPU_MFFS();                                     \
  77     (cw) = (fpu_control_t) __u.__ll;                            \
  78     (fpu_control_t) __u.__ll;                                   \
  79   })
  80
  81 #ifdef _ARCH_PWR9
  82 # define __FPU_MFFSL()                                          \
  83   ({register double __fr;                                       \
  84     __asm__ ("mffsl %0" : "=f" (__fr));                         \
  85     __fr;                                                       \
  86   })
  87 #else
  88 # define __FPU_MFFSL() __FPU_MFFS()
  89 #endif
  90
  91 # define _FPU_GET_RC()                                          \
  92   ({union { double __d; unsigned long long __ll; } __u;         \
  93     __u.__d = __FPU_MFFSL();                                    \
  94     __u.__ll &= _FPU_MASK_RC;                                   \
  95     (fpu_control_t) __u.__ll;                                   \
  96   })
  97
  98 # define _FPU_SETCW(cw)                                         \
  99   { union { double __d; unsigned long long __ll; } __u;         \
 100     register double __fr;                                       \
 101     __u.__ll = 0xfff80000LL << 32; /* This is a QNaN.  */       \
 102     __u.__ll |= (cw) & 0xffffffffLL;                            \
 103     __fr = __u.__d;                                             \
 104     __asm__ ("mtfsf 255,%0" : : "f" (__fr));                    \
 105   }
 106
 107 /* Default control word set at startup.  */
 108 extern fpu_control_t __fpu_control;
 109
 110 #endif /* PowerPC 6xx floating-point.  */
 111
 112 #endif /* _FPU_CONTROL_H */